1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __Q6PRM_H__ 4 #define __Q6PRM_H__ 5 6 #define LPAIF_MI2S_MCLK 1 7 #define LPAIF_MI2S_BCLK 2 8 9 /* Clock ID for Primary I2S IBIT */ 10 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 11 /* Clock ID for Primary I2S EBIT */ 12 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 13 /* Clock ID for Secondary I2S IBIT */ 14 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 15 /* Clock ID for Secondary I2S EBIT */ 16 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 17 /* Clock ID for Tertiary I2S IBIT */ 18 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 19 /* Clock ID for Tertiary I2S EBIT */ 20 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 21 /* Clock ID for Quartnery I2S IBIT */ 22 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 23 /* Clock ID for Quartnery I2S EBIT */ 24 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 25 /* Clock ID for Speaker I2S IBIT */ 26 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 27 /* Clock ID for Speaker I2S EBIT */ 28 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 29 /* Clock ID for Speaker I2S OSR */ 30 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A 31 32 /* Clock ID for QUINARY I2S IBIT */ 33 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B 34 /* Clock ID for QUINARY I2S EBIT */ 35 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C 36 /* Clock ID for SENARY I2S IBIT */ 37 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D 38 /* Clock ID for SENARY I2S EBIT */ 39 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E 40 /* Clock ID for INT0 I2S IBIT */ 41 #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F 42 /* Clock ID for INT1 I2S IBIT */ 43 #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 44 /* Clock ID for INT2 I2S IBIT */ 45 #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 46 /* Clock ID for INT3 I2S IBIT */ 47 #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 48 /* Clock ID for INT4 I2S IBIT */ 49 #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 50 /* Clock ID for INT5 I2S IBIT */ 51 #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 52 /* Clock ID for INT6 I2S IBIT */ 53 #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 54 55 /* Clock ID for QUINARY MI2S OSR CLK */ 56 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 57 58 /* Clock ID for MCLK1 */ 59 #define Q6PRM_LPASS_CLK_ID_MCLK_1 0x300 60 /* Clock ID for MCLK2 */ 61 #define Q6PRM_LPASS_CLK_ID_MCLK_2 0x301 62 /* Clock ID for MCLK3 */ 63 #define Q6PRM_LPASS_CLK_ID_MCLK_3 0x302 64 /* Clock ID for MCLK4 */ 65 #define Q6PRM_LPASS_CLK_ID_MCLK_4 0x303 66 /* Clock ID for MCLK5 */ 67 #define Q6PRM_LPASS_CLK_ID_MCLK_5 0x304 68 69 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305 70 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306 71 72 #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307 73 #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308 74 75 #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c 76 #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d 77 78 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e 79 #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f 80 81 /* Clock ID for MCLK for WSA2 core */ 82 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310 83 /* Clock ID for NPL MCLK for WSA2 core */ 84 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311 85 /* Clock ID for RX Core TX MCLK */ 86 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312 87 /* Clock ID for RX CORE TX 2X MCLK */ 88 #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313 89 /* Clock ID for WSA core TX MCLK */ 90 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314 91 /* Clock ID for WSA core TX 2X MCLK */ 92 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315 93 /* Clock ID for WSA2 core TX MCLK */ 94 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316 95 /* Clock ID for WSA2 core TX 2X MCLK */ 96 #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317 97 /* Clock ID for RX CORE MCLK2 2X MCLK */ 98 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318 99 100 #define Q6PRM_LPASS_CLK_ID_QAIF_IF0_IBIT 0x500 101 #define Q6PRM_LPASS_CLK_ID_QAIF_IF0_EBIT 0x501 102 #define Q6PRM_LPASS_CLK_ID_QAIF_IF1_IBIT 0x502 103 #define Q6PRM_LPASS_CLK_ID_QAIF_IF1_EBIT 0x503 104 #define Q6PRM_LPASS_CLK_ID_QAIF_IF2_IBIT 0x504 105 #define Q6PRM_LPASS_CLK_ID_QAIF_IF2_EBIT 0x505 106 #define Q6PRM_LPASS_CLK_ID_QAIF_IF3_IBIT 0x506 107 #define Q6PRM_LPASS_CLK_ID_QAIF_IF3_EBIT 0x507 108 #define Q6PRM_LPASS_CLK_ID_QAIF_IF4_IBIT 0x508 109 #define Q6PRM_LPASS_CLK_ID_QAIF_IF4_EBIT 0x509 110 #define Q6PRM_LPASS_CLK_ID_QAIF_IF5_IBIT 0x50A 111 #define Q6PRM_LPASS_CLK_ID_QAIF_IF5_EBIT 0x50B 112 #define Q6PRM_LPASS_CLK_ID_QAIF_IF6_IBIT 0x50C 113 #define Q6PRM_LPASS_CLK_ID_QAIF_IF6_EBIT 0x50D 114 #define Q6PRM_LPASS_CLK_ID_QAIF_IF7_IBIT 0x50E 115 #define Q6PRM_LPASS_CLK_ID_QAIF_IF7_EBIT 0x50F 116 #define Q6PRM_LPASS_CLK_ID_QAIF_IF8_IBIT 0x510 117 #define Q6PRM_LPASS_CLK_ID_QAIF_IF8_EBIT 0x511 118 #define Q6PRM_LPASS_CLK_ID_QAIF_IF9_IBIT 0x512 119 #define Q6PRM_LPASS_CLK_ID_QAIF_IF9_EBIT 0x513 120 #define Q6PRM_LPASS_CLK_ID_QAIF_IF10_IBIT 0x514 121 #define Q6PRM_LPASS_CLK_ID_QAIF_IF10_EBIT 0x515 122 #define Q6PRM_LPASS_CLK_ID_QAIF_IF11_IBIT 0x516 123 #define Q6PRM_LPASS_CLK_ID_QAIF_IF11_EBIT 0x517 124 #define Q6PRM_LPASS_CLK_ID_QAIF_IF12_IBIT 0x518 125 #define Q6PRM_LPASS_CLK_ID_QAIF_IF12_EBIT 0x519 126 #define Q6PRM_LPASS_CLK_ID_VA_QAIF_IF0_IBIT 0x550 127 #define Q6PRM_LPASS_CLK_ID_VA_QAIF_IF0_EBIT 0x551 128 129 #define Q6PRM_LPASS_CLK_SRC_INTERNAL 1 130 #define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0 131 #define Q6PRM_HW_CORE_ID_LPASS 1 132 #define Q6PRM_HW_CORE_ID_DCODEC 2 133 #define Q6PRM_HW_LPR_VOTE 3 134 135 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, 136 int clk_root, unsigned int freq); 137 int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 138 const char *client_name, uint32_t *client_handle); 139 int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 140 uint32_t client_handle); 141 #endif /* __Q6PRM_H__ */ 142