1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __Q6AFE_H__ 4 #define __Q6AFE_H__ 5 #include "../common.h" 6 7 #define AFE_PORT_MAX (LPASS_MAX_PORT) 8 9 #define MSM_AFE_PORT_TYPE_RX 0 10 #define MSM_AFE_PORT_TYPE_TX 1 11 #define AFE_MAX_PORTS AFE_PORT_MAX 12 13 #define Q6AFE_MAX_MI2S_LINES 4 14 15 #define AFE_MAX_CHAN_COUNT 8 16 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 17 18 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 19 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 20 21 #define LPAIF_DIG_CLK 1 22 #define LPAIF_BIT_CLK 2 23 #define LPAIF_OSR_CLK 3 24 25 /* Clock ID for Primary I2S IBIT */ 26 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 27 /* Clock ID for Primary I2S EBIT */ 28 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 29 /* Clock ID for Secondary I2S IBIT */ 30 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 31 /* Clock ID for Secondary I2S EBIT */ 32 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 33 /* Clock ID for Tertiary I2S IBIT */ 34 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 35 /* Clock ID for Tertiary I2S EBIT */ 36 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 37 /* Clock ID for Quartnery I2S IBIT */ 38 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 39 /* Clock ID for Quartnery I2S EBIT */ 40 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 41 /* Clock ID for Speaker I2S IBIT */ 42 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 43 /* Clock ID for Speaker I2S EBIT */ 44 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 45 /* Clock ID for Speaker I2S OSR */ 46 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A 47 48 /* Clock ID for QUINARY I2S IBIT */ 49 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B 50 /* Clock ID for QUINARY I2S EBIT */ 51 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C 52 /* Clock ID for SENARY I2S IBIT */ 53 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D 54 /* Clock ID for SENARY I2S EBIT */ 55 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E 56 /* Clock ID for INT0 I2S IBIT */ 57 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F 58 /* Clock ID for INT1 I2S IBIT */ 59 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 60 /* Clock ID for INT2 I2S IBIT */ 61 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 62 /* Clock ID for INT3 I2S IBIT */ 63 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 64 /* Clock ID for INT4 I2S IBIT */ 65 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 66 /* Clock ID for INT5 I2S IBIT */ 67 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 68 /* Clock ID for INT6 I2S IBIT */ 69 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 70 71 /* Clock ID for QUINARY MI2S OSR CLK */ 72 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 73 74 /* Clock ID for Primary PCM IBIT */ 75 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200 76 /* Clock ID for Primary PCM EBIT */ 77 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201 78 /* Clock ID for Secondary PCM IBIT */ 79 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202 80 /* Clock ID for Secondary PCM EBIT */ 81 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203 82 /* Clock ID for Tertiary PCM IBIT */ 83 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204 84 /* Clock ID for Tertiary PCM EBIT */ 85 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205 86 /* Clock ID for Quartery PCM IBIT */ 87 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206 88 /* Clock ID for Quartery PCM EBIT */ 89 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207 90 /* Clock ID for Quinary PCM IBIT */ 91 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208 92 /* Clock ID for Quinary PCM EBIT */ 93 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209 94 /* Clock ID for QUINARY PCM OSR */ 95 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A 96 97 /** Clock ID for Primary TDM IBIT */ 98 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200 99 /** Clock ID for Primary TDM EBIT */ 100 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201 101 /** Clock ID for Secondary TDM IBIT */ 102 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202 103 /** Clock ID for Secondary TDM EBIT */ 104 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203 105 /** Clock ID for Tertiary TDM IBIT */ 106 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204 107 /** Clock ID for Tertiary TDM EBIT */ 108 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205 109 /** Clock ID for Quartery TDM IBIT */ 110 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206 111 /** Clock ID for Quartery TDM EBIT */ 112 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207 113 /** Clock ID for Quinary TDM IBIT */ 114 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208 115 /** Clock ID for Quinary TDM EBIT */ 116 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209 117 /** Clock ID for Quinary TDM OSR */ 118 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A 119 120 /* Clock ID for MCLK1 */ 121 #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300 122 /* Clock ID for MCLK2 */ 123 #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301 124 /* Clock ID for MCLK3 */ 125 #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302 126 /* Clock ID for MCLK4 */ 127 #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304 128 /* Clock ID for Internal Digital Codec Core */ 129 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303 130 /* Clock ID for INT MCLK0 */ 131 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305 132 /* Clock ID for INT MCLK1 */ 133 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306 134 135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309 136 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a 137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c 138 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d 139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e 140 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f 141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b 142 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310 143 144 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2 145 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3 146 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4 147 148 /* Clock attribute for invalid use (reserved for internal usage) */ 149 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0 150 /* Clock attribute for no couple case */ 151 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 152 /* Clock attribute for dividend couple case */ 153 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 154 /* Clock attribute for divisor couple case */ 155 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 156 /* Clock attribute for invert and no couple case */ 157 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4 158 159 #define Q6AFE_CMAP_INVALID 0xFFFF 160 161 struct q6afe_hdmi_cfg { 162 u16 datatype; 163 u16 channel_allocation; 164 u32 sample_rate; 165 u16 bit_width; 166 }; 167 168 struct q6afe_slim_cfg { 169 u32 sample_rate; 170 u16 bit_width; 171 u16 data_format; 172 u16 num_channels; 173 u8 ch_mapping[AFE_MAX_CHAN_COUNT]; 174 }; 175 176 struct q6afe_i2s_cfg { 177 u32 sample_rate; 178 u16 bit_width; 179 u16 data_format; 180 u16 num_channels; 181 u32 sd_line_mask; 182 int fmt; 183 }; 184 185 struct q6afe_tdm_cfg { 186 u16 num_channels; 187 u32 sample_rate; 188 u16 bit_width; 189 u16 data_format; 190 u16 sync_mode; 191 u16 sync_src; 192 u16 nslots_per_frame; 193 u16 slot_width; 194 u16 slot_mask; 195 u32 data_align_type; 196 u16 ch_mapping[AFE_MAX_CHAN_COUNT]; 197 }; 198 199 struct q6afe_cdc_dma_cfg { 200 u16 sample_rate; 201 u16 bit_width; 202 u16 data_format; 203 u16 num_channels; 204 u16 active_channels_mask; 205 }; 206 207 /** 208 * struct q6afe_usb_cfg 209 * @cfg_minor_version: Minor version used for tracking USB audio device 210 * configuration. 211 * Supported values: 212 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 213 * @sample_rate: Sampling rate of the port 214 * Supported values: 215 * AFE_PORT_SAMPLE_RATE_8K 216 * AFE_PORT_SAMPLE_RATE_11025 217 * AFE_PORT_SAMPLE_RATE_12K 218 * AFE_PORT_SAMPLE_RATE_16K 219 * AFE_PORT_SAMPLE_RATE_22050 220 * AFE_PORT_SAMPLE_RATE_24K 221 * AFE_PORT_SAMPLE_RATE_32K 222 * AFE_PORT_SAMPLE_RATE_44P1K 223 * AFE_PORT_SAMPLE_RATE_48K 224 * AFE_PORT_SAMPLE_RATE_96K 225 * AFE_PORT_SAMPLE_RATE_192K 226 * @bit_width: Bit width of the sample. 227 * Supported values: 16, 24 228 * @num_channels: Number of channels 229 * Supported values: 1, 2 230 **/ 231 struct q6afe_usb_cfg { 232 u32 cfg_minor_version; 233 u32 sample_rate; 234 u16 bit_width; 235 u16 num_channels; 236 }; 237 238 struct q6afe_port_config { 239 struct q6afe_hdmi_cfg hdmi; 240 struct q6afe_slim_cfg slim; 241 struct q6afe_i2s_cfg i2s_cfg; 242 struct q6afe_tdm_cfg tdm; 243 struct q6afe_cdc_dma_cfg dma_cfg; 244 struct q6afe_usb_cfg usb_audio; 245 }; 246 247 struct q6afe_port; 248 249 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id); 250 int q6afe_port_start(struct q6afe_port *port); 251 int q6afe_port_stop(struct q6afe_port *port); 252 void q6afe_port_put(struct q6afe_port *port); 253 int q6afe_get_port_id(int index); 254 void q6afe_usb_port_prepare(struct q6afe_port *port, 255 struct q6afe_usb_cfg *cfg); 256 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 257 struct q6afe_hdmi_cfg *cfg); 258 void q6afe_slim_port_prepare(struct q6afe_port *port, 259 struct q6afe_slim_cfg *cfg); 260 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg); 261 void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg); 262 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 263 struct q6afe_cdc_dma_cfg *cfg); 264 265 int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx); 266 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 267 int clk_src, int clk_root, 268 unsigned int freq, int dir); 269 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 270 int clk_root, unsigned int freq); 271 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 272 const char *client_name, uint32_t *client_handle); 273 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 274 uint32_t client_handle); 275 #endif /* __Q6AFE_H__ */ 276