1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AMD HSMP Platform Driver
4 * Copyright (c) 2024, AMD.
5 * All Rights Reserved.
6 *
7 * This file provides platform device implementations.
8 */
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <asm/amd/hsmp.h>
13
14 #include <linux/acpi.h>
15 #include <linux/build_bug.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/dev_printk.h>
19 #include <linux/kconfig.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/rwsem.h>
24 #include <linux/sysfs.h>
25
26 #include <asm/amd/node.h>
27
28 #include "hsmp.h"
29
30 #define DRIVER_NAME "amd_hsmp"
31
32 /*
33 * To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox
34 * register into the SMN_INDEX register, and reads/writes the SMN_DATA reg.
35 * Below are required SMN address for HSMP Mailbox register offsets in SMU address space
36 */
37 #define SMN_HSMP_BASE 0x3B00000
38 #define SMN_HSMP_MSG_ID 0x0010534
39 #define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934
40 #define SMN_HSMP_MSG_RESP 0x0010980
41 #define SMN_HSMP_MSG_DATA 0x00109E0
42
43 static struct hsmp_plat_device *hsmp_pdev;
44
amd_hsmp_pci_rdwr(struct hsmp_socket * sock,u32 offset,u32 * value,bool write)45 static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset,
46 u32 *value, bool write)
47 {
48 return amd_smn_hsmp_rdwr(sock->sock_ind, sock->mbinfo.base_addr + offset, value, write);
49 }
50
hsmp_metric_tbl_plat_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)51 static ssize_t hsmp_metric_tbl_plat_read(struct file *filp, struct kobject *kobj,
52 const struct bin_attribute *bin_attr, char *buf,
53 loff_t off, size_t count)
54 {
55 struct hsmp_socket *sock;
56 u16 sock_ind;
57
58 sock_ind = (uintptr_t)bin_attr->private;
59 if (sock_ind >= hsmp_pdev->num_sockets)
60 return -EINVAL;
61
62 sock = &hsmp_pdev->sock[sock_ind];
63
64 return hsmp_metric_tbl_read(sock, buf, count);
65 }
66
hsmp_is_sock_attr_visible(struct kobject * kobj,const struct bin_attribute * battr,int id)67 static umode_t hsmp_is_sock_attr_visible(struct kobject *kobj,
68 const struct bin_attribute *battr, int id)
69 {
70 u16 sock_ind;
71
72 sock_ind = (uintptr_t)battr->private;
73
74 if (id == 0 && sock_ind >= hsmp_pdev->num_sockets)
75 return SYSFS_GROUP_INVISIBLE;
76
77 if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6)
78 return battr->attr.mode;
79
80 return 0;
81 }
82
83 /*
84 * AMD supports maximum of 8 sockets in a system.
85 * Static array of 8 + 1(for NULL) elements is created below
86 * to create sysfs groups for sockets.
87 * is_bin_visible function is used to show / hide the necessary groups.
88 *
89 * Validate the maximum number against MAX_AMD_NUM_NODES. If this changes,
90 * then the attributes and groups below must be adjusted.
91 */
92 static_assert(MAX_AMD_NUM_NODES == 8);
93
94 #define HSMP_BIN_ATTR(index, _list) \
95 static const struct bin_attribute attr##index = { \
96 .attr = { .name = HSMP_METRICS_TABLE_NAME, .mode = 0444}, \
97 .private = (void *)index, \
98 .read = hsmp_metric_tbl_plat_read, \
99 .size = sizeof(struct hsmp_metric_table), \
100 }; \
101 static const struct bin_attribute _list[] = { \
102 &attr##index, \
103 NULL \
104 }
105
106 HSMP_BIN_ATTR(0, *sock0_attr_list);
107 HSMP_BIN_ATTR(1, *sock1_attr_list);
108 HSMP_BIN_ATTR(2, *sock2_attr_list);
109 HSMP_BIN_ATTR(3, *sock3_attr_list);
110 HSMP_BIN_ATTR(4, *sock4_attr_list);
111 HSMP_BIN_ATTR(5, *sock5_attr_list);
112 HSMP_BIN_ATTR(6, *sock6_attr_list);
113 HSMP_BIN_ATTR(7, *sock7_attr_list);
114
115 #define HSMP_BIN_ATTR_GRP(index, _list, _name) \
116 static const struct attribute_group sock##index##_attr_grp = { \
117 .bin_attrs = _list, \
118 .is_bin_visible = hsmp_is_sock_attr_visible, \
119 .name = #_name, \
120 }
121
122 HSMP_BIN_ATTR_GRP(0, sock0_attr_list, socket0);
123 HSMP_BIN_ATTR_GRP(1, sock1_attr_list, socket1);
124 HSMP_BIN_ATTR_GRP(2, sock2_attr_list, socket2);
125 HSMP_BIN_ATTR_GRP(3, sock3_attr_list, socket3);
126 HSMP_BIN_ATTR_GRP(4, sock4_attr_list, socket4);
127 HSMP_BIN_ATTR_GRP(5, sock5_attr_list, socket5);
128 HSMP_BIN_ATTR_GRP(6, sock6_attr_list, socket6);
129 HSMP_BIN_ATTR_GRP(7, sock7_attr_list, socket7);
130
131 static const struct attribute_group *hsmp_groups[] = {
132 &sock0_attr_grp,
133 &sock1_attr_grp,
134 &sock2_attr_grp,
135 &sock3_attr_grp,
136 &sock4_attr_grp,
137 &sock5_attr_grp,
138 &sock6_attr_grp,
139 &sock7_attr_grp,
140 NULL
141 };
142
is_f1a_m0h(void)143 static inline bool is_f1a_m0h(void)
144 {
145 if (boot_cpu_data.x86 == 0x1A && boot_cpu_data.x86_model <= 0x0F)
146 return true;
147
148 return false;
149 }
150
init_platform_device(struct device * dev)151 static int init_platform_device(struct device *dev)
152 {
153 struct hsmp_socket *sock;
154 int ret, i;
155
156 for (i = 0; i < hsmp_pdev->num_sockets; i++) {
157 sock = &hsmp_pdev->sock[i];
158 sock->sock_ind = i;
159 sock->dev = dev;
160 sock->mbinfo.base_addr = SMN_HSMP_BASE;
161 sock->amd_hsmp_rdwr = amd_hsmp_pci_rdwr;
162
163 /*
164 * This is a transitional change from non-ACPI to ACPI, only
165 * family 0x1A, model 0x00 platform is supported for both ACPI and non-ACPI.
166 */
167 if (is_f1a_m0h())
168 sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H;
169 else
170 sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID;
171
172 sock->mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP;
173 sock->mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA;
174 sema_init(&sock->hsmp_sem, 1);
175
176 /* Test the hsmp interface on each socket */
177 ret = hsmp_test(i, 0xDEADBEEF);
178 if (ret) {
179 dev_err(dev, "HSMP test message failed on Fam:%x model:%x\n",
180 boot_cpu_data.x86, boot_cpu_data.x86_model);
181 dev_err(dev, "Is HSMP disabled in BIOS ?\n");
182 return ret;
183 }
184
185 ret = hsmp_cache_proto_ver(i);
186 if (ret) {
187 dev_err(dev, "Failed to read HSMP protocol version\n");
188 return ret;
189 }
190
191 if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6) {
192 ret = hsmp_get_tbl_dram_base(i);
193 if (ret)
194 dev_info(dev, "Failed to init metric table\n");
195 }
196
197 /* Register with hwmon interface for reporting power */
198 ret = hsmp_create_sensor(dev, i);
199 if (ret)
200 dev_info(dev, "Failed to register HSMP sensors with hwmon\n");
201 }
202
203 return 0;
204 }
205
206 /*
207 * The socket array is devm-managed and freed by the driver core, but the
208 * metric-table DRAM regions are mapped with plain ioremap() during probe and
209 * the per-socket mutexes need an explicit mutex_destroy(), neither of which
210 * devres covers.
211 *
212 * Take the data-plane rwsem for write to drain any in-flight
213 * hsmp_send_message(), unmap the metric tables, destroy the mutexes and drop
214 * the global socket pointer, all before devres frees the array. Registered as
215 * a devres action so it runs on both remove and probe failure.
216 */
hsmp_pltdrv_release(void * data)217 static void hsmp_pltdrv_release(void *data)
218 {
219 guard(rwsem_write)(&hsmp_sock_rwsem);
220 hsmp_unmap_metric_tbls(hsmp_pdev);
221 hsmp_destroy_metric_read_locks(hsmp_pdev);
222 hsmp_pdev->sock = NULL;
223 }
224
hsmp_pltdrv_probe(struct platform_device * pdev)225 static int hsmp_pltdrv_probe(struct platform_device *pdev)
226 {
227 int ret;
228
229 hsmp_pdev->sock = devm_kcalloc(&pdev->dev, hsmp_pdev->num_sockets,
230 sizeof(*hsmp_pdev->sock),
231 GFP_KERNEL);
232 if (!hsmp_pdev->sock)
233 return -ENOMEM;
234
235 hsmp_init_metric_read_locks(hsmp_pdev);
236
237 ret = devm_add_action_or_reset(&pdev->dev, hsmp_pltdrv_release, NULL);
238 if (ret)
239 return ret;
240
241 /*
242 * init_platform_device() runs the mailbox handshake via the probe-only
243 * senders, which issue messages through hsmp_send_message_locked() and
244 * so require hsmp_sock_rwsem held. Hold it for write, matching probe's
245 * role as a socket bring-up path. The lock is not held across
246 * devm_add_action_or_reset() above so the release action, which also
247 * takes it for write, does not deadlock if that registration fails.
248 */
249 scoped_guard(rwsem_write, &hsmp_sock_rwsem)
250 ret = init_platform_device(&pdev->dev);
251 if (ret) {
252 dev_err(&pdev->dev, "Failed to init HSMP mailbox\n");
253 return ret;
254 }
255
256 ret = hsmp_misc_register(&pdev->dev);
257 if (ret) {
258 dev_err(&pdev->dev, "Failed to register misc device\n");
259 return ret;
260 }
261
262 dev_dbg(&pdev->dev, "AMD HSMP is probed successfully\n");
263 return 0;
264 }
265
hsmp_pltdrv_remove(struct platform_device * pdev)266 static void hsmp_pltdrv_remove(struct platform_device *pdev)
267 {
268 hsmp_misc_deregister();
269 }
270
271 static struct platform_driver amd_hsmp_driver = {
272 .probe = hsmp_pltdrv_probe,
273 .remove = hsmp_pltdrv_remove,
274 .driver = {
275 .name = DRIVER_NAME,
276 .dev_groups = hsmp_groups,
277 },
278 };
279
280 static struct platform_device *amd_hsmp_platdev;
281
hsmp_plat_dev_register(void)282 static int hsmp_plat_dev_register(void)
283 {
284 int ret;
285
286 amd_hsmp_platdev = platform_device_alloc(DRIVER_NAME, PLATFORM_DEVID_NONE);
287 if (!amd_hsmp_platdev)
288 return -ENOMEM;
289
290 ret = platform_device_add(amd_hsmp_platdev);
291 if (ret)
292 platform_device_put(amd_hsmp_platdev);
293
294 return ret;
295 }
296
297 /*
298 * This check is only needed for backward compatibility of previous platforms.
299 * All new platforms are expected to support ACPI based probing.
300 */
legacy_hsmp_support(void)301 static bool legacy_hsmp_support(void)
302 {
303 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
304 return false;
305
306 switch (boot_cpu_data.x86) {
307 case 0x19:
308 switch (boot_cpu_data.x86_model) {
309 case 0x00 ... 0x1F:
310 case 0x30 ... 0x3F:
311 case 0x90 ... 0x9F:
312 case 0xA0 ... 0xAF:
313 return true;
314 default:
315 return false;
316 }
317 case 0x1A:
318 switch (boot_cpu_data.x86_model) {
319 case 0x00 ... 0x0F:
320 return true;
321 default:
322 return false;
323 }
324 default:
325 return false;
326 }
327
328 return false;
329 }
330
hsmp_plt_init(void)331 static int __init hsmp_plt_init(void)
332 {
333 int ret = -ENODEV;
334
335 if (acpi_dev_present(ACPI_HSMP_DEVICE_HID, NULL, -1)) {
336 if (IS_ENABLED(CONFIG_AMD_HSMP_ACPI))
337 pr_debug("HSMP is supported through ACPI on this platform, please use hsmp_acpi.ko\n");
338 else
339 pr_info("HSMP is supported through ACPI on this platform, please enable AMD_HSMP_ACPI config\n");
340 return -ENODEV;
341 }
342
343 if (!legacy_hsmp_support()) {
344 pr_info("HSMP interface is either disabled or not supported on family:%x model:%x\n",
345 boot_cpu_data.x86, boot_cpu_data.x86_model);
346 return ret;
347 }
348
349 hsmp_pdev = get_hsmp_pdev();
350 if (!hsmp_pdev)
351 return -ENOMEM;
352
353 /*
354 * amd_num_nodes() returns number of SMN/DF interfaces present in the system
355 * if we have N SMN/DF interfaces that ideally means N sockets
356 */
357 hsmp_pdev->num_sockets = amd_num_nodes();
358 if (hsmp_pdev->num_sockets == 0 || hsmp_pdev->num_sockets > MAX_AMD_NUM_NODES) {
359 pr_err("Wrong number of sockets\n");
360 return ret;
361 }
362
363 ret = platform_driver_register(&amd_hsmp_driver);
364 if (ret)
365 return ret;
366
367 ret = hsmp_plat_dev_register();
368 if (ret)
369 platform_driver_unregister(&amd_hsmp_driver);
370
371 return ret;
372 }
373
hsmp_plt_exit(void)374 static void __exit hsmp_plt_exit(void)
375 {
376 platform_device_unregister(amd_hsmp_platdev);
377 platform_driver_unregister(&amd_hsmp_driver);
378 }
379
380 device_initcall(hsmp_plt_init);
381 module_exit(hsmp_plt_exit);
382
383 MODULE_IMPORT_NS("AMD_HSMP");
384 MODULE_DESCRIPTION("AMD HSMP Platform Interface Driver");
385 MODULE_VERSION(DRIVER_VERSION);
386 MODULE_LICENSE("GPL");
387