1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18
19 #define PA_BASE 0
20 #define PB_BASE 32
21 #define PC_BASE 64
22 #define PD_BASE 96
23 #define PE_BASE 128
24 #define PF_BASE 160
25 #define PG_BASE 192
26 #define PH_BASE 224
27 #define PI_BASE 256
28 #define PJ_BASE 288
29 #define PK_BASE 320
30 #define PL_BASE 352
31 #define PM_BASE 384
32 #define PN_BASE 416
33
34 /* maximum number of banks per controller (PA -> PK) */
35 #define SUNXI_PINCTRL_MAX_BANKS 11
36
37 #define SUNXI_PINCTRL_PIN(bank, pin) \
38 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
39
40 #define SUNXI_PIN_NAME_MAX_LEN 5
41
42 #define BANK_MEM_SIZE 0x24
43 #define MUX_REGS_OFFSET 0x0
44 #define MUX_FIELD_WIDTH 4
45 #define DATA_REGS_OFFSET 0x10
46 #define DATA_FIELD_WIDTH 1
47 #define DLEVEL_REGS_OFFSET 0x14
48 #define DLEVEL_FIELD_WIDTH 2
49 #define PULL_REGS_OFFSET 0x1c
50 #define PULL_FIELD_WIDTH 2
51
52 #define D1_BANK_MEM_SIZE 0x30
53 #define D1_DLEVEL_FIELD_WIDTH 4
54 #define D1_PULL_REGS_OFFSET 0x24
55
56 #define PINS_PER_BANK 32
57
58 #define IRQ_PER_BANK 32
59
60 #define IRQ_CFG_REG 0x200
61 #define IRQ_CFG_IRQ_PER_REG 8
62 #define IRQ_CFG_IRQ_BITS 4
63 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
64 #define IRQ_CTRL_REG 0x210
65 #define IRQ_CTRL_IRQ_PER_REG 32
66 #define IRQ_CTRL_IRQ_BITS 1
67 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
68 #define IRQ_STATUS_REG 0x214
69 #define IRQ_STATUS_IRQ_PER_REG 32
70 #define IRQ_STATUS_IRQ_BITS 1
71 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
72
73 #define IRQ_DEBOUNCE_REG 0x218
74
75 #define IRQ_MEM_SIZE 0x20
76
77 #define IRQ_EDGE_RISING 0x00
78 #define IRQ_EDGE_FALLING 0x01
79 #define IRQ_LEVEL_HIGH 0x02
80 #define IRQ_LEVEL_LOW 0x03
81 #define IRQ_EDGE_BOTH 0x04
82
83 #define GRP_CFG_REG 0x300
84
85 #define IO_BIAS_MASK GENMASK(3, 0)
86
87 #define SUN4I_FUNC_INPUT 0
88 #define SUN4I_FUNC_OUTPUT 1
89 #define SUN4I_FUNC_IRQ 6
90 #define SUN4I_FUNC_DISABLED_OLD 7
91 #define SUN4I_FUNC_DISABLED_NEW 15
92
93 #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0)
94 #define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8)
95 #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9)
96 #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10)
97
98 #define PIO_POW_MOD_SEL_REG 0x340
99 #define PIO_11B_POW_MOD_SEL_REG 0x380
100 #define PIO_POW_MOD_CTL_OFS 0x004
101
102 #define PIO_BANK_K_OFFSET 0x500
103
104 enum sunxi_desc_bias_voltage {
105 BIAS_VOLTAGE_NONE,
106 /*
107 * Bias voltage configuration is done through
108 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
109 */
110 BIAS_VOLTAGE_GRP_CONFIG,
111 /*
112 * Bias voltage is set through PIO_POW_MOD_SEL_REG
113 * register, as seen on H6 SoC, for example.
114 */
115 BIAS_VOLTAGE_PIO_POW_MODE_SEL,
116 /*
117 * Bias voltage is set through PIO_POW_MOD_SEL_REG
118 * and PIO_POW_MOD_CTL_REG register, as seen on
119 * A100 and D1 SoC, for example.
120 * Some SoCs invert the encoding for 1.8V vs. 3.3V.
121 */
122 BIAS_VOLTAGE_PIO_POW_MODE_CTL,
123 BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV,
124 };
125
126 struct sunxi_desc_function {
127 unsigned long variant;
128 const char *name;
129 u8 muxval;
130 u8 irqbank;
131 u8 irqnum;
132 };
133
134 struct sunxi_desc_pin {
135 struct pinctrl_pin_desc pin;
136 unsigned long variant;
137 struct sunxi_desc_function *functions;
138 };
139
140 struct sunxi_pinctrl_desc {
141 const struct sunxi_desc_pin *pins;
142 int npins;
143 unsigned pin_base;
144 unsigned irq_banks;
145 const unsigned int *irq_bank_map;
146 bool irq_read_needs_mux;
147 bool disable_strict_mode;
148 enum sunxi_desc_bias_voltage io_bias_cfg_variant;
149 };
150
151 struct sunxi_pinctrl_function {
152 const char *name;
153 const char **groups;
154 unsigned ngroups;
155 };
156
157 struct sunxi_pinctrl_group {
158 const char *name;
159 unsigned pin;
160 };
161
162 struct sunxi_pinctrl_regulator {
163 struct regulator *regulator;
164 refcount_t refcount;
165 };
166
167 struct sunxi_pinctrl {
168 void __iomem *membase;
169 struct gpio_chip *chip;
170 const struct sunxi_pinctrl_desc *desc;
171 struct device *dev;
172 struct sunxi_pinctrl_regulator regulators[11];
173 struct irq_domain *domain;
174 struct sunxi_pinctrl_function *functions;
175 unsigned nfunctions;
176 struct sunxi_pinctrl_group *groups;
177 unsigned ngroups;
178 int *irq;
179 unsigned *irq_array;
180 raw_spinlock_t lock;
181 /*
182 * Output latch shadow, one word per bank. Seeded lockless at
183 * probe before the pinctrl device registers, protected by @lock
184 * afterwards.
185 */
186 u32 *dat_shadow;
187 struct pinctrl_dev *pctl_dev;
188 unsigned long flags;
189 u32 bank_mem_size;
190 u32 pull_regs_offset;
191 u32 dlevel_field_width;
192 u32 pow_mod_sel_offset;
193 };
194
195 #define SUNXI_PIN(_pin, ...) \
196 { \
197 .pin = _pin, \
198 .functions = (struct sunxi_desc_function[]){ \
199 __VA_ARGS__, { } }, \
200 }
201
202 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
203 { \
204 .pin = _pin, \
205 .variant = _variant, \
206 .functions = (struct sunxi_desc_function[]){ \
207 __VA_ARGS__, { } }, \
208 }
209
210 #define SUNXI_FUNCTION(_val, _name) \
211 { \
212 .name = _name, \
213 .muxval = _val, \
214 }
215
216 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
217 { \
218 .name = _name, \
219 .muxval = _val, \
220 .variant = _variant, \
221 }
222
223 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
224 { \
225 .name = "irq", \
226 .muxval = _val, \
227 .irqnum = _irq, \
228 }
229
230 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
231 { \
232 .name = "irq", \
233 .muxval = _val, \
234 .irqbank = _bank, \
235 .irqnum = _irq, \
236 }
237
sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc * desc,u8 bank)238 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
239 {
240 if (!desc->irq_bank_map)
241 return bank;
242 else
243 return desc->irq_bank_map[bank];
244 }
245
sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)246 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
247 u16 irq)
248 {
249 u8 bank = irq / IRQ_PER_BANK;
250 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
251
252 return IRQ_CFG_REG +
253 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
254 }
255
sunxi_irq_cfg_offset(u16 irq)256 static inline u32 sunxi_irq_cfg_offset(u16 irq)
257 {
258 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
259 return irq_num * IRQ_CFG_IRQ_BITS;
260 }
261
sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)262 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
263 {
264 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
265 }
266
sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)267 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
268 u16 irq)
269 {
270 u8 bank = irq / IRQ_PER_BANK;
271
272 return sunxi_irq_ctrl_reg_from_bank(desc, bank);
273 }
274
sunxi_irq_ctrl_offset(u16 irq)275 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
276 {
277 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
278 return irq_num * IRQ_CTRL_IRQ_BITS;
279 }
280
sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)281 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
282 {
283 return IRQ_DEBOUNCE_REG +
284 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
285 }
286
sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)287 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
288 {
289 return IRQ_STATUS_REG +
290 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
291 }
292
sunxi_irq_status_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)293 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
294 u16 irq)
295 {
296 u8 bank = irq / IRQ_PER_BANK;
297
298 return sunxi_irq_status_reg_from_bank(desc, bank);
299 }
300
sunxi_irq_status_offset(u16 irq)301 static inline u32 sunxi_irq_status_offset(u16 irq)
302 {
303 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
304 return irq_num * IRQ_STATUS_IRQ_BITS;
305 }
306
sunxi_grp_config_reg(u16 pin)307 static inline u32 sunxi_grp_config_reg(u16 pin)
308 {
309 u8 bank = pin / PINS_PER_BANK;
310
311 return GRP_CFG_REG + bank * 0x4;
312 }
313
314 int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
315 const struct sunxi_pinctrl_desc *desc,
316 unsigned long flags);
317
318 #define sunxi_pinctrl_init(_dev, _desc) \
319 sunxi_pinctrl_init_with_flags(_dev, _desc, 0)
320
321 int sunxi_pinctrl_dt_table_init(struct platform_device *pdev,
322 const u8 *pins_per_bank,
323 const u8 *irq_bank_muxes,
324 struct sunxi_pinctrl_desc *desc,
325 unsigned long flags);
326
327 #endif /* __PINCTRL_SUNXI_H */
328