1perf-c2c(1) 2=========== 3 4NAME 5---- 6perf-c2c - Shared Data C2C/HITM Analyzer. 7 8SYNOPSIS 9-------- 10[verse] 11'perf c2c record' [<options>] <command> 12'perf c2c record' [<options>] \-- [<record command options>] <command> 13'perf c2c report' [<options>] 14 15DESCRIPTION 16----------- 17C2C stands for Cache To Cache. 18 19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows 20you to track down the cacheline contentions. 21 22On Intel, the tool is based on load latency and precise store facility events 23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling 24with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware 25limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to 26sample load and store operations, therefore hardware and kernel support is 27required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the 28statistical nature of Arm SPE sampling, not every memory operation will be 29sampled. 30 31These events provide: 32 - memory address of the access 33 - type of the access (load and store details) 34 - latency (in cycles) of the load access 35 36The c2c tool provide means to record this data and report back access details 37for cachelines with highest contention - highest number of HITM accesses. 38 39The basic workflow with this tool follows the standard record/report phase. 40User uses the record command to record events data and report command to 41display it. 42 43 44RECORD OPTIONS 45-------------- 46-e:: 47--event=:: 48 Select the PMU event. Use 'perf c2c record -e list' 49 to list available events. 50 51-v:: 52--verbose:: 53 Be more verbose (show counter open errors, etc). 54 55-l:: 56--ldlat:: 57 Configure mem-loads latency. Supported on Intel, Arm64 and some AMD 58 processors. Ignored on other archs. 59 60 On supported AMD processors: 61 - /sys/bus/event_source/devices/ibs_op/caps/ldlat file contains '1'. 62 - Supported latency values are 128 to 2048 (both inclusive). 63 - Latency value which is a multiple of 128 incurs a little less profiling 64 overhead compared to other values. 65 - Load latency filtering is disabled by default. 66 67-k:: 68--all-kernel:: 69 Configure all used events to run in kernel space. 70 71-u:: 72--all-user:: 73 Configure all used events to run in user space. 74 75REPORT OPTIONS 76-------------- 77-k:: 78--vmlinux=<file>:: 79 vmlinux pathname 80 81-v:: 82--verbose:: 83 Be more verbose (show counter open errors, etc). 84 85-i:: 86--input:: 87 Specify the input file to process. 88 89-N:: 90--node-info:: 91 Show extra node info in report (see NODE INFO section) 92 93-c:: 94--coalesce:: 95 Specify sorting fields for single cacheline display. 96 Following fields are available: tid,pid,iaddr,dso 97 (see COALESCE) 98 99-g:: 100--call-graph:: 101 Setup callchains parameters. 102 Please refer to perf-report man page for details. 103 104--stdio:: 105 Force the stdio output (see STDIO OUTPUT) 106 107--stats:: 108 Display only statistic tables and force stdio mode. 109 110--full-symbols:: 111 Display full length of symbols. 112 113--no-source:: 114 Do not display Source:Line column. 115 116--show-all:: 117 Show all captured HITM lines, with no regard to HITM % 0.0005 limit. 118 119-f:: 120--force:: 121 Don't do ownership validation. 122 123-d:: 124--display:: 125 Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display 126 and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode 127 as default. 128 129--stitch-lbr:: 130 Show callgraph with stitched LBRs, which may have more complete 131 callgraph. The perf.data file must have been obtained using 132 perf c2c record --call-graph lbr. 133 Disabled by default. In common cases with call stack overflows, 134 it can recreate better call stacks than the default lbr call stack 135 output. But this approach is not foolproof. There can be cases 136 where it creates incorrect call stacks from incorrect matches. 137 The known limitations include exception handing such as 138 setjmp/longjmp will have calls/returns not match. 139 140--double-cl:: 141 Group the detection of shared cacheline events into double cacheline 142 granularity. Some architectures have an Adjacent Cacheline Prefetch 143 feature, which causes cacheline sharing to behave like the cacheline 144 size is doubled. 145 146-M:: 147--disassembler-style=:: 148 Set disassembler style for objdump. 149 150--objdump=<path>:: 151 Path to objdump binary. 152 153C2C RECORD 154---------- 155The perf c2c record command setup options related to HITM cacheline analysis 156and calls standard perf record command. 157 158Following perf record options are configured by default: 159(check perf record man page for details) 160 161 -W,-d,--phys-data,--sample-cpu 162 163The following table lists the events monitored on different architectures. 164Unless specified otherwise with the -e option, the tool will select the 165default events. 166 167 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 168 | Arch | Configuration | Options | Events | 169 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 170 | Intel | Default | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | 171 | | | -e ldlat-stores | cpu/mem-stores/P | 172 | |---------------+-----------------+--------------------------------------------------------------------------------+ 173 | | Load only | -e ldlat-loads | cpu/mem-loads,ldlat=30/P | 174 | |---------------+-----------------+--------------------------------------------------------------------------------+ 175 | | Store only | -e ldlat-stores | cpu/mem-stores/P | 176 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 177 | Intel | Default | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | 178 | with | | -e ldlat-stores | cpu/mem-stores/P | 179 | AUX |--------------+------------------+--------------------------------------------------------------------------------+ 180 | | Load only | -e ldlat-loads | {cpu/mem-loads-aux/,cpu/mem-loads,ldlat=30/}:P | 181 | |---------------+-----------------+--------------------------------------------------------------------------------+ 182 | | Store only | -e ldlat-stores | cpu/mem-stores/P | 183 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 184 | AMD | Default | -e mem-ldst | ibs_op// (without latency support) | 185 | | | | ibs_op/ldlat=30/ (with latency support) | 186 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 187 | PowerPC| Default | -e ldlat-loads | cpu/mem-loads/ | 188 | | | -e ldlat-stores | cpu/mem-stores/ | 189 | |---------------+-----------------+--------------------------------------------------------------------------------+ 190 | | Load only | -e ldlat-loads | cpu/mem-loads/ | 191 | |---------------+-----------------+--------------------------------------------------------------------------------+ 192 | | Store only | -e ldlat-stores | cpu/mem-stores/ | 193 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 194 | Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=30/ | 195 | SPE |---------------+-----------------+--------------------------------------------------------------------------------+ 196 | | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/ | 197 | |---------------+-----------------+--------------------------------------------------------------------------------+ 198 | | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ | 199 +--------+---------------+-----------------+--------------------------------------------------------------------------------+ 200 201User can pass any 'perf record' option behind '--' mark, like (to enable 202callchains and system wide monitoring): 203 204 $ perf c2c record -- -g -a 205 206Please check RECORD OPTIONS section for specific c2c record options. 207 208C2C REPORT 209---------- 210The perf c2c report command displays shared data analysis. It comes in two 211display modes: stdio and tui (default). 212 213The report command workflow is following: 214 - sort all the data based on the cacheline address 215 - store access details for each cacheline 216 - sort all cachelines based on user settings 217 - display data 218 219In general perf report output consist of 2 basic views: 220 1) most expensive cachelines list 221 2) offsets details for each cacheline 222 223For each cacheline in the 1) list we display following data: 224(Both stdio and TUI modes follow the same fields output) 225 226 Index 227 - zero based index to identify the cacheline 228 229 Cacheline 230 - cacheline address (hex number) 231 232 Rmt/Lcl Hitm (Display with HITM types) 233 - cacheline percentage of all Remote/Local HITM accesses 234 235 Peer Snoop (Display with peer type) 236 - cacheline percentage of all peer accesses 237 238 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types) 239 - count of Total/Local/Remote load HITMs 240 241 Load Peer - Total, Local, Remote (For display with peer type) 242 - count of Total/Local/Remote load from peer cache or DRAM 243 244 Total records 245 - sum of all cachelines accesses 246 247 Total loads 248 - sum of all load accesses 249 250 Total stores 251 - sum of all store accesses 252 253 Store Reference - L1Hit, L1Miss, N/A 254 L1Hit - store accesses that hit L1 255 L1Miss - store accesses that missed L1 256 N/A - store accesses with memory level is not available 257 258 Core Load Hit - FB, L1, L2 259 - count of load hits in FB (Fill Buffer), L1 and L2 cache 260 261 LLC Load Hit - LlcHit, LclHitm 262 - count of LLC load accesses, includes LLC hits and LLC HITMs 263 264 RMT Load Hit - RmtHit, RmtHitm 265 - count of remote load accesses, includes remote hits and remote HITMs; 266 on Arm neoverse cores, RmtHit is used to account remote accesses, 267 includes remote DRAM or any upward cache level in remote node 268 269 Load Dram - Lcl, Rmt 270 - count of local and remote DRAM accesses 271 272For each offset in the 2) list we display following data: 273 274 HITM - Rmt, Lcl (Display with HITM types) 275 - % of Remote/Local HITM accesses for given offset within cacheline 276 277 Peer Snoop - Rmt, Lcl (Display with peer type) 278 - % of Remote/Local peer accesses for given offset within cacheline 279 280 Store Refs - L1 Hit, L1 Miss, N/A 281 - % of store accesses that hit L1, missed L1 and N/A (no available) memory 282 level for given offset within cacheline 283 284 Data address - Offset 285 - offset address 286 287 Pid 288 - pid of the process responsible for the accesses 289 290 Tid 291 - tid of the process responsible for the accesses 292 293 Code address 294 - code address responsible for the accesses 295 296 cycles - rmt hitm, lcl hitm, load (Display with HITM types) 297 - sum of cycles for given accesses - Remote/Local HITM and generic load 298 299 cycles - rmt peer, lcl peer, load (Display with peer type) 300 - sum of cycles for given accesses - Remote/Local peer load and generic load 301 302 cpu cnt 303 - number of cpus that participated on the access 304 305 Symbol 306 - code symbol related to the 'Code address' value 307 308 Shared Object 309 - shared object name related to the 'Code address' value 310 311 Source:Line 312 - source information related to the 'Code address' value 313 314 Node 315 - nodes participating on the access (see NODE INFO section) 316 317NODE INFO 318--------- 319The 'Node' field displays nodes that accesses given cacheline 320offset. Its output comes in 3 flavors: 321 - node IDs separated by ',' 322 - node IDs with stats for each ID, in following format: 323 Node{cpus %hitms %stores} (Display with HITM types) 324 Node{cpus %peers %stores} (Display with peer type) 325 - node IDs with list of affected CPUs in following format: 326 Node{cpu list} 327 328User can switch between above flavors with -N option or 329use 'n' key to interactively switch in TUI mode. 330 331COALESCE 332-------- 333User can specify how to sort offsets for cacheline. 334 335Following fields are available and governs the final 336output fields set for cacheline offsets output: 337 338 tid - coalesced by process TIDs 339 pid - coalesced by process PIDs 340 iaddr - coalesced by code address, following fields are displayed: 341 Code address, Code symbol, Shared Object, Source line 342 dso - coalesced by shared object 343 344By default the coalescing is setup with 'pid,iaddr'. 345 346STDIO OUTPUT 347------------ 348The stdio output displays data on standard output. 349 350Following tables are displayed: 351 Trace Event Information 352 - overall statistics of memory accesses 353 354 Global Shared Cache Line Event Information 355 - overall statistics on shared cachelines 356 357 Shared Data Cache Line Table 358 - list of most expensive cachelines 359 360 Shared Cache Line Distribution Pareto 361 - list of all accessed offsets for each cacheline 362 363TUI OUTPUT 364---------- 365The TUI output provides interactive interface to navigate 366through cachelines list and to display offset details. 367 368Pressing the 'TAB' key in the cacheline view switches to the function 369view. The function view shows a three-level hierarchy of the symbolized 370entries retained in the cacheline view, organized around functions rather 371than cachelines. Levels 1 and 2 normally show function names, while level 3 372shows cacheline addresses. Lower levels are indented beneath their parents. 373Verbose mode also includes code addresses in function rows, and code addresses 374remain available in the per-cacheline detail view ('d'). 375 376The function view requires `iaddr` in the cacheline coalescing fields. If 377`--coalesce` omits it, TAB reports that the view is unavailable rather than 378attributing already-coalesced samples to an arbitrary function. 379 380 Level 1: the read-side function, sorted by Cycles % (estimated load 381 cycles: HITM, peer-snoop and other-load cycles) 382 Level 2: the functions sampled writing the shared lines read by the 383 level-1 function, sorted by store count. This can be the same 384 function when it has both read and write samples 385 Level 3: the specific cachelines shared by the reader/writer pair 386 387The Cycles % value is the function's share of event-provided load 388latency/weight estimates from cacheline-detail entries retained in the 389current view. It can include non-HITM and non-peer loads coalesced into 390entries that pass the C2C filter, so it is not a pure contention-cycle 391percentage. The share is relative to the functions and entries retained 392for the current report and is not comparable across recordings or different 393`--coalesce` settings. 394 395The store count on a level-1 row is the number of sampled stores by writers 396shown in the function view into the cachelines that function reads, including 397stores from the same function. It decomposes into the level-2 writer rows; 398each level-2 count in turn decomposes into that writer's stores on its level-3 399cachelines. A level-3 count is therefore not the cacheline's total store 400count. The level-1 value is not the number of stores made by the reader and 401is not additive across level-1 rows: two functions reading the same line each 402carry the stores into that line. 403 404Each function aggregates all of its code addresses into a single entry, 405and a level-2 writer aggregates all of its shared cachelines, so a 406reader/writer pair is a single row with its total shown -- there is no 407need to sum a writer's traffic across cachelines by hand. 408 409In the function view the 'd' key opens the detail view of the selected 410level-3 cacheline, 'e'/'+' expands or collapses the current entry, and 'TAB', 411'ESC', 'q' or Ctrl-C returns to the cacheline view. 412 413For example, with the first two read-side functions collapsed and 414dequeue_pushable_task expanded to show the functions writing the lines it 415reads -- two of which are further expanded to their individual cachelines: 416 417 Shared Data Functions Table (19 entries, sorted on Cycles %) 418 Cycles Store 419 % count Function / Contending function / Cacheline 420 ---------------------------------------------------------------------- 421 + 35.67% 876 + [k] cpupri_set 422 + 24.31% 424 + [k] pull_rt_task 423 - 16.53% 555 - [k] dequeue_pushable_task 424 145 - [k] pull_rt_task 425 145 0xff2d0082809da080 426 139 - [k] enqueue_pushable_task 427 70 0xff2d00a2071f9640 428 69 0xff2d0082809da000 429 430Here dequeue_pushable_task pays 16.53% of the estimated read-side load-cycle 431cost. Its store count decomposes into its level-2 writers, and each writer's 432count decomposes into its level-3 cachelines: pull_rt_task's 145 stores fall 433on a single line, while enqueue_pushable_task's 139 stores split across two 434lines (70 and 69). A writer can be the same function as the reader when it 435has both read and write samples; after cacheline coalescing and 436function-level grouping, the view cannot distinguish same-thread accesses 437from different threads running the same function. 438 439For details please refer to the help window by pressing '?' key. 440 441CREDITS 442------- 443Although Don Zickus, Dick Fowles and Joe Mario worked together 444to get this implemented, we got lots of early help from Arnaldo 445Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen. 446 447C2C BLOG 448-------- 449Check Joe's blog on c2c tool for detailed use case explanation: 450 https://joemario.github.io/blog/2016/09/01/c2c-blog/ 451 452SEE ALSO 453-------- 454linkperf:perf-record[1], linkperf:perf-mem[1], linkperf:perf-arm-spe[1] 455