1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_CL0080_H__ 3 #define __NVIF_CL0080_H__ 4 5 #define NV_DEVICE_V0_INFO 0x00 6 #define NV_DEVICE_V0_TIME 0x01 7 #define NV_DEVICE_V0_GCX_READY 0x02 8 9 struct nv_device_info_v0 { 10 __u8 version; 11 #define NV_DEVICE_INFO_V0_IGP 0x00 12 #define NV_DEVICE_INFO_V0_PCI 0x01 13 #define NV_DEVICE_INFO_V0_AGP 0x02 14 #define NV_DEVICE_INFO_V0_PCIE 0x03 15 #define NV_DEVICE_INFO_V0_SOC 0x04 16 __u8 platform; 17 __u16 chipset; /* from NV_PMC_BOOT_0 */ 18 __u8 revision; /* from NV_PMC_BOOT_0 */ 19 #define NV_DEVICE_INFO_V0_TNT 0x01 20 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 21 #define NV_DEVICE_INFO_V0_KELVIN 0x03 22 #define NV_DEVICE_INFO_V0_RANKINE 0x04 23 #define NV_DEVICE_INFO_V0_CURIE 0x05 24 #define NV_DEVICE_INFO_V0_TESLA 0x06 25 #define NV_DEVICE_INFO_V0_FERMI 0x07 26 #define NV_DEVICE_INFO_V0_KEPLER 0x08 27 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 28 #define NV_DEVICE_INFO_V0_PASCAL 0x0a 29 #define NV_DEVICE_INFO_V0_VOLTA 0x0b 30 #define NV_DEVICE_INFO_V0_TURING 0x0c 31 #define NV_DEVICE_INFO_V0_AMPERE 0x0d 32 #define NV_DEVICE_INFO_V0_ADA 0x0e 33 #define NV_DEVICE_INFO_V0_HOPPER 0x0f 34 #define NV_DEVICE_INFO_V0_BLACKWELL 0x10 35 __u8 family; 36 __u8 pad06[2]; 37 __u64 ram_size; 38 __u64 ram_user; 39 char chip[16]; 40 char name[64]; 41 }; 42 43 struct nv_device_info_v1 { 44 __u8 version; 45 __u8 count; 46 __u8 pad02[6]; 47 struct nv_device_info_v1_data { 48 __u64 mthd; /* NV_DEVICE_INFO_* (see below). */ 49 __u64 data; 50 } data[]; 51 }; 52 53 struct nv_device_time_v0 { 54 __u8 version; 55 __u8 pad01[7]; 56 __u64 time; 57 }; 58 59 #define NV_DEVICE_GC6_READY BIT(0) 60 #define NV_DEVICE_GCOFF_READY BIT(1) 61 62 struct nv_device_gcx_ready_v0 { 63 __u8 version; 64 __u8 pad01[6]; 65 __u8 ready; 66 }; 67 68 #define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) 69 #define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) 70 #define NV_DEVICE_HOST(n) ((n) | (0x00000001ULL << 32)) 71 72 /* This will be returned in the mthd field for unsupported queries. */ 73 #define NV_DEVICE_INFO_INVALID ~0ULL 74 75 /* Returns the number of available runlists. */ 76 #define NV_DEVICE_HOST_RUNLISTS NV_DEVICE_HOST(0x00000000) 77 /* Returns the number of available channels (0 if per-runlist). */ 78 #define NV_DEVICE_HOST_CHANNELS NV_DEVICE_HOST(0x00000001) 79 80 /* Returns a mask of available engine types on runlist(data). */ 81 #define NV_DEVICE_HOST_RUNLIST_ENGINES NV_DEVICE_HOST(0x00000100) 82 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SW 0x00000001 83 #define NV_DEVICE_HOST_RUNLIST_ENGINES_GR 0x00000002 84 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG 0x00000004 85 #define NV_DEVICE_HOST_RUNLIST_ENGINES_ME 0x00000008 86 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER 0x00000010 87 #define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP 0x00000020 88 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VP 0x00000040 89 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CE 0x00000080 90 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC 0x00000100 91 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD 0x00000200 92 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC 0x00000400 93 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP 0x00000800 94 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC 0x00001000 95 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC 0x00002000 96 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000 97 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000 98 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000 99 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000 100 #define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000 101 /* Returns the number of available channels on runlist(data). */ 102 #define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101) 103 #endif 104