1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12#include "tegra210-peripherals-opp.dtsi" 13 14/ { 15 compatible = "nvidia,tegra210"; 16 interrupt-parent = <&lic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 pcie@1003000 { 21 compatible = "nvidia,tegra210-pcie"; 22 device_type = "pci"; 23 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 24 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 25 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 26 reg-names = "pads", "afi", "cs"; 27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 28 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 29 interrupt-names = "intr", "msi"; 30 31 #interrupt-cells = <1>; 32 interrupt-map-mask = <0 0 0 0>; 33 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 34 35 bus-range = <0x00 0xff>; 36 #address-cells = <3>; 37 #size-cells = <2>; 38 39 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 40 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 41 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 42 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 43 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 44 45 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 46 <&tegra_car TEGRA210_CLK_AFI>, 47 <&tegra_car TEGRA210_CLK_PLL_E>, 48 <&tegra_car TEGRA210_CLK_CML0>; 49 clock-names = "pex", "afi", "pll_e", "cml"; 50 resets = <&tegra_car 70>, 51 <&tegra_car 72>, 52 <&tegra_car 74>; 53 reset-names = "pex", "afi", "pcie_x"; 54 55 pinctrl-names = "default", "idle"; 56 pinctrl-0 = <&pex_dpd_disable>; 57 pinctrl-1 = <&pex_dpd_enable>; 58 59 status = "disabled"; 60 61 pci@1,0 { 62 device_type = "pci"; 63 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 64 reg = <0x000800 0 0 0 0>; 65 bus-range = <0x00 0xff>; 66 status = "disabled"; 67 68 #address-cells = <3>; 69 #size-cells = <2>; 70 ranges; 71 72 nvidia,num-lanes = <4>; 73 }; 74 75 pci@2,0 { 76 device_type = "pci"; 77 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 78 reg = <0x001000 0 0 0 0>; 79 bus-range = <0x00 0xff>; 80 status = "disabled"; 81 82 #address-cells = <3>; 83 #size-cells = <2>; 84 ranges; 85 86 nvidia,num-lanes = <1>; 87 }; 88 }; 89 90 host1x@50000000 { 91 compatible = "nvidia,tegra210-host1x"; 92 reg = <0x0 0x50000000 0x0 0x00034000>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 95 interrupt-names = "syncpt", "host1x"; 96 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 97 clock-names = "host1x"; 98 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 99 reset-names = "host1x", "mc"; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 105 106 iommus = <&mc TEGRA_SWGROUP_HC>; 107 108 dpaux1: dpaux@54040000 { 109 compatible = "nvidia,tegra210-dpaux"; 110 reg = <0x0 0x54040000 0x0 0x00040000>; 111 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 113 <&tegra_car TEGRA210_CLK_PLL_DP>; 114 clock-names = "dpaux", "parent"; 115 resets = <&tegra_car 207>; 116 reset-names = "dpaux"; 117 power-domains = <&pd_sor>; 118 status = "disabled"; 119 120 state_dpaux1_aux: pinmux-aux { 121 groups = "dpaux-io"; 122 function = "aux"; 123 }; 124 125 state_dpaux1_i2c: pinmux-i2c { 126 groups = "dpaux-io"; 127 function = "i2c"; 128 }; 129 130 state_dpaux1_off: pinmux-off { 131 groups = "dpaux-io"; 132 function = "off"; 133 }; 134 135 i2c-bus { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 }; 140 141 vi@54080000 { 142 compatible = "nvidia,tegra210-vi"; 143 reg = <0x0 0x54080000 0x0 0x700>; 144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 145 status = "disabled"; 146 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 147 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 148 149 clocks = <&tegra_car TEGRA210_CLK_VI>; 150 power-domains = <&pd_venc>; 151 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 ranges = <0x0 0x0 0x54080000 0x2000>; 156 157 csi@838 { 158 compatible = "nvidia,tegra210-csi"; 159 reg = <0x838 0x1300>; 160 status = "disabled"; 161 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 162 <&tegra_car TEGRA210_CLK_CILCD>, 163 <&tegra_car TEGRA210_CLK_CILE>, 164 <&tegra_car TEGRA210_CLK_CSI_TPG>; 165 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 166 <&tegra_car TEGRA210_CLK_PLL_P>, 167 <&tegra_car TEGRA210_CLK_PLL_P>; 168 assigned-clock-rates = <102000000>, 169 <102000000>, 170 <102000000>, 171 <972000000>; 172 173 clocks = <&tegra_car TEGRA210_CLK_CSI>, 174 <&tegra_car TEGRA210_CLK_CILAB>, 175 <&tegra_car TEGRA210_CLK_CILCD>, 176 <&tegra_car TEGRA210_CLK_CILE>, 177 <&tegra_car TEGRA210_CLK_CSI_TPG>; 178 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 179 power-domains = <&pd_sor>; 180 }; 181 }; 182 183 tsec@54100000 { 184 compatible = "nvidia,tegra210-tsec"; 185 reg = <0x0 0x54100000 0x0 0x00040000>; 186 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 188 resets = <&tegra_car 83>; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 206 interconnects = <&mc TEGRA210_MC_DISPLAY0A &emc>, 207 <&mc TEGRA210_MC_DISPLAY0B &emc>, 208 <&mc TEGRA210_MC_DISPLAY0C &emc>, 209 <&mc TEGRA210_MC_DISPLAYHC &emc>, 210 <&mc TEGRA210_MC_DISPLAYD &emc>, 211 <&mc TEGRA210_MC_DISPLAYT &emc>; 212 interconnect-names = "wina", 213 "winb", 214 "winc", 215 "cursor", 216 "wind", 217 "wint"; 218 }; 219 220 dc@54240000 { 221 compatible = "nvidia,tegra210-dc"; 222 reg = <0x0 0x54240000 0x0 0x00040000>; 223 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 225 clock-names = "dc"; 226 resets = <&tegra_car 26>; 227 reset-names = "dc"; 228 229 iommus = <&mc TEGRA_SWGROUP_DCB>; 230 231 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 232 nvidia,head = <1>; 233 234 interconnects = <&mc TEGRA210_MC_DISPLAY0AB &emc>, 235 <&mc TEGRA210_MC_DISPLAY0BB &emc>, 236 <&mc TEGRA210_MC_DISPLAY0CB &emc>, 237 <&mc TEGRA210_MC_DISPLAYHCB &emc>; 238 interconnect-names = "wina", 239 "winb", 240 "winc", 241 "cursor"; 242 }; 243 244 dsia: dsi@54300000 { 245 compatible = "nvidia,tegra210-dsi"; 246 reg = <0x0 0x54300000 0x0 0x00040000>; 247 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 248 <&tegra_car TEGRA210_CLK_DSIALP>, 249 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 250 clock-names = "dsi", "lp", "parent"; 251 resets = <&tegra_car 48>; 252 reset-names = "dsi"; 253 power-domains = <&pd_sor>; 254 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 255 256 status = "disabled"; 257 258 #address-cells = <1>; 259 #size-cells = <0>; 260 }; 261 262 vic@54340000 { 263 compatible = "nvidia,tegra210-vic"; 264 reg = <0x0 0x54340000 0x0 0x00040000>; 265 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 267 clock-names = "vic"; 268 resets = <&tegra_car 178>; 269 reset-names = "vic"; 270 271 iommus = <&mc TEGRA_SWGROUP_VIC>; 272 power-domains = <&pd_vic>; 273 }; 274 275 nvjpg@54380000 { 276 compatible = "nvidia,tegra210-nvjpg"; 277 reg = <0x0 0x54380000 0x0 0x00040000>; 278 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 279 clock-names = "nvjpg"; 280 resets = <&tegra_car 195>; 281 reset-names = "nvjpg"; 282 283 iommus = <&mc TEGRA_SWGROUP_NVJPG>; 284 power-domains = <&pd_nvjpg>; 285 }; 286 287 dsib: dsi@54400000 { 288 compatible = "nvidia,tegra210-dsi"; 289 reg = <0x0 0x54400000 0x0 0x00040000>; 290 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 291 <&tegra_car TEGRA210_CLK_DSIBLP>, 292 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 293 clock-names = "dsi", "lp", "parent"; 294 resets = <&tegra_car 82>; 295 reset-names = "dsi"; 296 power-domains = <&pd_sor>; 297 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 298 299 status = "disabled"; 300 301 #address-cells = <1>; 302 #size-cells = <0>; 303 }; 304 305 nvdec@54480000 { 306 compatible = "nvidia,tegra210-nvdec"; 307 reg = <0x0 0x54480000 0x0 0x00040000>; 308 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 309 clock-names = "nvdec"; 310 resets = <&tegra_car 194>; 311 reset-names = "nvdec"; 312 313 iommus = <&mc TEGRA_SWGROUP_NVDEC>; 314 power-domains = <&pd_nvdec>; 315 }; 316 317 nvenc@544c0000 { 318 compatible = "nvidia,tegra210-nvenc"; 319 reg = <0x0 0x544c0000 0x0 0x00040000>; 320 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 321 clock-names = "nvenc"; 322 resets = <&tegra_car 219>; 323 reset-names = "nvenc"; 324 325 iommus = <&mc TEGRA_SWGROUP_NVENC>; 326 power-domains = <&pd_nvenc>; 327 }; 328 329 tsec@54500000 { 330 compatible = "nvidia,tegra210-tsec"; 331 reg = <0x0 0x54500000 0x0 0x00040000>; 332 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 334 clock-names = "tsec"; 335 resets = <&tegra_car 206>; 336 reset-names = "tsec"; 337 status = "disabled"; 338 }; 339 340 sor0: sor@54540000 { 341 compatible = "nvidia,tegra210-sor"; 342 reg = <0x0 0x54540000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 345 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 346 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 347 <&tegra_car TEGRA210_CLK_PLL_DP>, 348 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 349 clock-names = "sor", "out", "parent", "dp", "safe"; 350 resets = <&tegra_car 182>; 351 reset-names = "sor"; 352 pinctrl-0 = <&state_dpaux_aux>; 353 pinctrl-1 = <&state_dpaux_i2c>; 354 pinctrl-2 = <&state_dpaux_off>; 355 pinctrl-names = "aux", "i2c", "off"; 356 power-domains = <&pd_sor>; 357 status = "disabled"; 358 }; 359 360 sor1: sor@54580000 { 361 compatible = "nvidia,tegra210-sor1"; 362 reg = <0x0 0x54580000 0x0 0x00040000>; 363 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 365 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 366 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 367 <&tegra_car TEGRA210_CLK_PLL_DP>, 368 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 369 clock-names = "sor", "out", "parent", "dp", "safe"; 370 resets = <&tegra_car 183>; 371 reset-names = "sor"; 372 pinctrl-0 = <&state_dpaux1_aux>; 373 pinctrl-1 = <&state_dpaux1_i2c>; 374 pinctrl-2 = <&state_dpaux1_off>; 375 pinctrl-names = "aux", "i2c", "off"; 376 power-domains = <&pd_sor>; 377 status = "disabled"; 378 }; 379 380 dpaux: dpaux@545c0000 { 381 compatible = "nvidia,tegra210-dpaux"; 382 reg = <0x0 0x545c0000 0x0 0x00040000>; 383 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 385 <&tegra_car TEGRA210_CLK_PLL_DP>; 386 clock-names = "dpaux", "parent"; 387 resets = <&tegra_car 181>; 388 reset-names = "dpaux"; 389 power-domains = <&pd_sor>; 390 status = "disabled"; 391 392 state_dpaux_aux: pinmux-aux { 393 groups = "dpaux-io"; 394 function = "aux"; 395 }; 396 397 state_dpaux_i2c: pinmux-i2c { 398 groups = "dpaux-io"; 399 function = "i2c"; 400 }; 401 402 state_dpaux_off: pinmux-off { 403 groups = "dpaux-io"; 404 function = "off"; 405 }; 406 407 i2c-bus { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 }; 411 }; 412 413 isp@54600000 { 414 compatible = "nvidia,tegra210-isp"; 415 reg = <0x0 0x54600000 0x0 0x00040000>; 416 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 418 resets = <&tegra_car 23>; 419 reset-names = "isp"; 420 status = "disabled"; 421 }; 422 423 isp@54680000 { 424 compatible = "nvidia,tegra210-isp"; 425 reg = <0x0 0x54680000 0x0 0x00040000>; 426 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 428 resets = <&tegra_car 3>; 429 reset-names = "isp"; 430 status = "disabled"; 431 }; 432 433 i2c@546c0000 { 434 compatible = "nvidia,tegra210-i2c-vi"; 435 reg = <0x0 0x546c0000 0x0 0x00040000>; 436 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 438 <&tegra_car TEGRA210_CLK_I2CSLOW>; 439 clock-names = "div-clk", "slow"; 440 resets = <&tegra_car 208>; 441 reset-names = "i2c"; 442 power-domains = <&pd_venc>; 443 status = "disabled"; 444 445 #address-cells = <1>; 446 #size-cells = <0>; 447 }; 448 }; 449 450 gic: interrupt-controller@50041000 { 451 compatible = "arm,gic-400"; 452 #address-cells = <0>; 453 #interrupt-cells = <3>; 454 interrupt-controller; 455 reg = <0x0 0x50041000 0x0 0x1000>, 456 <0x0 0x50042000 0x0 0x2000>, 457 <0x0 0x50044000 0x0 0x2000>, 458 <0x0 0x50046000 0x0 0x2000>; 459 interrupts = <GIC_PPI 9 460 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 461 interrupt-parent = <&gic>; 462 }; 463 464 gpu@57000000 { 465 compatible = "nvidia,gm20b"; 466 reg = <0x0 0x57000000 0x0 0x01000000>, 467 <0x0 0x58000000 0x0 0x01000000>; 468 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "stall", "nonstall"; 471 clocks = <&tegra_car TEGRA210_CLK_GPU>, 472 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 473 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 474 clock-names = "gpu", "pwr", "ref"; 475 resets = <&tegra_car 184>; 476 reset-names = "gpu"; 477 478 iommus = <&mc TEGRA_SWGROUP_GPU>; 479 480 status = "disabled"; 481 }; 482 483 lic: interrupt-controller@60004000 { 484 compatible = "nvidia,tegra210-ictlr"; 485 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 486 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 487 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 488 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 489 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 490 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 491 interrupt-controller; 492 #interrupt-cells = <3>; 493 interrupt-parent = <&gic>; 494 }; 495 496 timer@60005000 { 497 compatible = "nvidia,tegra210-timer"; 498 reg = <0x0 0x60005000 0x0 0x400>; 499 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 514 clock-names = "timer"; 515 }; 516 517 tegra_car: clock@60006000 { 518 compatible = "nvidia,tegra210-car"; 519 reg = <0x0 0x60006000 0x0 0x1000>; 520 #clock-cells = <1>; 521 #reset-cells = <1>; 522 }; 523 524 flow-controller@60007000 { 525 compatible = "nvidia,tegra210-flowctrl"; 526 reg = <0x0 0x60007000 0x0 0x1000>; 527 }; 528 529 actmon@6000c800 { 530 compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; 531 reg = <0x0 0x6000c800 0x0 0x400>; 532 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&tegra_car TEGRA210_CLK_ACTMON>, 534 <&tegra_car TEGRA210_CLK_EMC>; 535 clock-names = "actmon", "emc"; 536 resets = <&tegra_car 119>; 537 reset-names = "actmon"; 538 operating-points-v2 = <&emc_bw_dfs_opp_table>; 539 interconnects = <&mc TEGRA210_MC_MPCORER &emc>; 540 interconnect-names = "cpu-read"; 541 #cooling-cells = <2>; 542 }; 543 544 gpio: gpio@6000d000 { 545 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 546 reg = <0x0 0x6000d000 0x0 0x1000>; 547 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 555 #gpio-cells = <2>; 556 gpio-controller; 557 #interrupt-cells = <2>; 558 interrupt-controller; 559 }; 560 561 apbdma: dma-controller@60020000 { 562 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 563 reg = <0x0 0x60020000 0x0 0x1400>; 564 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 597 clock-names = "dma"; 598 resets = <&tegra_car 34>; 599 reset-names = "dma"; 600 #dma-cells = <1>; 601 }; 602 603 apbmisc@70000800 { 604 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 605 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 606 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 607 }; 608 609 pinmux: pinmux@700008d4 { 610 compatible = "nvidia,tegra210-pinmux"; 611 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 612 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 613 614 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 615 sdmmc1 { 616 nvidia,pins = "drive_sdmmc1"; 617 nvidia,pull-down-strength = <0x4>; 618 nvidia,pull-up-strength = <0x3>; 619 }; 620 }; 621 622 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 623 sdmmc1 { 624 nvidia,pins = "drive_sdmmc1"; 625 nvidia,pull-down-strength = <0x8>; 626 nvidia,pull-up-strength = <0x8>; 627 }; 628 }; 629 630 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 631 sdmmc2 { 632 nvidia,pins = "drive_sdmmc2"; 633 nvidia,pull-down-strength = <0x10>; 634 nvidia,pull-up-strength = <0x10>; 635 }; 636 }; 637 638 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 639 sdmmc3 { 640 nvidia,pins = "drive_sdmmc3"; 641 nvidia,pull-down-strength = <0x4>; 642 nvidia,pull-up-strength = <0x3>; 643 }; 644 }; 645 646 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 647 sdmmc3 { 648 nvidia,pins = "drive_sdmmc3"; 649 nvidia,pull-down-strength = <0x8>; 650 nvidia,pull-up-strength = <0x8>; 651 }; 652 }; 653 654 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 655 sdmmc4 { 656 nvidia,pins = "drive_sdmmc4"; 657 nvidia,pull-down-strength = <0x10>; 658 nvidia,pull-up-strength = <0x10>; 659 }; 660 }; 661 }; 662 663 /* 664 * There are two serial driver i.e. 8250 based simple serial 665 * driver and APB DMA based serial driver for higher baudrate 666 * and performance. To enable the 8250 based driver, the compatible 667 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 668 * the APB DMA based serial driver, the compatible is 669 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 670 */ 671 uarta: serial@70006000 { 672 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 673 reg = <0x0 0x70006000 0x0 0x40>; 674 reg-shift = <2>; 675 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 677 resets = <&tegra_car 6>; 678 dmas = <&apbdma 8>, <&apbdma 8>; 679 dma-names = "rx", "tx"; 680 status = "disabled"; 681 }; 682 683 uartb: serial@70006040 { 684 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 685 reg = <0x0 0x70006040 0x0 0x40>; 686 reg-shift = <2>; 687 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 689 resets = <&tegra_car 7>; 690 dmas = <&apbdma 9>, <&apbdma 9>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 uartc: serial@70006200 { 696 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 697 reg = <0x0 0x70006200 0x0 0x40>; 698 reg-shift = <2>; 699 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 701 resets = <&tegra_car 55>; 702 dmas = <&apbdma 10>, <&apbdma 10>; 703 dma-names = "rx", "tx"; 704 status = "disabled"; 705 }; 706 707 uartd: serial@70006300 { 708 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 709 reg = <0x0 0x70006300 0x0 0x40>; 710 reg-shift = <2>; 711 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 713 resets = <&tegra_car 65>; 714 dmas = <&apbdma 19>, <&apbdma 19>; 715 dma-names = "rx", "tx"; 716 status = "disabled"; 717 }; 718 719 pwm: pwm@7000a000 { 720 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 721 reg = <0x0 0x7000a000 0x0 0x100>; 722 #pwm-cells = <2>; 723 clocks = <&tegra_car TEGRA210_CLK_PWM>; 724 resets = <&tegra_car 17>; 725 reset-names = "pwm"; 726 status = "disabled"; 727 }; 728 729 i2c@7000c000 { 730 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 731 reg = <0x0 0x7000c000 0x0 0x100>; 732 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 736 clock-names = "div-clk"; 737 resets = <&tegra_car 12>; 738 reset-names = "i2c"; 739 dmas = <&apbdma 21>, <&apbdma 21>; 740 dma-names = "rx", "tx"; 741 status = "disabled"; 742 }; 743 744 i2c@7000c400 { 745 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 746 reg = <0x0 0x7000c400 0x0 0x100>; 747 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 751 clock-names = "div-clk"; 752 resets = <&tegra_car 54>; 753 reset-names = "i2c"; 754 dmas = <&apbdma 22>, <&apbdma 22>; 755 dma-names = "rx", "tx"; 756 status = "disabled"; 757 }; 758 759 i2c@7000c500 { 760 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 761 reg = <0x0 0x7000c500 0x0 0x100>; 762 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 766 clock-names = "div-clk"; 767 resets = <&tegra_car 67>; 768 reset-names = "i2c"; 769 dmas = <&apbdma 23>, <&apbdma 23>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 i2c@7000c700 { 775 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 776 reg = <0x0 0x7000c700 0x0 0x100>; 777 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 781 clock-names = "div-clk"; 782 resets = <&tegra_car 103>; 783 reset-names = "i2c"; 784 dmas = <&apbdma 26>, <&apbdma 26>; 785 dma-names = "rx", "tx"; 786 pinctrl-0 = <&state_dpaux1_i2c>; 787 pinctrl-1 = <&state_dpaux1_off>; 788 pinctrl-names = "default", "idle"; 789 status = "disabled"; 790 }; 791 792 i2c@7000d000 { 793 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 794 reg = <0x0 0x7000d000 0x0 0x100>; 795 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 799 clock-names = "div-clk"; 800 resets = <&tegra_car 47>; 801 reset-names = "i2c"; 802 dmas = <&apbdma 24>, <&apbdma 24>; 803 dma-names = "rx", "tx"; 804 status = "disabled"; 805 }; 806 807 i2c@7000d100 { 808 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 809 reg = <0x0 0x7000d100 0x0 0x100>; 810 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 814 clock-names = "div-clk"; 815 resets = <&tegra_car 166>; 816 reset-names = "i2c"; 817 dmas = <&apbdma 30>, <&apbdma 30>; 818 dma-names = "rx", "tx"; 819 pinctrl-0 = <&state_dpaux_i2c>; 820 pinctrl-1 = <&state_dpaux_off>; 821 pinctrl-names = "default", "idle"; 822 status = "disabled"; 823 }; 824 825 spi@7000d400 { 826 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 827 reg = <0x0 0x7000d400 0x0 0x200>; 828 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 832 clock-names = "spi"; 833 resets = <&tegra_car 41>; 834 reset-names = "spi"; 835 dmas = <&apbdma 15>, <&apbdma 15>; 836 dma-names = "rx", "tx"; 837 status = "disabled"; 838 }; 839 840 spi@7000d600 { 841 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 842 reg = <0x0 0x7000d600 0x0 0x200>; 843 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 847 clock-names = "spi"; 848 resets = <&tegra_car 44>; 849 reset-names = "spi"; 850 dmas = <&apbdma 16>, <&apbdma 16>; 851 dma-names = "rx", "tx"; 852 status = "disabled"; 853 }; 854 855 spi@7000d800 { 856 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 857 reg = <0x0 0x7000d800 0x0 0x200>; 858 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 862 clock-names = "spi"; 863 resets = <&tegra_car 46>; 864 reset-names = "spi"; 865 dmas = <&apbdma 17>, <&apbdma 17>; 866 dma-names = "rx", "tx"; 867 status = "disabled"; 868 }; 869 870 spi@7000da00 { 871 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 872 reg = <0x0 0x7000da00 0x0 0x200>; 873 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 877 clock-names = "spi"; 878 resets = <&tegra_car 68>; 879 reset-names = "spi"; 880 dmas = <&apbdma 18>, <&apbdma 18>; 881 dma-names = "rx", "tx"; 882 status = "disabled"; 883 }; 884 885 rtc@7000e000 { 886 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 887 reg = <0x0 0x7000e000 0x0 0x100>; 888 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-parent = <&tegra_pmc>; 890 clocks = <&tegra_car TEGRA210_CLK_RTC>; 891 clock-names = "rtc"; 892 }; 893 894 tegra_pmc: pmc@7000e400 { 895 compatible = "nvidia,tegra210-pmc"; 896 reg = <0x0 0x7000e400 0x0 0x400>; 897 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 898 clock-names = "pclk", "clk32k_in"; 899 #clock-cells = <1>; 900 #interrupt-cells = <2>; 901 interrupt-controller; 902 903 pinmux { 904 pex_dpd_disable: pex-dpd-disable { 905 pins = "pex-bias", "pex-clk1", "pex-clk2"; 906 low-power-disable; 907 }; 908 909 pex_dpd_enable: pex-dpd-enable { 910 pins = "pex-bias", "pex-clk1", "pex-clk2"; 911 low-power-enable; 912 }; 913 914 sdmmc1_1v8: sdmmc1-1v8 { 915 pins = "sdmmc1"; 916 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 917 }; 918 919 sdmmc1_3v3: sdmmc1-3v3 { 920 pins = "sdmmc1"; 921 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 922 }; 923 924 sdmmc3_1v8: sdmmc3-1v8 { 925 pins = "sdmmc3"; 926 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 927 }; 928 929 sdmmc3_3v3: sdmmc3-3v3 { 930 pins = "sdmmc3"; 931 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 932 }; 933 934 gpio_1v8: gpio-1v8 { 935 pins = "gpio"; 936 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 937 }; 938 939 gpio_3v3: gpio-3v3 { 940 pins = "gpio"; 941 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 942 }; 943 }; 944 945 powergates { 946 pd_audio: aud { 947 clocks = <&tegra_car TEGRA210_CLK_APE>, 948 <&tegra_car TEGRA210_CLK_APB2APE>; 949 resets = <&tegra_car 198>; 950 #power-domain-cells = <0>; 951 }; 952 953 pd_nvenc: mpe { 954 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 955 resets = <&tegra_car 219>; 956 #power-domain-cells = <0>; 957 }; 958 959 pd_nvdec: nvdec { 960 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 961 resets = <&tegra_car 194>; 962 #power-domain-cells = <0>; 963 }; 964 965 pd_sor: sor { 966 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 967 <&tegra_car TEGRA210_CLK_SOR1>, 968 <&tegra_car TEGRA210_CLK_CILAB>, 969 <&tegra_car TEGRA210_CLK_CILCD>, 970 <&tegra_car TEGRA210_CLK_CILE>, 971 <&tegra_car TEGRA210_CLK_DSIA>, 972 <&tegra_car TEGRA210_CLK_DSIB>, 973 <&tegra_car TEGRA210_CLK_DPAUX>, 974 <&tegra_car TEGRA210_CLK_DPAUX1>, 975 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 976 resets = <&tegra_car TEGRA210_CLK_SOR0>, 977 <&tegra_car TEGRA210_CLK_SOR1>, 978 <&tegra_car TEGRA210_CLK_DSIA>, 979 <&tegra_car TEGRA210_CLK_DSIB>, 980 <&tegra_car TEGRA210_CLK_DPAUX>, 981 <&tegra_car TEGRA210_CLK_DPAUX1>, 982 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 983 #power-domain-cells = <0>; 984 }; 985 986 pd_venc: venc { 987 clocks = <&tegra_car TEGRA210_CLK_VI>, 988 <&tegra_car TEGRA210_CLK_CSI>; 989 resets = <&mc TEGRA210_MC_RESET_VI>, 990 <&tegra_car 20>, 991 <&tegra_car 52>; 992 #power-domain-cells = <0>; 993 }; 994 995 pd_vic: vic { 996 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 997 resets = <&tegra_car 178>; 998 #power-domain-cells = <0>; 999 }; 1000 1001 pd_xusbss: xusba { 1002 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 1003 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 1004 #power-domain-cells = <0>; 1005 }; 1006 1007 pd_xusbdev: xusbb { 1008 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 1009 resets = <&tegra_car 95>; 1010 #power-domain-cells = <0>; 1011 }; 1012 1013 pd_xusbhost: xusbc { 1014 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 1015 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 1016 #power-domain-cells = <0>; 1017 }; 1018 1019 pd_nvjpg: nvjpg { 1020 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 1021 resets = <&tegra_car 195>; 1022 #power-domain-cells = <0>; 1023 }; 1024 }; 1025 }; 1026 1027 fuse@7000f800 { 1028 compatible = "nvidia,tegra210-efuse"; 1029 reg = <0x0 0x7000f800 0x0 0x400>; 1030 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 1031 clock-names = "fuse"; 1032 resets = <&tegra_car 39>; 1033 reset-names = "fuse"; 1034 }; 1035 1036 cec@70015000 { 1037 compatible = "nvidia,tegra210-cec"; 1038 reg = <0x0 0x070015000 0x0 0x1000>; 1039 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&tegra_car TEGRA210_CLK_CEC>; 1041 clock-names = "cec"; 1042 status = "disabled"; 1043 }; 1044 1045 mc: memory-controller@70019000 { 1046 compatible = "nvidia,tegra210-mc"; 1047 reg = <0x0 0x70019000 0x0 0x1000>; 1048 clocks = <&tegra_car TEGRA210_CLK_MC>; 1049 clock-names = "mc"; 1050 1051 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1052 1053 #iommu-cells = <1>; 1054 #reset-cells = <1>; 1055 #interconnect-cells = <1>; 1056 }; 1057 1058 emc: external-memory-controller@7001b000 { 1059 compatible = "nvidia,tegra210-emc"; 1060 reg = <0x0 0x7001b000 0x0 0x1000>, 1061 <0x0 0x7001e000 0x0 0x1000>, 1062 <0x0 0x7001f000 0x0 0x1000>; 1063 clocks = <&tegra_car TEGRA210_CLK_EMC>; 1064 clock-names = "emc"; 1065 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1066 nvidia,memory-controller = <&mc>; 1067 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 1068 1069 #interconnect-cells = <0>; 1070 #cooling-cells = <2>; 1071 }; 1072 1073 sata@70020000 { 1074 compatible = "nvidia,tegra210-ahci"; 1075 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 1076 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 1077 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 1078 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&tegra_car TEGRA210_CLK_SATA>, 1080 <&tegra_car TEGRA210_CLK_SATA_OOB>; 1081 clock-names = "sata", "sata-oob"; 1082 resets = <&tegra_car 124>, 1083 <&tegra_car 129>, 1084 <&tegra_car 123>; 1085 reset-names = "sata", "sata-cold", "sata-oob"; 1086 status = "disabled"; 1087 }; 1088 1089 hda@70030000 { 1090 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1091 reg = <0x0 0x70030000 0x0 0x10000>; 1092 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1094 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1095 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1096 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1097 resets = <&tegra_car 125>, /* hda */ 1098 <&tegra_car 128>, /* hda2hdmi */ 1099 <&tegra_car 111>; /* hda2codec_2x */ 1100 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1101 power-domains = <&pd_sor>; 1102 status = "disabled"; 1103 }; 1104 1105 usb@70090000 { 1106 compatible = "nvidia,tegra210-xusb"; 1107 reg = <0x0 0x70090000 0x0 0x8000>, 1108 <0x0 0x70098000 0x0 0x1000>, 1109 <0x0 0x70099000 0x0 0x1000>; 1110 reg-names = "hcd", "fpci", "ipfs"; 1111 1112 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1114 1115 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1116 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1117 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1118 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1119 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1120 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1121 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1122 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1123 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1124 <&tegra_car TEGRA210_CLK_CLK_M>, 1125 <&tegra_car TEGRA210_CLK_PLL_E>; 1126 clock-names = "xusb_host", "xusb_host_src", 1127 "xusb_falcon_src", "xusb_ss", 1128 "xusb_ss_div2", "xusb_ss_src", 1129 "xusb_hs_src", "xusb_fs_src", 1130 "pll_u_480m", "clk_m", "pll_e"; 1131 resets = <&tegra_car 89>, <&tegra_car 156>, 1132 <&tegra_car 143>; 1133 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1134 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1135 power-domain-names = "xusb_host", "xusb_ss"; 1136 1137 nvidia,xusb-padctl = <&padctl>; 1138 1139 status = "disabled"; 1140 }; 1141 1142 padctl: padctl@7009f000 { 1143 compatible = "nvidia,tegra210-xusb-padctl"; 1144 reg = <0x0 0x7009f000 0x0 0x1000>; 1145 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1146 resets = <&tegra_car 142>; 1147 reset-names = "padctl"; 1148 nvidia,pmc = <&tegra_pmc>; 1149 1150 status = "disabled"; 1151 1152 pads { 1153 usb2 { 1154 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1155 clock-names = "trk"; 1156 status = "disabled"; 1157 1158 lanes { 1159 usb2-0 { 1160 status = "disabled"; 1161 #phy-cells = <0>; 1162 }; 1163 1164 usb2-1 { 1165 status = "disabled"; 1166 #phy-cells = <0>; 1167 }; 1168 1169 usb2-2 { 1170 status = "disabled"; 1171 #phy-cells = <0>; 1172 }; 1173 1174 usb2-3 { 1175 status = "disabled"; 1176 #phy-cells = <0>; 1177 }; 1178 }; 1179 }; 1180 1181 hsic { 1182 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1183 clock-names = "trk"; 1184 status = "disabled"; 1185 1186 lanes { 1187 hsic-0 { 1188 status = "disabled"; 1189 #phy-cells = <0>; 1190 }; 1191 1192 hsic-1 { 1193 status = "disabled"; 1194 #phy-cells = <0>; 1195 }; 1196 }; 1197 }; 1198 1199 pcie { 1200 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1201 clock-names = "pll"; 1202 resets = <&tegra_car 205>; 1203 reset-names = "phy"; 1204 status = "disabled"; 1205 1206 lanes { 1207 pcie-0 { 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 1212 pcie-1 { 1213 status = "disabled"; 1214 #phy-cells = <0>; 1215 }; 1216 1217 pcie-2 { 1218 status = "disabled"; 1219 #phy-cells = <0>; 1220 }; 1221 1222 pcie-3 { 1223 status = "disabled"; 1224 #phy-cells = <0>; 1225 }; 1226 1227 pcie-4 { 1228 status = "disabled"; 1229 #phy-cells = <0>; 1230 }; 1231 1232 pcie-5 { 1233 status = "disabled"; 1234 #phy-cells = <0>; 1235 }; 1236 1237 pcie-6 { 1238 status = "disabled"; 1239 #phy-cells = <0>; 1240 }; 1241 }; 1242 }; 1243 1244 sata { 1245 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1246 clock-names = "pll"; 1247 resets = <&tegra_car 204>; 1248 reset-names = "phy"; 1249 status = "disabled"; 1250 1251 lanes { 1252 sata-0 { 1253 status = "disabled"; 1254 #phy-cells = <0>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 ports { 1261 usb2-0 { 1262 status = "disabled"; 1263 }; 1264 1265 usb2-1 { 1266 status = "disabled"; 1267 }; 1268 1269 usb2-2 { 1270 status = "disabled"; 1271 }; 1272 1273 usb2-3 { 1274 status = "disabled"; 1275 }; 1276 1277 hsic-0 { 1278 status = "disabled"; 1279 }; 1280 1281 usb3-0 { 1282 status = "disabled"; 1283 }; 1284 1285 usb3-1 { 1286 status = "disabled"; 1287 }; 1288 1289 usb3-2 { 1290 status = "disabled"; 1291 }; 1292 1293 usb3-3 { 1294 status = "disabled"; 1295 }; 1296 }; 1297 }; 1298 1299 mmc@700b0000 { 1300 compatible = "nvidia,tegra210-sdhci"; 1301 reg = <0x0 0x700b0000 0x0 0x200>; 1302 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1304 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1305 clock-names = "sdhci", "tmclk"; 1306 resets = <&tegra_car 14>; 1307 reset-names = "sdhci"; 1308 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1309 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1310 pinctrl-0 = <&sdmmc1_3v3>; 1311 pinctrl-1 = <&sdmmc1_1v8>; 1312 pinctrl-2 = <&sdmmc1_3v3_drv>; 1313 pinctrl-3 = <&sdmmc1_1v8_drv>; 1314 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1315 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1316 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1317 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1318 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>; 1319 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>; 1320 nvidia,default-tap = <0x2>; 1321 nvidia,default-trim = <0x4>; 1322 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1323 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1324 <&tegra_car TEGRA210_CLK_PLL_C4>; 1325 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1326 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1327 status = "disabled"; 1328 }; 1329 1330 mmc@700b0200 { 1331 compatible = "nvidia,tegra210-sdhci"; 1332 reg = <0x0 0x700b0200 0x0 0x200>; 1333 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1334 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1335 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1336 clock-names = "sdhci", "tmclk"; 1337 resets = <&tegra_car 9>; 1338 reset-names = "sdhci"; 1339 pinctrl-names = "sdmmc-1v8-drv"; 1340 pinctrl-0 = <&sdmmc2_1v8_drv>; 1341 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1342 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1343 nvidia,default-tap = <0x8>; 1344 nvidia,default-trim = <0x0>; 1345 status = "disabled"; 1346 }; 1347 1348 mmc@700b0400 { 1349 compatible = "nvidia,tegra210-sdhci"; 1350 reg = <0x0 0x700b0400 0x0 0x200>; 1351 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1353 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1354 clock-names = "sdhci", "tmclk"; 1355 resets = <&tegra_car 69>; 1356 reset-names = "sdhci"; 1357 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1358 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1359 pinctrl-0 = <&sdmmc3_3v3>; 1360 pinctrl-1 = <&sdmmc3_1v8>; 1361 pinctrl-2 = <&sdmmc3_3v3_drv>; 1362 pinctrl-3 = <&sdmmc3_1v8_drv>; 1363 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1364 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1365 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1366 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1367 nvidia,default-tap = <0x3>; 1368 nvidia,default-trim = <0x3>; 1369 status = "disabled"; 1370 }; 1371 1372 mmc@700b0600 { 1373 compatible = "nvidia,tegra210-sdhci"; 1374 reg = <0x0 0x700b0600 0x0 0x200>; 1375 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1377 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1378 clock-names = "sdhci", "tmclk"; 1379 resets = <&tegra_car 15>; 1380 reset-names = "sdhci"; 1381 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1382 pinctrl-0 = <&sdmmc4_1v8_drv>; 1383 pinctrl-1 = <&sdmmc4_1v8_drv>; 1384 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1385 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1386 nvidia,default-tap = <0x8>; 1387 nvidia,default-trim = <0x0>; 1388 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1389 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1390 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1391 nvidia,dqs-trim = <40>; 1392 mmc-hs400-1_8v; 1393 status = "disabled"; 1394 }; 1395 1396 usb@700d0000 { 1397 compatible = "nvidia,tegra210-xudc"; 1398 reg = <0x0 0x700d0000 0x0 0x8000>, 1399 <0x0 0x700d8000 0x0 0x1000>, 1400 <0x0 0x700d9000 0x0 0x1000>; 1401 reg-names = "base", "fpci", "ipfs"; 1402 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1403 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1404 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1405 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1406 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1407 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1408 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1409 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1410 power-domain-names = "dev", "ss"; 1411 nvidia,xusb-padctl = <&padctl>; 1412 status = "disabled"; 1413 }; 1414 1415 soctherm: thermal-sensor@700e2000 { 1416 compatible = "nvidia,tegra210-soctherm"; 1417 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1418 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1419 reg-names = "soctherm-reg", "car-reg"; 1420 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1422 interrupt-names = "thermal", "edp"; 1423 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1424 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1425 clock-names = "tsensor", "soctherm"; 1426 resets = <&tegra_car 78>; 1427 reset-names = "soctherm"; 1428 #thermal-sensor-cells = <1>; 1429 1430 throttle-cfgs { 1431 throttle_heavy: heavy { 1432 nvidia,priority = <100>; 1433 nvidia,cpu-throt-percent = <85>; 1434 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1435 1436 #cooling-cells = <2>; 1437 }; 1438 }; 1439 }; 1440 1441 mipi: mipi@700e3000 { 1442 compatible = "nvidia,tegra210-mipi"; 1443 reg = <0x0 0x700e3000 0x0 0x100>; 1444 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1445 clock-names = "mipi-cal"; 1446 power-domains = <&pd_sor>; 1447 #nvidia,mipi-calibrate-cells = <1>; 1448 }; 1449 1450 dfll: clock@70110000 { 1451 compatible = "nvidia,tegra210-dfll"; 1452 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1453 <0 0x70110000 0 0x100>, /* I2C output control */ 1454 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1455 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1456 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1457 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1458 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1459 <&tegra_car TEGRA210_CLK_I2C5>; 1460 clock-names = "soc", "ref", "i2c"; 1461 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1462 <&tegra_car 155>; 1463 reset-names = "dvco", "dfll"; 1464 #clock-cells = <0>; 1465 clock-output-names = "dfllCPU_out"; 1466 status = "disabled"; 1467 }; 1468 1469 aconnect@702c0000 { 1470 compatible = "nvidia,tegra210-aconnect"; 1471 clocks = <&tegra_car TEGRA210_CLK_APE>, 1472 <&tegra_car TEGRA210_CLK_APB2APE>; 1473 clock-names = "ape", "apb2ape"; 1474 power-domains = <&pd_audio>; 1475 #address-cells = <1>; 1476 #size-cells = <1>; 1477 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1478 status = "disabled"; 1479 1480 tegra_ahub: ahub@702d0800 { 1481 compatible = "nvidia,tegra210-ahub"; 1482 reg = <0x702d0800 0x800>; 1483 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1484 clock-names = "ahub"; 1485 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1486 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; 1487 assigned-clock-rates = <81600000>; 1488 #address-cells = <1>; 1489 #size-cells = <1>; 1490 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1491 status = "disabled"; 1492 1493 tegra_admaif: admaif@702d0000 { 1494 compatible = "nvidia,tegra210-admaif"; 1495 reg = <0x702d0000 0x800>; 1496 dmas = <&adma 1>, <&adma 1>, 1497 <&adma 2>, <&adma 2>, 1498 <&adma 3>, <&adma 3>, 1499 <&adma 4>, <&adma 4>, 1500 <&adma 5>, <&adma 5>, 1501 <&adma 6>, <&adma 6>, 1502 <&adma 7>, <&adma 7>, 1503 <&adma 8>, <&adma 8>, 1504 <&adma 9>, <&adma 9>, 1505 <&adma 10>, <&adma 10>; 1506 dma-names = "rx1", "tx1", 1507 "rx2", "tx2", 1508 "rx3", "tx3", 1509 "rx4", "tx4", 1510 "rx5", "tx5", 1511 "rx6", "tx6", 1512 "rx7", "tx7", 1513 "rx8", "tx8", 1514 "rx9", "tx9", 1515 "rx10", "tx10"; 1516 status = "disabled"; 1517 1518 ports { 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 1522 admaif1_port: port@0 { 1523 reg = <0>; 1524 1525 admaif1_ep: endpoint { 1526 remote-endpoint = <&xbar_admaif1_ep>; 1527 }; 1528 }; 1529 1530 admaif2_port: port@1 { 1531 reg = <1>; 1532 1533 admaif2_ep: endpoint { 1534 remote-endpoint = <&xbar_admaif2_ep>; 1535 }; 1536 }; 1537 1538 admaif3_port: port@2 { 1539 reg = <2>; 1540 1541 admaif3_ep: endpoint { 1542 remote-endpoint = <&xbar_admaif3_ep>; 1543 }; 1544 }; 1545 1546 admaif4_port: port@3 { 1547 reg = <3>; 1548 1549 admaif4_ep: endpoint { 1550 remote-endpoint = <&xbar_admaif4_ep>; 1551 }; 1552 }; 1553 1554 admaif5_port: port@4 { 1555 reg = <4>; 1556 1557 admaif5_ep: endpoint { 1558 remote-endpoint = <&xbar_admaif5_ep>; 1559 }; 1560 }; 1561 1562 admaif6_port: port@5 { 1563 reg = <5>; 1564 1565 admaif6_ep: endpoint { 1566 remote-endpoint = <&xbar_admaif6_ep>; 1567 }; 1568 }; 1569 1570 admaif7_port: port@6 { 1571 reg = <6>; 1572 1573 admaif7_ep: endpoint { 1574 remote-endpoint = <&xbar_admaif7_ep>; 1575 }; 1576 }; 1577 1578 admaif8_port: port@7 { 1579 reg = <7>; 1580 1581 admaif8_ep: endpoint { 1582 remote-endpoint = <&xbar_admaif8_ep>; 1583 }; 1584 }; 1585 1586 admaif9_port: port@8 { 1587 reg = <8>; 1588 1589 admaif9_ep: endpoint { 1590 remote-endpoint = <&xbar_admaif9_ep>; 1591 }; 1592 }; 1593 1594 admaif10_port: port@9 { 1595 reg = <9>; 1596 1597 admaif10_ep: endpoint { 1598 remote-endpoint = <&xbar_admaif10_ep>; 1599 }; 1600 }; 1601 }; 1602 }; 1603 1604 tegra_i2s1: i2s@702d1000 { 1605 compatible = "nvidia,tegra210-i2s"; 1606 reg = <0x702d1000 0x100>; 1607 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1608 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1609 clock-names = "i2s", "sync_input"; 1610 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1611 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1612 assigned-clock-rates = <1536000>; 1613 sound-name-prefix = "I2S1"; 1614 status = "disabled"; 1615 }; 1616 1617 tegra_i2s2: i2s@702d1100 { 1618 compatible = "nvidia,tegra210-i2s"; 1619 reg = <0x702d1100 0x100>; 1620 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1621 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1622 clock-names = "i2s", "sync_input"; 1623 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1624 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1625 assigned-clock-rates = <1536000>; 1626 sound-name-prefix = "I2S2"; 1627 status = "disabled"; 1628 }; 1629 1630 tegra_i2s3: i2s@702d1200 { 1631 compatible = "nvidia,tegra210-i2s"; 1632 reg = <0x702d1200 0x100>; 1633 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1634 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1635 clock-names = "i2s", "sync_input"; 1636 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1637 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1638 assigned-clock-rates = <1536000>; 1639 sound-name-prefix = "I2S3"; 1640 status = "disabled"; 1641 }; 1642 1643 tegra_i2s4: i2s@702d1300 { 1644 compatible = "nvidia,tegra210-i2s"; 1645 reg = <0x702d1300 0x100>; 1646 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1647 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1648 clock-names = "i2s", "sync_input"; 1649 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1650 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1651 assigned-clock-rates = <1536000>; 1652 sound-name-prefix = "I2S4"; 1653 status = "disabled"; 1654 }; 1655 1656 tegra_i2s5: i2s@702d1400 { 1657 compatible = "nvidia,tegra210-i2s"; 1658 reg = <0x702d1400 0x100>; 1659 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1660 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1661 clock-names = "i2s", "sync_input"; 1662 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1663 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1664 assigned-clock-rates = <1536000>; 1665 sound-name-prefix = "I2S5"; 1666 status = "disabled"; 1667 }; 1668 1669 tegra_sfc1: sfc@702d2000 { 1670 compatible = "nvidia,tegra210-sfc"; 1671 reg = <0x702d2000 0x200>; 1672 sound-name-prefix = "SFC1"; 1673 status = "disabled"; 1674 }; 1675 1676 tegra_sfc2: sfc@702d2200 { 1677 compatible = "nvidia,tegra210-sfc"; 1678 reg = <0x702d2200 0x200>; 1679 sound-name-prefix = "SFC2"; 1680 status = "disabled"; 1681 }; 1682 1683 tegra_sfc3: sfc@702d2400 { 1684 compatible = "nvidia,tegra210-sfc"; 1685 reg = <0x702d2400 0x200>; 1686 sound-name-prefix = "SFC3"; 1687 status = "disabled"; 1688 }; 1689 1690 tegra_sfc4: sfc@702d2600 { 1691 compatible = "nvidia,tegra210-sfc"; 1692 reg = <0x702d2600 0x200>; 1693 sound-name-prefix = "SFC4"; 1694 status = "disabled"; 1695 }; 1696 1697 tegra_amx1: amx@702d3000 { 1698 compatible = "nvidia,tegra210-amx"; 1699 reg = <0x702d3000 0x100>; 1700 sound-name-prefix = "AMX1"; 1701 status = "disabled"; 1702 }; 1703 1704 tegra_amx2: amx@702d3100 { 1705 compatible = "nvidia,tegra210-amx"; 1706 reg = <0x702d3100 0x100>; 1707 sound-name-prefix = "AMX2"; 1708 status = "disabled"; 1709 }; 1710 1711 tegra_adx1: adx@702d3800 { 1712 compatible = "nvidia,tegra210-adx"; 1713 reg = <0x702d3800 0x100>; 1714 sound-name-prefix = "ADX1"; 1715 status = "disabled"; 1716 }; 1717 1718 tegra_adx2: adx@702d3900 { 1719 compatible = "nvidia,tegra210-adx"; 1720 reg = <0x702d3900 0x100>; 1721 sound-name-prefix = "ADX2"; 1722 status = "disabled"; 1723 }; 1724 1725 tegra_dmic1: dmic@702d4000 { 1726 compatible = "nvidia,tegra210-dmic"; 1727 reg = <0x702d4000 0x100>; 1728 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1729 clock-names = "dmic"; 1730 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1731 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1732 assigned-clock-rates = <3072000>; 1733 sound-name-prefix = "DMIC1"; 1734 status = "disabled"; 1735 }; 1736 1737 tegra_dmic2: dmic@702d4100 { 1738 compatible = "nvidia,tegra210-dmic"; 1739 reg = <0x702d4100 0x100>; 1740 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1741 clock-names = "dmic"; 1742 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1743 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1744 assigned-clock-rates = <3072000>; 1745 sound-name-prefix = "DMIC2"; 1746 status = "disabled"; 1747 }; 1748 1749 tegra_dmic3: dmic@702d4200 { 1750 compatible = "nvidia,tegra210-dmic"; 1751 reg = <0x702d4200 0x100>; 1752 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1753 clock-names = "dmic"; 1754 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1755 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1756 assigned-clock-rates = <3072000>; 1757 sound-name-prefix = "DMIC3"; 1758 status = "disabled"; 1759 }; 1760 1761 tegra_ope1: processing-engine@702d8000 { 1762 compatible = "nvidia,tegra210-ope"; 1763 reg = <0x702d8000 0x100>; 1764 #address-cells = <1>; 1765 #size-cells = <1>; 1766 ranges; 1767 sound-name-prefix = "OPE1"; 1768 status = "disabled"; 1769 1770 equalizer@702d8100 { 1771 compatible = "nvidia,tegra210-peq"; 1772 reg = <0x702d8100 0x100>; 1773 }; 1774 1775 dynamic-range-compressor@702d8200 { 1776 compatible = "nvidia,tegra210-mbdrc"; 1777 reg = <0x702d8200 0x200>; 1778 }; 1779 }; 1780 1781 tegra_ope2: processing-engine@702d8400 { 1782 compatible = "nvidia,tegra210-ope"; 1783 reg = <0x702d8400 0x100>; 1784 #address-cells = <1>; 1785 #size-cells = <1>; 1786 ranges; 1787 sound-name-prefix = "OPE2"; 1788 status = "disabled"; 1789 1790 equalizer@702d8500 { 1791 compatible = "nvidia,tegra210-peq"; 1792 reg = <0x702d8500 0x100>; 1793 }; 1794 1795 dynamic-range-compressor@702d8600 { 1796 compatible = "nvidia,tegra210-mbdrc"; 1797 reg = <0x702d8600 0x200>; 1798 }; 1799 }; 1800 1801 tegra_mvc1: mvc@702da000 { 1802 compatible = "nvidia,tegra210-mvc"; 1803 reg = <0x702da000 0x200>; 1804 sound-name-prefix = "MVC1"; 1805 status = "disabled"; 1806 }; 1807 1808 tegra_mvc2: mvc@702da200 { 1809 compatible = "nvidia,tegra210-mvc"; 1810 reg = <0x702da200 0x200>; 1811 sound-name-prefix = "MVC2"; 1812 status = "disabled"; 1813 }; 1814 1815 tegra_amixer: amixer@702dbb00 { 1816 compatible = "nvidia,tegra210-amixer"; 1817 reg = <0x702dbb00 0x800>; 1818 sound-name-prefix = "MIXER1"; 1819 status = "disabled"; 1820 }; 1821 1822 ports { 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 port@0 { 1827 reg = <0x0>; 1828 1829 xbar_admaif1_ep: endpoint { 1830 remote-endpoint = <&admaif1_ep>; 1831 }; 1832 }; 1833 1834 port@1 { 1835 reg = <0x1>; 1836 1837 xbar_admaif2_ep: endpoint { 1838 remote-endpoint = <&admaif2_ep>; 1839 }; 1840 }; 1841 1842 port@2 { 1843 reg = <0x2>; 1844 1845 xbar_admaif3_ep: endpoint { 1846 remote-endpoint = <&admaif3_ep>; 1847 }; 1848 }; 1849 1850 port@3 { 1851 reg = <0x3>; 1852 1853 xbar_admaif4_ep: endpoint { 1854 remote-endpoint = <&admaif4_ep>; 1855 }; 1856 }; 1857 1858 port@4 { 1859 reg = <0x4>; 1860 xbar_admaif5_ep: endpoint { 1861 remote-endpoint = <&admaif5_ep>; 1862 }; 1863 }; 1864 port@5 { 1865 reg = <0x5>; 1866 1867 xbar_admaif6_ep: endpoint { 1868 remote-endpoint = <&admaif6_ep>; 1869 }; 1870 }; 1871 1872 port@6 { 1873 reg = <0x6>; 1874 1875 xbar_admaif7_ep: endpoint { 1876 remote-endpoint = <&admaif7_ep>; 1877 }; 1878 }; 1879 1880 port@7 { 1881 reg = <0x7>; 1882 1883 xbar_admaif8_ep: endpoint { 1884 remote-endpoint = <&admaif8_ep>; 1885 }; 1886 }; 1887 1888 port@8 { 1889 reg = <0x8>; 1890 1891 xbar_admaif9_ep: endpoint { 1892 remote-endpoint = <&admaif9_ep>; 1893 }; 1894 }; 1895 1896 port@9 { 1897 reg = <0x9>; 1898 1899 xbar_admaif10_ep: endpoint { 1900 remote-endpoint = <&admaif10_ep>; 1901 }; 1902 }; 1903 }; 1904 }; 1905 1906 adma: dma-controller@702e2000 { 1907 compatible = "nvidia,tegra210-adma"; 1908 reg = <0x702e2000 0x2000>; 1909 interrupt-parent = <&agic>; 1910 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1932 #dma-cells = <1>; 1933 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1934 clock-names = "d_audio"; 1935 status = "disabled"; 1936 }; 1937 1938 agic: interrupt-controller@702f9000 { 1939 compatible = "nvidia,tegra210-agic"; 1940 #interrupt-cells = <3>; 1941 interrupt-controller; 1942 reg = <0x702f9000 0x1000>, 1943 <0x702fa000 0x2000>; 1944 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1945 clocks = <&tegra_car TEGRA210_CLK_APE>; 1946 clock-names = "clk"; 1947 status = "disabled"; 1948 }; 1949 }; 1950 1951 spi@70410000 { 1952 compatible = "nvidia,tegra210-qspi"; 1953 reg = <0x0 0x70410000 0x0 0x1000>; 1954 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1958 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1959 clock-names = "qspi", "qspi_out"; 1960 resets = <&tegra_car 211>; 1961 dmas = <&apbdma 5>, <&apbdma 5>; 1962 dma-names = "rx", "tx"; 1963 status = "disabled"; 1964 }; 1965 1966 usb@7d000000 { 1967 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1968 reg = <0x0 0x7d000000 0x0 0x4000>; 1969 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1970 phy_type = "utmi"; 1971 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1972 clock-names = "usb"; 1973 resets = <&tegra_car 22>; 1974 reset-names = "usb"; 1975 nvidia,phy = <&phy1>; 1976 status = "disabled"; 1977 }; 1978 1979 phy1: usb-phy@7d000000 { 1980 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1981 reg = <0x0 0x7d000000 0x0 0x4000>, 1982 <0x0 0x7d000000 0x0 0x4000>; 1983 phy_type = "utmi"; 1984 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1985 <&tegra_car TEGRA210_CLK_PLL_U>, 1986 <&tegra_car TEGRA210_CLK_USBD>; 1987 clock-names = "reg", "pll_u", "utmi-pads"; 1988 resets = <&tegra_car 22>, <&tegra_car 22>; 1989 reset-names = "usb", "utmi-pads"; 1990 nvidia,hssync-start-delay = <0>; 1991 nvidia,idle-wait-delay = <17>; 1992 nvidia,elastic-limit = <16>; 1993 nvidia,term-range-adj = <6>; 1994 nvidia,xcvr-setup = <9>; 1995 nvidia,xcvr-lsfslew = <0>; 1996 nvidia,xcvr-lsrslew = <3>; 1997 nvidia,hssquelch-level = <2>; 1998 nvidia,hsdiscon-level = <5>; 1999 nvidia,xcvr-hsslew = <12>; 2000 nvidia,has-utmi-pad-registers; 2001 status = "disabled"; 2002 }; 2003 2004 usb@7d004000 { 2005 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 2006 reg = <0x0 0x7d004000 0x0 0x4000>; 2007 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 2008 phy_type = "utmi"; 2009 clocks = <&tegra_car TEGRA210_CLK_USB2>; 2010 clock-names = "usb"; 2011 resets = <&tegra_car 58>; 2012 reset-names = "usb"; 2013 nvidia,phy = <&phy2>; 2014 status = "disabled"; 2015 }; 2016 2017 phy2: usb-phy@7d004000 { 2018 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 2019 reg = <0x0 0x7d004000 0x0 0x4000>, 2020 <0x0 0x7d000000 0x0 0x4000>; 2021 phy_type = "utmi"; 2022 clocks = <&tegra_car TEGRA210_CLK_USB2>, 2023 <&tegra_car TEGRA210_CLK_PLL_U>, 2024 <&tegra_car TEGRA210_CLK_USBD>; 2025 clock-names = "reg", "pll_u", "utmi-pads"; 2026 resets = <&tegra_car 58>, <&tegra_car 22>; 2027 reset-names = "usb", "utmi-pads"; 2028 nvidia,hssync-start-delay = <0>; 2029 nvidia,idle-wait-delay = <17>; 2030 nvidia,elastic-limit = <16>; 2031 nvidia,term-range-adj = <6>; 2032 nvidia,xcvr-setup = <9>; 2033 nvidia,xcvr-lsfslew = <0>; 2034 nvidia,xcvr-lsrslew = <3>; 2035 nvidia,hssquelch-level = <2>; 2036 nvidia,hsdiscon-level = <5>; 2037 nvidia,xcvr-hsslew = <12>; 2038 status = "disabled"; 2039 }; 2040 2041 cpus { 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 2045 cpu@0 { 2046 device_type = "cpu"; 2047 compatible = "arm,cortex-a57"; 2048 reg = <0>; 2049 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 2050 <&tegra_car TEGRA210_CLK_PLL_X>, 2051 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 2052 <&dfll>; 2053 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 2054 clock-latency = <300000>; 2055 cpu-idle-states = <&CPU_SLEEP>; 2056 next-level-cache = <&L2>; 2057 }; 2058 2059 cpu@1 { 2060 device_type = "cpu"; 2061 compatible = "arm,cortex-a57"; 2062 reg = <1>; 2063 cpu-idle-states = <&CPU_SLEEP>; 2064 next-level-cache = <&L2>; 2065 }; 2066 2067 cpu@2 { 2068 device_type = "cpu"; 2069 compatible = "arm,cortex-a57"; 2070 reg = <2>; 2071 cpu-idle-states = <&CPU_SLEEP>; 2072 next-level-cache = <&L2>; 2073 }; 2074 2075 cpu@3 { 2076 device_type = "cpu"; 2077 compatible = "arm,cortex-a57"; 2078 reg = <3>; 2079 cpu-idle-states = <&CPU_SLEEP>; 2080 next-level-cache = <&L2>; 2081 }; 2082 2083 idle-states { 2084 entry-method = "psci"; 2085 2086 CPU_SLEEP: cpu-sleep { 2087 compatible = "arm,idle-state"; 2088 arm,psci-suspend-param = <0x40000007>; 2089 entry-latency-us = <100>; 2090 exit-latency-us = <30>; 2091 min-residency-us = <1000>; 2092 wakeup-latency-us = <130>; 2093 idle-state-name = "cpu-sleep"; 2094 status = "disabled"; 2095 }; 2096 }; 2097 2098 L2: l2-cache { 2099 compatible = "cache"; 2100 cache-level = <2>; 2101 cache-unified; 2102 }; 2103 }; 2104 2105 pmu { 2106 compatible = "arm,cortex-a57-pmu"; 2107 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2111 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2112 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2113 }; 2114 2115 sound { 2116 status = "disabled"; 2117 2118 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2119 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2120 clock-names = "pll_a", "plla_out0"; 2121 2122 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2123 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2124 <&tegra_car TEGRA210_CLK_EXTERN1>; 2125 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2126 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2127 }; 2128 2129 thermal-zones { 2130 cpu-thermal { 2131 polling-delay-passive = <1000>; 2132 polling-delay = <0>; 2133 2134 thermal-sensors = 2135 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2136 2137 trips { 2138 cpu-shutdown-trip { 2139 temperature = <102500>; 2140 hysteresis = <0>; 2141 type = "critical"; 2142 }; 2143 2144 cpu_throttle_trip: throttle-trip { 2145 temperature = <98500>; 2146 hysteresis = <1000>; 2147 type = "hot"; 2148 }; 2149 }; 2150 2151 cooling-maps { 2152 map0 { 2153 trip = <&cpu_throttle_trip>; 2154 cooling-device = <&throttle_heavy 1 1>; 2155 }; 2156 }; 2157 }; 2158 2159 mem-thermal { 2160 polling-delay-passive = <0>; 2161 polling-delay = <0>; 2162 2163 thermal-sensors = 2164 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2165 2166 trips { 2167 dram_nominal: mem-nominal-trip { 2168 temperature = <50000>; 2169 hysteresis = <1000>; 2170 type = "passive"; 2171 }; 2172 2173 dram_throttle: mem-throttle-trip { 2174 temperature = <70000>; 2175 hysteresis = <1000>; 2176 type = "active"; 2177 }; 2178 2179 mem-hot-trip { 2180 temperature = <100000>; 2181 hysteresis = <1000>; 2182 type = "hot"; 2183 }; 2184 2185 mem-shutdown-trip { 2186 temperature = <103000>; 2187 hysteresis = <0>; 2188 type = "critical"; 2189 }; 2190 }; 2191 2192 cooling-maps { 2193 dram-passive { 2194 cooling-device = <&emc 0 0>; 2195 trip = <&dram_nominal>; 2196 }; 2197 2198 dram-active { 2199 cooling-device = <&emc 1 1>; 2200 trip = <&dram_throttle>; 2201 }; 2202 }; 2203 }; 2204 2205 gpu-thermal { 2206 polling-delay-passive = <1000>; 2207 polling-delay = <0>; 2208 2209 thermal-sensors = 2210 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2211 2212 trips { 2213 gpu-shutdown-trip { 2214 temperature = <103000>; 2215 hysteresis = <0>; 2216 type = "critical"; 2217 }; 2218 2219 gpu_throttle_trip: throttle-trip { 2220 temperature = <100000>; 2221 hysteresis = <1000>; 2222 type = "hot"; 2223 }; 2224 }; 2225 2226 cooling-maps { 2227 map0 { 2228 trip = <&gpu_throttle_trip>; 2229 cooling-device = <&throttle_heavy 1 1>; 2230 }; 2231 }; 2232 }; 2233 2234 pllx-thermal { 2235 polling-delay-passive = <0>; 2236 polling-delay = <0>; 2237 2238 thermal-sensors = 2239 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2240 2241 trips { 2242 pllx-shutdown-trip { 2243 temperature = <103000>; 2244 hysteresis = <0>; 2245 type = "critical"; 2246 }; 2247 2248 pllx-throttle-trip { 2249 temperature = <100000>; 2250 hysteresis = <1000>; 2251 type = "hot"; 2252 }; 2253 }; 2254 2255 cooling-maps { 2256 /* 2257 * There are currently no cooling maps, 2258 * because there are no cooling devices. 2259 */ 2260 }; 2261 }; 2262 }; 2263 2264 timer { 2265 compatible = "arm,armv8-timer"; 2266 interrupts = <GIC_PPI 13 2267 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2268 <GIC_PPI 14 2269 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2270 <GIC_PPI 11 2271 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2272 <GIC_PPI 10 2273 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2274 interrupt-parent = <&gic>; 2275 arm,no-tick-in-suspend; 2276 }; 2277}; 2278