1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>; 235 assigned-clock-rates = <81600000>; 236 status = "disabled"; 237 238 #address-cells = <2>; 239 #size-cells = <2>; 240 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 241 242 tegra_i2s1: i2s@2901000 { 243 compatible = "nvidia,tegra194-i2s", 244 "nvidia,tegra210-i2s"; 245 reg = <0x0 0x2901000 0x0 0x100>; 246 clocks = <&bpmp TEGRA194_CLK_I2S1>, 247 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 248 clock-names = "i2s", "sync_input"; 249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 251 assigned-clock-rates = <1536000>; 252 sound-name-prefix = "I2S1"; 253 status = "disabled"; 254 }; 255 256 tegra_i2s2: i2s@2901100 { 257 compatible = "nvidia,tegra194-i2s", 258 "nvidia,tegra210-i2s"; 259 reg = <0x0 0x2901100 0x0 0x100>; 260 clocks = <&bpmp TEGRA194_CLK_I2S2>, 261 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 262 clock-names = "i2s", "sync_input"; 263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 265 assigned-clock-rates = <1536000>; 266 sound-name-prefix = "I2S2"; 267 status = "disabled"; 268 }; 269 270 tegra_i2s3: i2s@2901200 { 271 compatible = "nvidia,tegra194-i2s", 272 "nvidia,tegra210-i2s"; 273 reg = <0x0 0x2901200 0x0 0x100>; 274 clocks = <&bpmp TEGRA194_CLK_I2S3>, 275 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 276 clock-names = "i2s", "sync_input"; 277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 279 assigned-clock-rates = <1536000>; 280 sound-name-prefix = "I2S3"; 281 status = "disabled"; 282 }; 283 284 tegra_i2s4: i2s@2901300 { 285 compatible = "nvidia,tegra194-i2s", 286 "nvidia,tegra210-i2s"; 287 reg = <0x0 0x2901300 0x0 0x100>; 288 clocks = <&bpmp TEGRA194_CLK_I2S4>, 289 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 290 clock-names = "i2s", "sync_input"; 291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 293 assigned-clock-rates = <1536000>; 294 sound-name-prefix = "I2S4"; 295 status = "disabled"; 296 }; 297 298 tegra_i2s5: i2s@2901400 { 299 compatible = "nvidia,tegra194-i2s", 300 "nvidia,tegra210-i2s"; 301 reg = <0x0 0x2901400 0x0 0x100>; 302 clocks = <&bpmp TEGRA194_CLK_I2S5>, 303 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 304 clock-names = "i2s", "sync_input"; 305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 307 assigned-clock-rates = <1536000>; 308 sound-name-prefix = "I2S5"; 309 status = "disabled"; 310 }; 311 312 tegra_i2s6: i2s@2901500 { 313 compatible = "nvidia,tegra194-i2s", 314 "nvidia,tegra210-i2s"; 315 reg = <0x0 0x2901500 0x0 0x100>; 316 clocks = <&bpmp TEGRA194_CLK_I2S6>, 317 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 318 clock-names = "i2s", "sync_input"; 319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 321 assigned-clock-rates = <1536000>; 322 sound-name-prefix = "I2S6"; 323 status = "disabled"; 324 }; 325 326 tegra_sfc1: sfc@2902000 { 327 compatible = "nvidia,tegra194-sfc", 328 "nvidia,tegra210-sfc"; 329 reg = <0x0 0x2902000 0x0 0x200>; 330 sound-name-prefix = "SFC1"; 331 status = "disabled"; 332 }; 333 334 tegra_sfc2: sfc@2902200 { 335 compatible = "nvidia,tegra194-sfc", 336 "nvidia,tegra210-sfc"; 337 reg = <0x0 0x2902200 0x0 0x200>; 338 sound-name-prefix = "SFC2"; 339 status = "disabled"; 340 }; 341 342 tegra_sfc3: sfc@2902400 { 343 compatible = "nvidia,tegra194-sfc", 344 "nvidia,tegra210-sfc"; 345 reg = <0x0 0x2902400 0x0 0x200>; 346 sound-name-prefix = "SFC3"; 347 status = "disabled"; 348 }; 349 350 tegra_sfc4: sfc@2902600 { 351 compatible = "nvidia,tegra194-sfc", 352 "nvidia,tegra210-sfc"; 353 reg = <0x0 0x2902600 0x0 0x200>; 354 sound-name-prefix = "SFC4"; 355 status = "disabled"; 356 }; 357 358 tegra_amx1: amx@2903000 { 359 compatible = "nvidia,tegra194-amx"; 360 reg = <0x0 0x2903000 0x0 0x100>; 361 sound-name-prefix = "AMX1"; 362 status = "disabled"; 363 }; 364 365 tegra_amx2: amx@2903100 { 366 compatible = "nvidia,tegra194-amx"; 367 reg = <0x0 0x2903100 0x0 0x100>; 368 sound-name-prefix = "AMX2"; 369 status = "disabled"; 370 }; 371 372 tegra_amx3: amx@2903200 { 373 compatible = "nvidia,tegra194-amx"; 374 reg = <0x0 0x2903200 0x0 0x100>; 375 sound-name-prefix = "AMX3"; 376 status = "disabled"; 377 }; 378 379 tegra_amx4: amx@2903300 { 380 compatible = "nvidia,tegra194-amx"; 381 reg = <0x0 0x2903300 0x0 0x100>; 382 sound-name-prefix = "AMX4"; 383 status = "disabled"; 384 }; 385 386 tegra_adx1: adx@2903800 { 387 compatible = "nvidia,tegra194-adx", 388 "nvidia,tegra210-adx"; 389 reg = <0x0 0x2903800 0x0 0x100>; 390 sound-name-prefix = "ADX1"; 391 status = "disabled"; 392 }; 393 394 tegra_adx2: adx@2903900 { 395 compatible = "nvidia,tegra194-adx", 396 "nvidia,tegra210-adx"; 397 reg = <0x0 0x2903900 0x0 0x100>; 398 sound-name-prefix = "ADX2"; 399 status = "disabled"; 400 }; 401 402 tegra_adx3: adx@2903a00 { 403 compatible = "nvidia,tegra194-adx", 404 "nvidia,tegra210-adx"; 405 reg = <0x0 0x2903a00 0x0 0x100>; 406 sound-name-prefix = "ADX3"; 407 status = "disabled"; 408 }; 409 410 tegra_adx4: adx@2903b00 { 411 compatible = "nvidia,tegra194-adx", 412 "nvidia,tegra210-adx"; 413 reg = <0x0 0x2903b00 0x0 0x100>; 414 sound-name-prefix = "ADX4"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic1: dmic@2904000 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x0 0x2904000 0x0 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC1"; 428 status = "disabled"; 429 }; 430 431 tegra_dmic2: dmic@2904100 { 432 compatible = "nvidia,tegra194-dmic", 433 "nvidia,tegra210-dmic"; 434 reg = <0x0 0x2904100 0x0 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 436 clock-names = "dmic"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <3072000>; 440 sound-name-prefix = "DMIC2"; 441 status = "disabled"; 442 }; 443 444 tegra_dmic3: dmic@2904200 { 445 compatible = "nvidia,tegra194-dmic", 446 "nvidia,tegra210-dmic"; 447 reg = <0x0 0x2904200 0x0 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 449 clock-names = "dmic"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <3072000>; 453 sound-name-prefix = "DMIC3"; 454 status = "disabled"; 455 }; 456 457 tegra_dmic4: dmic@2904300 { 458 compatible = "nvidia,tegra194-dmic", 459 "nvidia,tegra210-dmic"; 460 reg = <0x0 0x2904300 0x0 0x100>; 461 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 462 clock-names = "dmic"; 463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 465 assigned-clock-rates = <3072000>; 466 sound-name-prefix = "DMIC4"; 467 status = "disabled"; 468 }; 469 470 tegra_dspk1: dspk@2905000 { 471 compatible = "nvidia,tegra194-dspk", 472 "nvidia,tegra186-dspk"; 473 reg = <0x0 0x2905000 0x0 0x100>; 474 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 475 clock-names = "dspk"; 476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 478 assigned-clock-rates = <12288000>; 479 sound-name-prefix = "DSPK1"; 480 status = "disabled"; 481 }; 482 483 tegra_dspk2: dspk@2905100 { 484 compatible = "nvidia,tegra194-dspk", 485 "nvidia,tegra186-dspk"; 486 reg = <0x0 0x2905100 0x0 0x100>; 487 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 488 clock-names = "dspk"; 489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 491 assigned-clock-rates = <12288000>; 492 sound-name-prefix = "DSPK2"; 493 status = "disabled"; 494 }; 495 496 tegra_ope1: processing-engine@2908000 { 497 compatible = "nvidia,tegra194-ope", 498 "nvidia,tegra210-ope"; 499 reg = <0x0 0x2908000 0x0 0x100>; 500 sound-name-prefix = "OPE1"; 501 status = "disabled"; 502 503 #address-cells = <2>; 504 #size-cells = <2>; 505 ranges; 506 507 equalizer@2908100 { 508 compatible = "nvidia,tegra194-peq", 509 "nvidia,tegra210-peq"; 510 reg = <0x0 0x2908100 0x0 0x100>; 511 }; 512 513 dynamic-range-compressor@2908200 { 514 compatible = "nvidia,tegra194-mbdrc", 515 "nvidia,tegra210-mbdrc"; 516 reg = <0x0 0x2908200 0x0 0x200>; 517 }; 518 }; 519 520 tegra_mvc1: mvc@290a000 { 521 compatible = "nvidia,tegra194-mvc", 522 "nvidia,tegra210-mvc"; 523 reg = <0x0 0x290a000 0x0 0x200>; 524 sound-name-prefix = "MVC1"; 525 status = "disabled"; 526 }; 527 528 tegra_mvc2: mvc@290a200 { 529 compatible = "nvidia,tegra194-mvc", 530 "nvidia,tegra210-mvc"; 531 reg = <0x0 0x290a200 0x0 0x200>; 532 sound-name-prefix = "MVC2"; 533 status = "disabled"; 534 }; 535 536 tegra_amixer: amixer@290bb00 { 537 compatible = "nvidia,tegra194-amixer", 538 "nvidia,tegra210-amixer"; 539 reg = <0x0 0x290bb00 0x0 0x800>; 540 sound-name-prefix = "MIXER1"; 541 status = "disabled"; 542 }; 543 544 tegra_admaif: admaif@290f000 { 545 compatible = "nvidia,tegra194-admaif", 546 "nvidia,tegra186-admaif"; 547 reg = <0x0 0x0290f000 0x0 0x1000>; 548 dmas = <&adma 1>, <&adma 1>, 549 <&adma 2>, <&adma 2>, 550 <&adma 3>, <&adma 3>, 551 <&adma 4>, <&adma 4>, 552 <&adma 5>, <&adma 5>, 553 <&adma 6>, <&adma 6>, 554 <&adma 7>, <&adma 7>, 555 <&adma 8>, <&adma 8>, 556 <&adma 9>, <&adma 9>, 557 <&adma 10>, <&adma 10>, 558 <&adma 11>, <&adma 11>, 559 <&adma 12>, <&adma 12>, 560 <&adma 13>, <&adma 13>, 561 <&adma 14>, <&adma 14>, 562 <&adma 15>, <&adma 15>, 563 <&adma 16>, <&adma 16>, 564 <&adma 17>, <&adma 17>, 565 <&adma 18>, <&adma 18>, 566 <&adma 19>, <&adma 19>, 567 <&adma 20>, <&adma 20>; 568 dma-names = "rx1", "tx1", 569 "rx2", "tx2", 570 "rx3", "tx3", 571 "rx4", "tx4", 572 "rx5", "tx5", 573 "rx6", "tx6", 574 "rx7", "tx7", 575 "rx8", "tx8", 576 "rx9", "tx9", 577 "rx10", "tx10", 578 "rx11", "tx11", 579 "rx12", "tx12", 580 "rx13", "tx13", 581 "rx14", "tx14", 582 "rx15", "tx15", 583 "rx16", "tx16", 584 "rx17", "tx17", 585 "rx18", "tx18", 586 "rx19", "tx19", 587 "rx20", "tx20"; 588 status = "disabled"; 589 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 590 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 591 interconnect-names = "dma-mem", "write"; 592 iommus = <&smmu TEGRA194_SID_APE>; 593 }; 594 595 tegra_asrc: asrc@2910000 { 596 compatible = "nvidia,tegra194-asrc", 597 "nvidia,tegra186-asrc"; 598 reg = <0x0 0x2910000 0x0 0x2000>; 599 sound-name-prefix = "ASRC1"; 600 status = "disabled"; 601 }; 602 }; 603 604 adma: dma-controller@2930000 { 605 compatible = "nvidia,tegra194-adma", 606 "nvidia,tegra186-adma"; 607 reg = <0x0 0x02930000 0x0 0x20000>; 608 interrupt-parent = <&agic>; 609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 641 #dma-cells = <1>; 642 clocks = <&bpmp TEGRA194_CLK_AHUB>; 643 clock-names = "d_audio"; 644 status = "disabled"; 645 }; 646 647 agic: interrupt-controller@2a40000 { 648 compatible = "nvidia,tegra194-agic", 649 "nvidia,tegra210-agic"; 650 #interrupt-cells = <3>; 651 interrupt-controller; 652 reg = <0x0 0x02a41000 0x0 0x1000>, 653 <0x0 0x02a42000 0x0 0x2000>; 654 interrupts = <GIC_SPI 145 655 (GIC_CPU_MASK_SIMPLE(4) | 656 IRQ_TYPE_LEVEL_HIGH)>; 657 clocks = <&bpmp TEGRA194_CLK_APE>; 658 clock-names = "clk"; 659 status = "disabled"; 660 }; 661 }; 662 663 mc: memory-controller@2c00000 { 664 compatible = "nvidia,tegra194-mc"; 665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 666 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 667 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 668 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 669 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 670 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 671 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 672 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 673 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 674 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 675 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 676 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 677 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 678 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 679 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 680 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 681 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 682 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 683 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 684 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 685 "ch11", "ch12", "ch13", "ch14", "ch15"; 686 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 687 #interconnect-cells = <1>; 688 status = "disabled"; 689 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 693 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 694 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 695 696 /* 697 * Bit 39 of addresses passing through the memory 698 * controller selects the XBAR format used when memory 699 * is accessed. This is used to transparently access 700 * memory in the XBAR format used by the discrete GPU 701 * (bit 39 set) or Tegra (bit 39 clear). 702 * 703 * As a consequence, the operating system must ensure 704 * that bit 39 is never used implicitly, for example 705 * via an I/O virtual address mapping of an IOMMU. If 706 * devices require access to the XBAR switch, their 707 * drivers must set this bit explicitly. 708 * 709 * Limit the DMA range for memory clients to [38:0]. 710 */ 711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 712 713 emc: external-memory-controller@2c60000 { 714 compatible = "nvidia,tegra194-emc"; 715 reg = <0x0 0x02c60000 0x0 0x90000>, 716 <0x0 0x01780000 0x0 0x80000>; 717 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA194_CLK_EMC>; 719 clock-names = "emc"; 720 721 #interconnect-cells = <0>; 722 723 nvidia,bpmp = <&bpmp>; 724 }; 725 }; 726 727 timer@3010000 { 728 compatible = "nvidia,tegra186-timer"; 729 reg = <0x0 0x03010000 0x0 0x000e0000>; 730 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 740 status = "okay"; 741 }; 742 743 uarta: serial@3100000 { 744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 745 reg = <0x0 0x03100000 0x0 0x40>; 746 reg-shift = <2>; 747 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&bpmp TEGRA194_CLK_UARTA>; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 dmas = <&gpcdma 8>, <&gpcdma 8>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 uartb: serial@3110000 { 756 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 757 reg = <0x0 0x03110000 0x0 0x40>; 758 reg-shift = <2>; 759 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&bpmp TEGRA194_CLK_UARTB>; 761 resets = <&bpmp TEGRA194_RESET_UARTB>; 762 dmas = <&gpcdma 9>, <&gpcdma 9>; 763 dma-names = "rx", "tx"; 764 status = "disabled"; 765 }; 766 767 uartd: serial@3130000 { 768 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 769 reg = <0x0 0x03130000 0x0 0x40>; 770 reg-shift = <2>; 771 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&bpmp TEGRA194_CLK_UARTD>; 773 resets = <&bpmp TEGRA194_RESET_UARTD>; 774 dmas = <&gpcdma 19>, <&gpcdma 19>; 775 dma-names = "rx", "tx"; 776 status = "disabled"; 777 }; 778 779 uarte: serial@3140000 { 780 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 781 reg = <0x0 0x03140000 0x0 0x40>; 782 reg-shift = <2>; 783 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&bpmp TEGRA194_CLK_UARTE>; 785 resets = <&bpmp TEGRA194_RESET_UARTE>; 786 dmas = <&gpcdma 20>, <&gpcdma 20>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 uartf: serial@3150000 { 792 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 793 reg = <0x0 0x03150000 0x0 0x40>; 794 reg-shift = <2>; 795 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&bpmp TEGRA194_CLK_UARTF>; 797 resets = <&bpmp TEGRA194_RESET_UARTF>; 798 dmas = <&gpcdma 12>, <&gpcdma 12>; 799 dma-names = "rx", "tx"; 800 status = "disabled"; 801 }; 802 803 gen1_i2c: i2c@3160000 { 804 compatible = "nvidia,tegra194-i2c"; 805 reg = <0x0 0x03160000 0x0 0x10000>; 806 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 clocks = <&bpmp TEGRA194_CLK_I2C1>; 810 clock-names = "div-clk"; 811 resets = <&bpmp TEGRA194_RESET_I2C1>; 812 reset-names = "i2c"; 813 dmas = <&gpcdma 21>, <&gpcdma 21>; 814 dma-names = "rx", "tx"; 815 status = "disabled"; 816 }; 817 818 uarth: serial@3170000 { 819 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 820 reg = <0x0 0x03170000 0x0 0x40>; 821 reg-shift = <2>; 822 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&bpmp TEGRA194_CLK_UARTH>; 824 resets = <&bpmp TEGRA194_RESET_UARTH>; 825 dmas = <&gpcdma 13>, <&gpcdma 13>; 826 dma-names = "rx", "tx"; 827 status = "disabled"; 828 }; 829 830 cam_i2c: i2c@3180000 { 831 compatible = "nvidia,tegra194-i2c"; 832 reg = <0x0 0x03180000 0x0 0x10000>; 833 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 clocks = <&bpmp TEGRA194_CLK_I2C3>; 837 clock-names = "div-clk"; 838 resets = <&bpmp TEGRA194_RESET_I2C3>; 839 reset-names = "i2c"; 840 dmas = <&gpcdma 23>, <&gpcdma 23>; 841 dma-names = "rx", "tx"; 842 status = "disabled"; 843 }; 844 845 /* shares pads with dpaux1 */ 846 dp_aux_ch1_i2c: i2c@3190000 { 847 compatible = "nvidia,tegra194-i2c"; 848 reg = <0x0 0x03190000 0x0 0x10000>; 849 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 clocks = <&bpmp TEGRA194_CLK_I2C4>; 853 clock-names = "div-clk"; 854 resets = <&bpmp TEGRA194_RESET_I2C4>; 855 reset-names = "i2c"; 856 pinctrl-0 = <&state_dpaux1_i2c>; 857 pinctrl-1 = <&state_dpaux1_off>; 858 pinctrl-names = "default", "idle"; 859 dmas = <&gpcdma 26>, <&gpcdma 26>; 860 dma-names = "rx", "tx"; 861 status = "disabled"; 862 }; 863 864 /* shares pads with dpaux0 */ 865 dp_aux_ch0_i2c: i2c@31b0000 { 866 compatible = "nvidia,tegra194-i2c"; 867 reg = <0x0 0x031b0000 0x0 0x10000>; 868 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 clocks = <&bpmp TEGRA194_CLK_I2C6>; 872 clock-names = "div-clk"; 873 resets = <&bpmp TEGRA194_RESET_I2C6>; 874 reset-names = "i2c"; 875 pinctrl-0 = <&state_dpaux0_i2c>; 876 pinctrl-1 = <&state_dpaux0_off>; 877 pinctrl-names = "default", "idle"; 878 dmas = <&gpcdma 30>, <&gpcdma 30>; 879 dma-names = "rx", "tx"; 880 status = "disabled"; 881 }; 882 883 /* shares pads with dpaux2 */ 884 dp_aux_ch2_i2c: i2c@31c0000 { 885 compatible = "nvidia,tegra194-i2c"; 886 reg = <0x0 0x031c0000 0x0 0x10000>; 887 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 clocks = <&bpmp TEGRA194_CLK_I2C7>; 891 clock-names = "div-clk"; 892 resets = <&bpmp TEGRA194_RESET_I2C7>; 893 reset-names = "i2c"; 894 pinctrl-0 = <&state_dpaux2_i2c>; 895 pinctrl-1 = <&state_dpaux2_off>; 896 pinctrl-names = "default", "idle"; 897 dmas = <&gpcdma 27>, <&gpcdma 27>; 898 dma-names = "rx", "tx"; 899 status = "disabled"; 900 }; 901 902 /* shares pads with dpaux3 */ 903 dp_aux_ch3_i2c: i2c@31e0000 { 904 compatible = "nvidia,tegra194-i2c"; 905 reg = <0x0 0x031e0000 0x0 0x10000>; 906 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 clocks = <&bpmp TEGRA194_CLK_I2C9>; 910 clock-names = "div-clk"; 911 resets = <&bpmp TEGRA194_RESET_I2C9>; 912 reset-names = "i2c"; 913 pinctrl-0 = <&state_dpaux3_i2c>; 914 pinctrl-1 = <&state_dpaux3_off>; 915 pinctrl-names = "default", "idle"; 916 dmas = <&gpcdma 31>, <&gpcdma 31>; 917 dma-names = "rx", "tx"; 918 status = "disabled"; 919 }; 920 921 spi@3270000 { 922 compatible = "nvidia,tegra194-qspi"; 923 reg = <0x0 0x3270000 0x0 0x1000>; 924 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 928 <&bpmp TEGRA194_CLK_QSPI0_PM>; 929 clock-names = "qspi", "qspi_out"; 930 resets = <&bpmp TEGRA194_RESET_QSPI0>; 931 status = "disabled"; 932 }; 933 934 pwm1: pwm@3280000 { 935 compatible = "nvidia,tegra194-pwm", 936 "nvidia,tegra186-pwm"; 937 reg = <0x0 0x3280000 0x0 0x10000>; 938 clocks = <&bpmp TEGRA194_CLK_PWM1>; 939 resets = <&bpmp TEGRA194_RESET_PWM1>; 940 reset-names = "pwm"; 941 status = "disabled"; 942 #pwm-cells = <2>; 943 }; 944 945 pwm2: pwm@3290000 { 946 compatible = "nvidia,tegra194-pwm", 947 "nvidia,tegra186-pwm"; 948 reg = <0x0 0x3290000 0x0 0x10000>; 949 clocks = <&bpmp TEGRA194_CLK_PWM2>; 950 resets = <&bpmp TEGRA194_RESET_PWM2>; 951 reset-names = "pwm"; 952 status = "disabled"; 953 #pwm-cells = <2>; 954 }; 955 956 pwm3: pwm@32a0000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x0 0x32a0000 0x0 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM3>; 961 resets = <&bpmp TEGRA194_RESET_PWM3>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm5: pwm@32c0000 { 968 compatible = "nvidia,tegra194-pwm", 969 "nvidia,tegra186-pwm"; 970 reg = <0x0 0x32c0000 0x0 0x10000>; 971 clocks = <&bpmp TEGRA194_CLK_PWM5>; 972 resets = <&bpmp TEGRA194_RESET_PWM5>; 973 reset-names = "pwm"; 974 status = "disabled"; 975 #pwm-cells = <2>; 976 }; 977 978 pwm6: pwm@32d0000 { 979 compatible = "nvidia,tegra194-pwm", 980 "nvidia,tegra186-pwm"; 981 reg = <0x0 0x32d0000 0x0 0x10000>; 982 clocks = <&bpmp TEGRA194_CLK_PWM6>; 983 resets = <&bpmp TEGRA194_RESET_PWM6>; 984 reset-names = "pwm"; 985 status = "disabled"; 986 #pwm-cells = <2>; 987 }; 988 989 pwm7: pwm@32e0000 { 990 compatible = "nvidia,tegra194-pwm", 991 "nvidia,tegra186-pwm"; 992 reg = <0x0 0x32e0000 0x0 0x10000>; 993 clocks = <&bpmp TEGRA194_CLK_PWM7>; 994 resets = <&bpmp TEGRA194_RESET_PWM7>; 995 reset-names = "pwm"; 996 status = "disabled"; 997 #pwm-cells = <2>; 998 }; 999 1000 pwm8: pwm@32f0000 { 1001 compatible = "nvidia,tegra194-pwm", 1002 "nvidia,tegra186-pwm"; 1003 reg = <0x0 0x32f0000 0x0 0x10000>; 1004 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1005 resets = <&bpmp TEGRA194_RESET_PWM8>; 1006 reset-names = "pwm"; 1007 status = "disabled"; 1008 #pwm-cells = <2>; 1009 }; 1010 1011 spi@3300000 { 1012 compatible = "nvidia,tegra194-qspi"; 1013 reg = <0x0 0x3300000 0x0 0x1000>; 1014 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1018 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1019 clock-names = "qspi", "qspi_out"; 1020 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1021 status = "disabled"; 1022 }; 1023 1024 sdmmc1: mmc@3400000 { 1025 compatible = "nvidia,tegra194-sdhci"; 1026 reg = <0x0 0x03400000 0x0 0x10000>; 1027 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1029 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1030 clock-names = "sdhci", "tmclk"; 1031 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1032 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1033 assigned-clock-parents = 1034 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1035 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1036 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1037 reset-names = "sdhci"; 1038 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1039 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1040 interconnect-names = "dma-mem", "write"; 1041 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1042 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1043 pinctrl-0 = <&sdmmc1_3v3>; 1044 pinctrl-1 = <&sdmmc1_1v8>; 1045 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1046 <0x07>; 1047 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1048 <0x07>; 1049 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1050 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1051 <0x07>; 1052 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1053 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1054 nvidia,default-tap = <0x9>; 1055 nvidia,default-trim = <0x5>; 1056 sd-uhs-sdr25; 1057 sd-uhs-sdr50; 1058 sd-uhs-ddr50; 1059 sd-uhs-sdr104; 1060 status = "disabled"; 1061 }; 1062 1063 sdmmc3: mmc@3440000 { 1064 compatible = "nvidia,tegra194-sdhci"; 1065 reg = <0x0 0x03440000 0x0 0x10000>; 1066 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1068 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1069 clock-names = "sdhci", "tmclk"; 1070 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1071 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1072 assigned-clock-parents = 1073 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1074 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1075 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1076 reset-names = "sdhci"; 1077 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1078 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1079 interconnect-names = "dma-mem", "write"; 1080 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1081 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1082 pinctrl-0 = <&sdmmc3_3v3>; 1083 pinctrl-1 = <&sdmmc3_1v8>; 1084 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1085 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1086 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1087 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1088 <0x07>; 1089 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1090 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1091 <0x07>; 1092 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1093 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1094 nvidia,default-tap = <0x9>; 1095 nvidia,default-trim = <0x5>; 1096 sd-uhs-sdr25; 1097 sd-uhs-sdr50; 1098 sd-uhs-ddr50; 1099 sd-uhs-sdr104; 1100 status = "disabled"; 1101 }; 1102 1103 sdmmc4: mmc@3460000 { 1104 compatible = "nvidia,tegra194-sdhci"; 1105 reg = <0x0 0x03460000 0x0 0x10000>; 1106 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1108 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1109 clock-names = "sdhci", "tmclk"; 1110 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1111 <&bpmp TEGRA194_CLK_PLLC4>; 1112 assigned-clock-parents = 1113 <&bpmp TEGRA194_CLK_PLLC4>; 1114 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1115 reset-names = "sdhci"; 1116 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1117 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1118 interconnect-names = "dma-mem", "write"; 1119 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1120 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1121 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1122 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1123 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1124 <0x0a>; 1125 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1126 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1127 <0x0a>; 1128 nvidia,default-tap = <0x8>; 1129 nvidia,default-trim = <0x14>; 1130 nvidia,dqs-trim = <40>; 1131 cap-mmc-highspeed; 1132 mmc-ddr-1_8v; 1133 mmc-hs200-1_8v; 1134 mmc-hs400-1_8v; 1135 mmc-hs400-enhanced-strobe; 1136 supports-cqe; 1137 status = "disabled"; 1138 }; 1139 1140 hda@3510000 { 1141 compatible = "nvidia,tegra194-hda"; 1142 reg = <0x0 0x3510000 0x0 0x10000>; 1143 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&bpmp TEGRA194_CLK_HDA>, 1145 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1146 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1147 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1148 resets = <&bpmp TEGRA194_RESET_HDA>, 1149 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1150 reset-names = "hda", "hda2hdmi"; 1151 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1152 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1153 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1154 interconnect-names = "dma-mem", "write"; 1155 iommus = <&smmu TEGRA194_SID_HDA>; 1156 status = "disabled"; 1157 }; 1158 1159 xusb_padctl: padctl@3520000 { 1160 compatible = "nvidia,tegra194-xusb-padctl"; 1161 reg = <0x0 0x03520000 0x0 0x1000>, 1162 <0x0 0x03540000 0x0 0x1000>; 1163 reg-names = "padctl", "ao"; 1164 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1165 1166 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1167 reset-names = "padctl"; 1168 1169 status = "disabled"; 1170 1171 pads { 1172 usb2 { 1173 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1174 clock-names = "trk"; 1175 1176 lanes { 1177 usb2-0 { 1178 nvidia,function = "xusb"; 1179 status = "disabled"; 1180 #phy-cells = <0>; 1181 }; 1182 1183 usb2-1 { 1184 nvidia,function = "xusb"; 1185 status = "disabled"; 1186 #phy-cells = <0>; 1187 }; 1188 1189 usb2-2 { 1190 nvidia,function = "xusb"; 1191 status = "disabled"; 1192 #phy-cells = <0>; 1193 }; 1194 1195 usb2-3 { 1196 nvidia,function = "xusb"; 1197 status = "disabled"; 1198 #phy-cells = <0>; 1199 }; 1200 }; 1201 }; 1202 1203 usb3 { 1204 lanes { 1205 usb3-0 { 1206 nvidia,function = "xusb"; 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 1211 usb3-1 { 1212 nvidia,function = "xusb"; 1213 status = "disabled"; 1214 #phy-cells = <0>; 1215 }; 1216 1217 usb3-2 { 1218 nvidia,function = "xusb"; 1219 status = "disabled"; 1220 #phy-cells = <0>; 1221 }; 1222 1223 usb3-3 { 1224 nvidia,function = "xusb"; 1225 status = "disabled"; 1226 #phy-cells = <0>; 1227 }; 1228 }; 1229 }; 1230 }; 1231 1232 ports { 1233 usb2-0 { 1234 status = "disabled"; 1235 }; 1236 1237 usb2-1 { 1238 status = "disabled"; 1239 }; 1240 1241 usb2-2 { 1242 status = "disabled"; 1243 }; 1244 1245 usb2-3 { 1246 status = "disabled"; 1247 }; 1248 1249 usb3-0 { 1250 status = "disabled"; 1251 }; 1252 1253 usb3-1 { 1254 status = "disabled"; 1255 }; 1256 1257 usb3-2 { 1258 status = "disabled"; 1259 }; 1260 1261 usb3-3 { 1262 status = "disabled"; 1263 }; 1264 }; 1265 }; 1266 1267 usb@3550000 { 1268 compatible = "nvidia,tegra194-xudc"; 1269 reg = <0x0 0x03550000 0x0 0x8000>, 1270 <0x0 0x03558000 0x0 0x1000>; 1271 reg-names = "base", "fpci"; 1272 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1274 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1275 <&bpmp TEGRA194_CLK_XUSB_SS>, 1276 <&bpmp TEGRA194_CLK_XUSB_FS>; 1277 clock-names = "dev", "ss", "ss_src", "fs_src"; 1278 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1279 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1280 interconnect-names = "dma-mem", "write"; 1281 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1282 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1283 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1284 power-domain-names = "dev", "ss"; 1285 nvidia,xusb-padctl = <&xusb_padctl>; 1286 dma-coherent; 1287 status = "disabled"; 1288 }; 1289 1290 usb@3610000 { 1291 compatible = "nvidia,tegra194-xusb"; 1292 reg = <0x0 0x03610000 0x0 0x40000>, 1293 <0x0 0x03600000 0x0 0x10000>; 1294 reg-names = "hcd", "fpci"; 1295 1296 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1298 1299 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1300 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1301 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1302 <&bpmp TEGRA194_CLK_XUSB_SS>, 1303 <&bpmp TEGRA194_CLK_CLK_M>, 1304 <&bpmp TEGRA194_CLK_XUSB_FS>, 1305 <&bpmp TEGRA194_CLK_UTMIPLL>, 1306 <&bpmp TEGRA194_CLK_CLK_M>, 1307 <&bpmp TEGRA194_CLK_PLLE>; 1308 clock-names = "xusb_host", "xusb_falcon_src", 1309 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1310 "xusb_fs_src", "pll_u_480m", "clk_m", 1311 "pll_e"; 1312 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1313 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1314 interconnect-names = "dma-mem", "write"; 1315 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1316 1317 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1318 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1319 power-domain-names = "xusb_host", "xusb_ss"; 1320 1321 nvidia,xusb-padctl = <&xusb_padctl>; 1322 status = "disabled"; 1323 }; 1324 1325 fuse@3820000 { 1326 compatible = "nvidia,tegra194-efuse"; 1327 reg = <0x0 0x03820000 0x0 0x10000>; 1328 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1329 clock-names = "fuse"; 1330 }; 1331 1332 gic: interrupt-controller@3881000 { 1333 compatible = "arm,gic-400"; 1334 #address-cells = <0>; 1335 #interrupt-cells = <3>; 1336 interrupt-controller; 1337 reg = <0x0 0x03881000 0x0 0x1000>, 1338 <0x0 0x03882000 0x0 0x2000>, 1339 <0x0 0x03884000 0x0 0x2000>, 1340 <0x0 0x03886000 0x0 0x2000>; 1341 interrupts = <GIC_PPI 9 1342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1343 interrupt-parent = <&gic>; 1344 }; 1345 1346 cec@3960000 { 1347 compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec"; 1348 reg = <0x0 0x03960000 0x0 0x10000>; 1349 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&bpmp TEGRA194_CLK_CEC>; 1351 clock-names = "cec"; 1352 status = "disabled"; 1353 }; 1354 1355 hte_lic: hardware-timestamp@3aa0000 { 1356 compatible = "nvidia,tegra194-gte-lic"; 1357 reg = <0x0 0x3aa0000 0x0 0x10000>; 1358 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1359 nvidia,int-threshold = <1>; 1360 nvidia,slices = <11>; 1361 #timestamp-cells = <1>; 1362 status = "okay"; 1363 }; 1364 1365 hsp_top0: hsp@3c00000 { 1366 compatible = "nvidia,tegra194-hsp"; 1367 reg = <0x0 0x03c00000 0x0 0xa0000>; 1368 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1377 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1378 "shared3", "shared4", "shared5", "shared6", 1379 "shared7"; 1380 #mbox-cells = <2>; 1381 }; 1382 1383 p2u_hsio_0: phy@3e10000 { 1384 compatible = "nvidia,tegra194-p2u"; 1385 reg = <0x0 0x03e10000 0x0 0x10000>; 1386 reg-names = "ctl"; 1387 1388 #phy-cells = <0>; 1389 }; 1390 1391 p2u_hsio_1: phy@3e20000 { 1392 compatible = "nvidia,tegra194-p2u"; 1393 reg = <0x0 0x03e20000 0x0 0x10000>; 1394 reg-names = "ctl"; 1395 1396 #phy-cells = <0>; 1397 }; 1398 1399 p2u_hsio_2: phy@3e30000 { 1400 compatible = "nvidia,tegra194-p2u"; 1401 reg = <0x0 0x03e30000 0x0 0x10000>; 1402 reg-names = "ctl"; 1403 1404 #phy-cells = <0>; 1405 }; 1406 1407 p2u_hsio_3: phy@3e40000 { 1408 compatible = "nvidia,tegra194-p2u"; 1409 reg = <0x0 0x03e40000 0x0 0x10000>; 1410 reg-names = "ctl"; 1411 1412 #phy-cells = <0>; 1413 }; 1414 1415 p2u_hsio_4: phy@3e50000 { 1416 compatible = "nvidia,tegra194-p2u"; 1417 reg = <0x0 0x03e50000 0x0 0x10000>; 1418 reg-names = "ctl"; 1419 1420 #phy-cells = <0>; 1421 }; 1422 1423 p2u_hsio_5: phy@3e60000 { 1424 compatible = "nvidia,tegra194-p2u"; 1425 reg = <0x0 0x03e60000 0x0 0x10000>; 1426 reg-names = "ctl"; 1427 1428 #phy-cells = <0>; 1429 }; 1430 1431 p2u_hsio_6: phy@3e70000 { 1432 compatible = "nvidia,tegra194-p2u"; 1433 reg = <0x0 0x03e70000 0x0 0x10000>; 1434 reg-names = "ctl"; 1435 1436 #phy-cells = <0>; 1437 }; 1438 1439 p2u_hsio_7: phy@3e80000 { 1440 compatible = "nvidia,tegra194-p2u"; 1441 reg = <0x0 0x03e80000 0x0 0x10000>; 1442 reg-names = "ctl"; 1443 1444 #phy-cells = <0>; 1445 }; 1446 1447 p2u_hsio_8: phy@3e90000 { 1448 compatible = "nvidia,tegra194-p2u"; 1449 reg = <0x0 0x03e90000 0x0 0x10000>; 1450 reg-names = "ctl"; 1451 1452 #phy-cells = <0>; 1453 }; 1454 1455 p2u_hsio_9: phy@3ea0000 { 1456 compatible = "nvidia,tegra194-p2u"; 1457 reg = <0x0 0x03ea0000 0x0 0x10000>; 1458 reg-names = "ctl"; 1459 1460 #phy-cells = <0>; 1461 }; 1462 1463 p2u_nvhs_0: phy@3eb0000 { 1464 compatible = "nvidia,tegra194-p2u"; 1465 reg = <0x0 0x03eb0000 0x0 0x10000>; 1466 reg-names = "ctl"; 1467 1468 #phy-cells = <0>; 1469 }; 1470 1471 p2u_nvhs_1: phy@3ec0000 { 1472 compatible = "nvidia,tegra194-p2u"; 1473 reg = <0x0 0x03ec0000 0x0 0x10000>; 1474 reg-names = "ctl"; 1475 1476 #phy-cells = <0>; 1477 }; 1478 1479 p2u_nvhs_2: phy@3ed0000 { 1480 compatible = "nvidia,tegra194-p2u"; 1481 reg = <0x0 0x03ed0000 0x0 0x10000>; 1482 reg-names = "ctl"; 1483 1484 #phy-cells = <0>; 1485 }; 1486 1487 p2u_nvhs_3: phy@3ee0000 { 1488 compatible = "nvidia,tegra194-p2u"; 1489 reg = <0x0 0x03ee0000 0x0 0x10000>; 1490 reg-names = "ctl"; 1491 1492 #phy-cells = <0>; 1493 }; 1494 1495 p2u_nvhs_4: phy@3ef0000 { 1496 compatible = "nvidia,tegra194-p2u"; 1497 reg = <0x0 0x03ef0000 0x0 0x10000>; 1498 reg-names = "ctl"; 1499 1500 #phy-cells = <0>; 1501 }; 1502 1503 p2u_nvhs_5: phy@3f00000 { 1504 compatible = "nvidia,tegra194-p2u"; 1505 reg = <0x0 0x03f00000 0x0 0x10000>; 1506 reg-names = "ctl"; 1507 1508 #phy-cells = <0>; 1509 }; 1510 1511 p2u_nvhs_6: phy@3f10000 { 1512 compatible = "nvidia,tegra194-p2u"; 1513 reg = <0x0 0x03f10000 0x0 0x10000>; 1514 reg-names = "ctl"; 1515 1516 #phy-cells = <0>; 1517 }; 1518 1519 p2u_nvhs_7: phy@3f20000 { 1520 compatible = "nvidia,tegra194-p2u"; 1521 reg = <0x0 0x03f20000 0x0 0x10000>; 1522 reg-names = "ctl"; 1523 1524 #phy-cells = <0>; 1525 }; 1526 1527 p2u_hsio_10: phy@3f30000 { 1528 compatible = "nvidia,tegra194-p2u"; 1529 reg = <0x0 0x03f30000 0x0 0x10000>; 1530 reg-names = "ctl"; 1531 1532 #phy-cells = <0>; 1533 }; 1534 1535 p2u_hsio_11: phy@3f40000 { 1536 compatible = "nvidia,tegra194-p2u"; 1537 reg = <0x0 0x03f40000 0x0 0x10000>; 1538 reg-names = "ctl"; 1539 1540 #phy-cells = <0>; 1541 }; 1542 1543 sce-noc@b600000 { 1544 compatible = "nvidia,tegra194-sce-noc"; 1545 reg = <0x0 0xb600000 0x0 0x1000>; 1546 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1548 nvidia,axi2apb = <&axi2apb>; 1549 nvidia,apbmisc = <&apbmisc>; 1550 status = "okay"; 1551 }; 1552 1553 rce-noc@be00000 { 1554 compatible = "nvidia,tegra194-rce-noc"; 1555 reg = <0x0 0xbe00000 0x0 0x1000>; 1556 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1558 nvidia,axi2apb = <&axi2apb>; 1559 nvidia,apbmisc = <&apbmisc>; 1560 status = "okay"; 1561 }; 1562 1563 hsp_aon: hsp@c150000 { 1564 compatible = "nvidia,tegra194-hsp"; 1565 reg = <0x0 0x0c150000 0x0 0x90000>; 1566 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1570 /* 1571 * Shared interrupt 0 is routed only to AON/SPE, so 1572 * we only have 4 shared interrupts for the CCPLEX. 1573 */ 1574 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1575 #mbox-cells = <2>; 1576 }; 1577 1578 hte_aon: hardware-timestamp@c1e0000 { 1579 compatible = "nvidia,tegra194-gte-aon"; 1580 reg = <0x0 0xc1e0000 0x0 0x10000>; 1581 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1582 nvidia,int-threshold = <1>; 1583 nvidia,slices = <3>; 1584 #timestamp-cells = <1>; 1585 status = "okay"; 1586 }; 1587 1588 gen2_i2c: i2c@c240000 { 1589 compatible = "nvidia,tegra194-i2c"; 1590 reg = <0x0 0x0c240000 0x0 0x10000>; 1591 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1595 clock-names = "div-clk"; 1596 resets = <&bpmp TEGRA194_RESET_I2C2>; 1597 reset-names = "i2c"; 1598 dmas = <&gpcdma 22>, <&gpcdma 22>; 1599 dma-names = "rx", "tx"; 1600 status = "disabled"; 1601 }; 1602 1603 gen8_i2c: i2c@c250000 { 1604 compatible = "nvidia,tegra194-i2c"; 1605 reg = <0x0 0x0c250000 0x0 0x10000>; 1606 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1610 clock-names = "div-clk"; 1611 resets = <&bpmp TEGRA194_RESET_I2C8>; 1612 reset-names = "i2c"; 1613 dmas = <&gpcdma 0>, <&gpcdma 0>; 1614 dma-names = "rx", "tx"; 1615 status = "disabled"; 1616 }; 1617 1618 uartc: serial@c280000 { 1619 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1620 reg = <0x0 0x0c280000 0x0 0x40>; 1621 reg-shift = <2>; 1622 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1624 resets = <&bpmp TEGRA194_RESET_UARTC>; 1625 dmas = <&gpcdma 3>, <&gpcdma 3>; 1626 dma-names = "rx", "tx"; 1627 status = "disabled"; 1628 }; 1629 1630 uartg: serial@c290000 { 1631 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1632 reg = <0x0 0x0c290000 0x0 0x40>; 1633 reg-shift = <2>; 1634 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1636 resets = <&bpmp TEGRA194_RESET_UARTG>; 1637 dmas = <&gpcdma 2>, <&gpcdma 2>; 1638 dma-names = "rx", "tx"; 1639 status = "disabled"; 1640 }; 1641 1642 rtc: rtc@c2a0000 { 1643 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1644 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1645 interrupt-parent = <&pmc>; 1646 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1648 clock-names = "rtc"; 1649 status = "disabled"; 1650 }; 1651 1652 gpio_aon: gpio@c2f0000 { 1653 compatible = "nvidia,tegra194-gpio-aon"; 1654 reg-names = "security", "gpio"; 1655 reg = <0x0 0xc2f0000 0x0 0x1000>, 1656 <0x0 0xc2f1000 0x0 0x1000>; 1657 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1661 gpio-controller; 1662 #gpio-cells = <2>; 1663 interrupt-controller; 1664 #interrupt-cells = <2>; 1665 gpio-ranges = <&pinmux_aon 0 0 30>; 1666 }; 1667 1668 pinmux_aon: pinmux@c300000 { 1669 compatible = "nvidia,tegra194-pinmux-aon"; 1670 reg = <0x0 0xc300000 0x0 0x4000>; 1671 1672 status = "okay"; 1673 }; 1674 1675 pwm4: pwm@c340000 { 1676 compatible = "nvidia,tegra194-pwm", 1677 "nvidia,tegra186-pwm"; 1678 reg = <0x0 0xc340000 0x0 0x10000>; 1679 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1680 resets = <&bpmp TEGRA194_RESET_PWM4>; 1681 reset-names = "pwm"; 1682 status = "disabled"; 1683 #pwm-cells = <2>; 1684 }; 1685 1686 pmc: pmc@c360000 { 1687 compatible = "nvidia,tegra194-pmc"; 1688 reg = <0x0 0x0c360000 0x0 0x10000>, 1689 <0x0 0x0c370000 0x0 0x10000>, 1690 <0x0 0x0c380000 0x0 0x10000>, 1691 <0x0 0x0c390000 0x0 0x10000>, 1692 <0x0 0x0c3a0000 0x0 0x10000>; 1693 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1694 1695 #interrupt-cells = <2>; 1696 interrupt-controller; 1697 1698 sdmmc1_1v8: sdmmc1-1v8 { 1699 pins = "sdmmc1-hv"; 1700 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1701 }; 1702 1703 sdmmc1_3v3: sdmmc1-3v3 { 1704 pins = "sdmmc1-hv"; 1705 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1706 }; 1707 1708 sdmmc3_1v8: sdmmc3-1v8 { 1709 pins = "sdmmc3-hv"; 1710 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1711 }; 1712 1713 sdmmc3_3v3: sdmmc3-3v3 { 1714 pins = "sdmmc3-hv"; 1715 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1716 }; 1717 }; 1718 1719 aon-noc@c600000 { 1720 compatible = "nvidia,tegra194-aon-noc"; 1721 reg = <0x0 0xc600000 0x0 0x1000>; 1722 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1724 nvidia,apbmisc = <&apbmisc>; 1725 status = "okay"; 1726 }; 1727 1728 bpmp-noc@d600000 { 1729 compatible = "nvidia,tegra194-bpmp-noc"; 1730 reg = <0x0 0xd600000 0x0 0x1000>; 1731 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1733 nvidia,axi2apb = <&axi2apb>; 1734 nvidia,apbmisc = <&apbmisc>; 1735 status = "okay"; 1736 }; 1737 1738 iommu@10000000 { 1739 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1740 reg = <0x0 0x10000000 0x0 0x800000>; 1741 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1806 stream-match-mask = <0x7f80>; 1807 #global-interrupts = <1>; 1808 #iommu-cells = <1>; 1809 1810 nvidia,memory-controller = <&mc>; 1811 status = "disabled"; 1812 }; 1813 1814 smmu: iommu@12000000 { 1815 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1816 reg = <0x0 0x12000000 0x0 0x800000>, 1817 <0x0 0x11000000 0x0 0x800000>; 1818 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1884 stream-match-mask = <0x7f80>; 1885 #global-interrupts = <2>; 1886 #iommu-cells = <1>; 1887 1888 nvidia,memory-controller = <&mc>; 1889 status = "okay"; 1890 }; 1891 1892 host1x@13e00000 { 1893 compatible = "nvidia,tegra194-host1x"; 1894 reg = <0x0 0x13e00000 0x0 0x10000>, 1895 <0x0 0x13e10000 0x0 0x10000>; 1896 reg-names = "hypervisor", "vm"; 1897 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1899 interrupt-names = "syncpt", "host1x"; 1900 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1901 clock-names = "host1x"; 1902 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1903 reset-names = "host1x"; 1904 1905 #address-cells = <2>; 1906 #size-cells = <2>; 1907 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1908 1909 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1910 interconnect-names = "dma-mem"; 1911 iommus = <&smmu TEGRA194_SID_HOST1X>; 1912 dma-coherent; 1913 1914 /* Context isolation domains */ 1915 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1916 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1917 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1918 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1919 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1920 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1921 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1922 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1923 1924 nvdec@15140000 { 1925 compatible = "nvidia,tegra194-nvdec"; 1926 reg = <0x0 0x15140000 0x0 0x00040000>; 1927 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1928 clock-names = "nvdec"; 1929 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1930 reset-names = "nvdec"; 1931 1932 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1933 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1934 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1935 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1936 interconnect-names = "dma-mem", "read-1", "write"; 1937 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1938 dma-coherent; 1939 1940 nvidia,host1x-class = <0xf5>; 1941 }; 1942 1943 display-hub@15200000 { 1944 compatible = "nvidia,tegra194-display"; 1945 reg = <0x0 0x15200000 0x0 0x00040000>; 1946 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1947 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1948 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1949 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1950 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1951 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1952 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1953 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1954 "wgrp3", "wgrp4", "wgrp5"; 1955 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1956 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1957 clock-names = "disp", "hub"; 1958 status = "disabled"; 1959 1960 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1961 1962 #address-cells = <2>; 1963 #size-cells = <2>; 1964 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1965 1966 display@15200000 { 1967 compatible = "nvidia,tegra194-dc"; 1968 reg = <0x0 0x15200000 0x0 0x10000>; 1969 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1971 clock-names = "dc"; 1972 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1973 reset-names = "dc"; 1974 1975 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1976 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1977 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1978 interconnect-names = "dma-mem", "read-1"; 1979 1980 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1981 nvidia,head = <0>; 1982 }; 1983 1984 display@15210000 { 1985 compatible = "nvidia,tegra194-dc"; 1986 reg = <0x0 0x15210000 0x0 0x10000>; 1987 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1989 clock-names = "dc"; 1990 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1991 reset-names = "dc"; 1992 1993 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1994 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1995 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1996 interconnect-names = "dma-mem", "read-1"; 1997 1998 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1999 nvidia,head = <1>; 2000 }; 2001 2002 display@15220000 { 2003 compatible = "nvidia,tegra194-dc"; 2004 reg = <0x0 0x15220000 0x0 0x10000>; 2005 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2006 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2007 clock-names = "dc"; 2008 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2009 reset-names = "dc"; 2010 2011 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2012 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2013 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2014 interconnect-names = "dma-mem", "read-1"; 2015 2016 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2017 nvidia,head = <2>; 2018 }; 2019 2020 display@15230000 { 2021 compatible = "nvidia,tegra194-dc"; 2022 reg = <0x0 0x15230000 0x0 0x10000>; 2023 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2024 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2025 clock-names = "dc"; 2026 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2027 reset-names = "dc"; 2028 2029 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2030 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2031 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2032 interconnect-names = "dma-mem", "read-1"; 2033 2034 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2035 nvidia,head = <3>; 2036 }; 2037 }; 2038 2039 vic@15340000 { 2040 compatible = "nvidia,tegra194-vic"; 2041 reg = <0x0 0x15340000 0x0 0x00040000>; 2042 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2043 clocks = <&bpmp TEGRA194_CLK_VIC>; 2044 clock-names = "vic"; 2045 resets = <&bpmp TEGRA194_RESET_VIC>; 2046 reset-names = "vic"; 2047 2048 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2049 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2050 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2051 interconnect-names = "dma-mem", "write"; 2052 iommus = <&smmu TEGRA194_SID_VIC>; 2053 dma-coherent; 2054 }; 2055 2056 nvjpg@15380000 { 2057 compatible = "nvidia,tegra194-nvjpg"; 2058 reg = <0x0 0x15380000 0x0 0x40000>; 2059 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2060 clock-names = "nvjpg"; 2061 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2062 reset-names = "nvjpg"; 2063 2064 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2065 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2066 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2067 interconnect-names = "dma-mem", "write"; 2068 iommus = <&smmu TEGRA194_SID_NVJPG>; 2069 dma-coherent; 2070 }; 2071 2072 nvdec@15480000 { 2073 compatible = "nvidia,tegra194-nvdec"; 2074 reg = <0x0 0x15480000 0x0 0x00040000>; 2075 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2076 clock-names = "nvdec"; 2077 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2078 reset-names = "nvdec"; 2079 2080 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2081 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2082 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2083 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2084 interconnect-names = "dma-mem", "read-1", "write"; 2085 iommus = <&smmu TEGRA194_SID_NVDEC>; 2086 dma-coherent; 2087 2088 nvidia,host1x-class = <0xf0>; 2089 }; 2090 2091 nvenc@154c0000 { 2092 compatible = "nvidia,tegra194-nvenc"; 2093 reg = <0x0 0x154c0000 0x0 0x40000>; 2094 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2095 clock-names = "nvenc"; 2096 resets = <&bpmp TEGRA194_RESET_NVENC>; 2097 reset-names = "nvenc"; 2098 2099 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2100 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2101 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2102 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2103 interconnect-names = "dma-mem", "read-1", "write"; 2104 iommus = <&smmu TEGRA194_SID_NVENC>; 2105 dma-coherent; 2106 2107 nvidia,host1x-class = <0x21>; 2108 }; 2109 2110 dpaux0: dpaux@155c0000 { 2111 compatible = "nvidia,tegra194-dpaux"; 2112 reg = <0x0 0x155c0000 0x0 0x10000>; 2113 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2114 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2115 <&bpmp TEGRA194_CLK_PLLDP>; 2116 clock-names = "dpaux", "parent"; 2117 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2118 reset-names = "dpaux"; 2119 status = "disabled"; 2120 2121 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2122 2123 state_dpaux0_aux: pinmux-aux { 2124 groups = "dpaux-io"; 2125 function = "aux"; 2126 }; 2127 2128 state_dpaux0_i2c: pinmux-i2c { 2129 groups = "dpaux-io"; 2130 function = "i2c"; 2131 }; 2132 2133 state_dpaux0_off: pinmux-off { 2134 groups = "dpaux-io"; 2135 function = "off"; 2136 }; 2137 2138 i2c-bus { 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 }; 2142 }; 2143 2144 dpaux1: dpaux@155d0000 { 2145 compatible = "nvidia,tegra194-dpaux"; 2146 reg = <0x0 0x155d0000 0x0 0x10000>; 2147 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2148 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2149 <&bpmp TEGRA194_CLK_PLLDP>; 2150 clock-names = "dpaux", "parent"; 2151 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2152 reset-names = "dpaux"; 2153 status = "disabled"; 2154 2155 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2156 2157 state_dpaux1_aux: pinmux-aux { 2158 groups = "dpaux-io"; 2159 function = "aux"; 2160 }; 2161 2162 state_dpaux1_i2c: pinmux-i2c { 2163 groups = "dpaux-io"; 2164 function = "i2c"; 2165 }; 2166 2167 state_dpaux1_off: pinmux-off { 2168 groups = "dpaux-io"; 2169 function = "off"; 2170 }; 2171 2172 i2c-bus { 2173 #address-cells = <1>; 2174 #size-cells = <0>; 2175 }; 2176 }; 2177 2178 dpaux2: dpaux@155e0000 { 2179 compatible = "nvidia,tegra194-dpaux"; 2180 reg = <0x0 0x155e0000 0x0 0x10000>; 2181 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2182 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2183 <&bpmp TEGRA194_CLK_PLLDP>; 2184 clock-names = "dpaux", "parent"; 2185 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2186 reset-names = "dpaux"; 2187 status = "disabled"; 2188 2189 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2190 2191 state_dpaux2_aux: pinmux-aux { 2192 groups = "dpaux-io"; 2193 function = "aux"; 2194 }; 2195 2196 state_dpaux2_i2c: pinmux-i2c { 2197 groups = "dpaux-io"; 2198 function = "i2c"; 2199 }; 2200 2201 state_dpaux2_off: pinmux-off { 2202 groups = "dpaux-io"; 2203 function = "off"; 2204 }; 2205 2206 i2c-bus { 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 }; 2210 }; 2211 2212 dpaux3: dpaux@155f0000 { 2213 compatible = "nvidia,tegra194-dpaux"; 2214 reg = <0x0 0x155f0000 0x0 0x10000>; 2215 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2217 <&bpmp TEGRA194_CLK_PLLDP>; 2218 clock-names = "dpaux", "parent"; 2219 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2220 reset-names = "dpaux"; 2221 status = "disabled"; 2222 2223 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2224 2225 state_dpaux3_aux: pinmux-aux { 2226 groups = "dpaux-io"; 2227 function = "aux"; 2228 }; 2229 2230 state_dpaux3_i2c: pinmux-i2c { 2231 groups = "dpaux-io"; 2232 function = "i2c"; 2233 }; 2234 2235 state_dpaux3_off: pinmux-off { 2236 groups = "dpaux-io"; 2237 function = "off"; 2238 }; 2239 2240 i2c-bus { 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 }; 2244 }; 2245 2246 nvenc@15a80000 { 2247 compatible = "nvidia,tegra194-nvenc"; 2248 reg = <0x0 0x15a80000 0x0 0x00040000>; 2249 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2250 clock-names = "nvenc"; 2251 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2252 reset-names = "nvenc"; 2253 2254 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2255 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2256 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2257 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2258 interconnect-names = "dma-mem", "read-1", "write"; 2259 iommus = <&smmu TEGRA194_SID_NVENC1>; 2260 dma-coherent; 2261 2262 nvidia,host1x-class = <0x22>; 2263 }; 2264 2265 sor0: sor@15b00000 { 2266 compatible = "nvidia,tegra194-sor"; 2267 reg = <0x0 0x15b00000 0x0 0x40000>; 2268 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2270 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2271 <&bpmp TEGRA194_CLK_PLLD>, 2272 <&bpmp TEGRA194_CLK_PLLDP>, 2273 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2274 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2275 clock-names = "sor", "out", "parent", "dp", "safe", 2276 "pad"; 2277 resets = <&bpmp TEGRA194_RESET_SOR0>; 2278 reset-names = "sor"; 2279 pinctrl-0 = <&state_dpaux0_aux>; 2280 pinctrl-1 = <&state_dpaux0_i2c>; 2281 pinctrl-2 = <&state_dpaux0_off>; 2282 pinctrl-names = "aux", "i2c", "off"; 2283 status = "disabled"; 2284 2285 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2286 nvidia,interface = <0>; 2287 }; 2288 2289 sor1: sor@15b40000 { 2290 compatible = "nvidia,tegra194-sor"; 2291 reg = <0x0 0x15b40000 0x0 0x40000>; 2292 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2293 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2294 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2295 <&bpmp TEGRA194_CLK_PLLD2>, 2296 <&bpmp TEGRA194_CLK_PLLDP>, 2297 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2298 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2299 clock-names = "sor", "out", "parent", "dp", "safe", 2300 "pad"; 2301 resets = <&bpmp TEGRA194_RESET_SOR1>; 2302 reset-names = "sor"; 2303 pinctrl-0 = <&state_dpaux1_aux>; 2304 pinctrl-1 = <&state_dpaux1_i2c>; 2305 pinctrl-2 = <&state_dpaux1_off>; 2306 pinctrl-names = "aux", "i2c", "off"; 2307 status = "disabled"; 2308 2309 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2310 nvidia,interface = <1>; 2311 }; 2312 2313 sor2: sor@15b80000 { 2314 compatible = "nvidia,tegra194-sor"; 2315 reg = <0x0 0x15b80000 0x0 0x40000>; 2316 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2318 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2319 <&bpmp TEGRA194_CLK_PLLD3>, 2320 <&bpmp TEGRA194_CLK_PLLDP>, 2321 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2322 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2323 clock-names = "sor", "out", "parent", "dp", "safe", 2324 "pad"; 2325 resets = <&bpmp TEGRA194_RESET_SOR2>; 2326 reset-names = "sor"; 2327 pinctrl-0 = <&state_dpaux2_aux>; 2328 pinctrl-1 = <&state_dpaux2_i2c>; 2329 pinctrl-2 = <&state_dpaux2_off>; 2330 pinctrl-names = "aux", "i2c", "off"; 2331 status = "disabled"; 2332 2333 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2334 nvidia,interface = <2>; 2335 }; 2336 2337 sor3: sor@15bc0000 { 2338 compatible = "nvidia,tegra194-sor"; 2339 reg = <0x0 0x15bc0000 0x0 0x40000>; 2340 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2342 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2343 <&bpmp TEGRA194_CLK_PLLD4>, 2344 <&bpmp TEGRA194_CLK_PLLDP>, 2345 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2346 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2347 clock-names = "sor", "out", "parent", "dp", "safe", 2348 "pad"; 2349 resets = <&bpmp TEGRA194_RESET_SOR3>; 2350 reset-names = "sor"; 2351 pinctrl-0 = <&state_dpaux3_aux>; 2352 pinctrl-1 = <&state_dpaux3_i2c>; 2353 pinctrl-2 = <&state_dpaux3_off>; 2354 pinctrl-names = "aux", "i2c", "off"; 2355 status = "disabled"; 2356 2357 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2358 nvidia,interface = <3>; 2359 }; 2360 }; 2361 2362 pcie@14100000 { 2363 compatible = "nvidia,tegra194-pcie"; 2364 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2365 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2366 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2367 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2368 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2369 reg-names = "appl", "config", "atu_dma", "dbi"; 2370 2371 status = "disabled"; 2372 2373 #address-cells = <3>; 2374 #size-cells = <2>; 2375 device_type = "pci"; 2376 num-lanes = <1>; 2377 linux,pci-domain = <1>; 2378 2379 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2380 clock-names = "core"; 2381 2382 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2383 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2384 reset-names = "apb", "core"; 2385 2386 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2387 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2388 interrupt-names = "intr", "msi"; 2389 2390 #interrupt-cells = <1>; 2391 interrupt-map-mask = <0 0 0 0>; 2392 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2393 2394 nvidia,bpmp = <&bpmp 1>; 2395 2396 nvidia,aspm-cmrt-us = <60>; 2397 nvidia,aspm-pwr-on-t-us = <20>; 2398 nvidia,aspm-l0s-entrance-latency-us = <3>; 2399 2400 bus-range = <0x0 0xff>; 2401 2402 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2403 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2404 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2405 2406 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2407 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2408 interconnect-names = "dma-mem", "write"; 2409 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2410 iommu-map-mask = <0x0>; 2411 dma-coherent; 2412 }; 2413 2414 pcie@14120000 { 2415 compatible = "nvidia,tegra194-pcie"; 2416 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2417 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2418 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2419 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2420 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2421 reg-names = "appl", "config", "atu_dma", "dbi"; 2422 2423 status = "disabled"; 2424 2425 #address-cells = <3>; 2426 #size-cells = <2>; 2427 device_type = "pci"; 2428 num-lanes = <1>; 2429 linux,pci-domain = <2>; 2430 2431 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2432 clock-names = "core"; 2433 2434 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2435 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2436 reset-names = "apb", "core"; 2437 2438 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2439 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2440 interrupt-names = "intr", "msi"; 2441 2442 #interrupt-cells = <1>; 2443 interrupt-map-mask = <0 0 0 0>; 2444 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2445 2446 nvidia,bpmp = <&bpmp 2>; 2447 2448 nvidia,aspm-cmrt-us = <60>; 2449 nvidia,aspm-pwr-on-t-us = <20>; 2450 nvidia,aspm-l0s-entrance-latency-us = <3>; 2451 2452 bus-range = <0x0 0xff>; 2453 2454 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2455 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2456 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2457 2458 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2459 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2460 interconnect-names = "dma-mem", "write"; 2461 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2462 iommu-map-mask = <0x0>; 2463 dma-coherent; 2464 }; 2465 2466 pcie@14140000 { 2467 compatible = "nvidia,tegra194-pcie"; 2468 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2469 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2470 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2471 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2472 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2473 reg-names = "appl", "config", "atu_dma", "dbi"; 2474 2475 status = "disabled"; 2476 2477 #address-cells = <3>; 2478 #size-cells = <2>; 2479 device_type = "pci"; 2480 num-lanes = <1>; 2481 linux,pci-domain = <3>; 2482 2483 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2484 clock-names = "core"; 2485 2486 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2487 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2488 reset-names = "apb", "core"; 2489 2490 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2491 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2492 interrupt-names = "intr", "msi"; 2493 2494 #interrupt-cells = <1>; 2495 interrupt-map-mask = <0 0 0 0>; 2496 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2497 2498 nvidia,bpmp = <&bpmp 3>; 2499 2500 nvidia,aspm-cmrt-us = <60>; 2501 nvidia,aspm-pwr-on-t-us = <20>; 2502 nvidia,aspm-l0s-entrance-latency-us = <3>; 2503 2504 bus-range = <0x0 0xff>; 2505 2506 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2507 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2508 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2509 2510 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2511 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2512 interconnect-names = "dma-mem", "write"; 2513 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2514 iommu-map-mask = <0x0>; 2515 dma-coherent; 2516 }; 2517 2518 pcie@14160000 { 2519 compatible = "nvidia,tegra194-pcie"; 2520 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2521 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2522 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2523 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2524 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2525 reg-names = "appl", "config", "atu_dma", "dbi"; 2526 2527 status = "disabled"; 2528 2529 #address-cells = <3>; 2530 #size-cells = <2>; 2531 device_type = "pci"; 2532 num-lanes = <4>; 2533 linux,pci-domain = <4>; 2534 2535 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2536 clock-names = "core"; 2537 2538 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2539 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2540 reset-names = "apb", "core"; 2541 2542 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2543 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2544 interrupt-names = "intr", "msi"; 2545 2546 #interrupt-cells = <1>; 2547 interrupt-map-mask = <0 0 0 0>; 2548 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2549 2550 nvidia,bpmp = <&bpmp 4>; 2551 2552 nvidia,aspm-cmrt-us = <60>; 2553 nvidia,aspm-pwr-on-t-us = <20>; 2554 nvidia,aspm-l0s-entrance-latency-us = <3>; 2555 2556 bus-range = <0x0 0xff>; 2557 2558 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2559 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2560 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2561 2562 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2563 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2564 interconnect-names = "dma-mem", "write"; 2565 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2566 iommu-map-mask = <0x0>; 2567 dma-coherent; 2568 }; 2569 2570 pcie-ep@14160000 { 2571 compatible = "nvidia,tegra194-pcie-ep"; 2572 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2573 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2574 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2575 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2576 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2577 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2578 2579 status = "disabled"; 2580 2581 num-lanes = <4>; 2582 num-ib-windows = <2>; 2583 num-ob-windows = <8>; 2584 2585 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2586 clock-names = "core"; 2587 2588 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2589 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2590 reset-names = "apb", "core"; 2591 2592 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2593 interrupt-names = "intr"; 2594 2595 nvidia,bpmp = <&bpmp 4>; 2596 2597 nvidia,aspm-cmrt-us = <60>; 2598 nvidia,aspm-pwr-on-t-us = <20>; 2599 nvidia,aspm-l0s-entrance-latency-us = <3>; 2600 2601 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2602 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2603 interconnect-names = "dma-mem", "write"; 2604 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2605 iommu-map-mask = <0x0>; 2606 dma-coherent; 2607 }; 2608 2609 pcie@14180000 { 2610 compatible = "nvidia,tegra194-pcie"; 2611 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2612 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2613 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2614 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2615 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2616 reg-names = "appl", "config", "atu_dma", "dbi"; 2617 2618 status = "disabled"; 2619 2620 #address-cells = <3>; 2621 #size-cells = <2>; 2622 device_type = "pci"; 2623 num-lanes = <8>; 2624 linux,pci-domain = <0>; 2625 2626 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2627 clock-names = "core"; 2628 2629 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2630 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2631 reset-names = "apb", "core"; 2632 2633 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2634 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2635 interrupt-names = "intr", "msi"; 2636 2637 #interrupt-cells = <1>; 2638 interrupt-map-mask = <0 0 0 0>; 2639 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2640 2641 nvidia,bpmp = <&bpmp 0>; 2642 2643 nvidia,aspm-cmrt-us = <60>; 2644 nvidia,aspm-pwr-on-t-us = <20>; 2645 nvidia,aspm-l0s-entrance-latency-us = <3>; 2646 2647 bus-range = <0x0 0xff>; 2648 2649 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2650 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2651 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2652 2653 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2654 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2655 interconnect-names = "dma-mem", "write"; 2656 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2657 iommu-map-mask = <0x0>; 2658 dma-coherent; 2659 }; 2660 2661 pcie-ep@14180000 { 2662 compatible = "nvidia,tegra194-pcie-ep"; 2663 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2664 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2665 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2666 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2667 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2668 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2669 2670 status = "disabled"; 2671 2672 num-lanes = <8>; 2673 num-ib-windows = <2>; 2674 num-ob-windows = <8>; 2675 2676 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2677 clock-names = "core"; 2678 2679 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2680 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2681 reset-names = "apb", "core"; 2682 2683 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2684 interrupt-names = "intr"; 2685 2686 nvidia,bpmp = <&bpmp 0>; 2687 2688 nvidia,aspm-cmrt-us = <60>; 2689 nvidia,aspm-pwr-on-t-us = <20>; 2690 nvidia,aspm-l0s-entrance-latency-us = <3>; 2691 2692 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2693 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2694 interconnect-names = "dma-mem", "write"; 2695 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2696 iommu-map-mask = <0x0>; 2697 dma-coherent; 2698 }; 2699 2700 pcie@141a0000 { 2701 compatible = "nvidia,tegra194-pcie"; 2702 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2703 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2704 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2705 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2706 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2707 reg-names = "appl", "config", "atu_dma", "dbi"; 2708 2709 status = "disabled"; 2710 2711 #address-cells = <3>; 2712 #size-cells = <2>; 2713 device_type = "pci"; 2714 num-lanes = <8>; 2715 linux,pci-domain = <5>; 2716 2717 pinctrl-names = "default"; 2718 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2719 2720 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2721 clock-names = "core"; 2722 2723 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2724 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2725 reset-names = "apb", "core"; 2726 2727 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2728 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2729 interrupt-names = "intr", "msi"; 2730 2731 nvidia,bpmp = <&bpmp 5>; 2732 2733 #interrupt-cells = <1>; 2734 interrupt-map-mask = <0 0 0 0>; 2735 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2736 2737 nvidia,aspm-cmrt-us = <60>; 2738 nvidia,aspm-pwr-on-t-us = <20>; 2739 nvidia,aspm-l0s-entrance-latency-us = <3>; 2740 2741 bus-range = <0x0 0xff>; 2742 2743 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2744 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2745 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2746 2747 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2748 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2749 interconnect-names = "dma-mem", "write"; 2750 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2751 iommu-map-mask = <0x0>; 2752 dma-coherent; 2753 }; 2754 2755 pcie-ep@141a0000 { 2756 compatible = "nvidia,tegra194-pcie-ep"; 2757 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2758 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2759 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2760 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2761 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2762 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2763 2764 status = "disabled"; 2765 2766 num-lanes = <8>; 2767 num-ib-windows = <2>; 2768 num-ob-windows = <8>; 2769 2770 pinctrl-names = "default"; 2771 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2772 2773 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2774 clock-names = "core"; 2775 2776 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2777 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2778 reset-names = "apb", "core"; 2779 2780 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2781 interrupt-names = "intr"; 2782 2783 nvidia,bpmp = <&bpmp 5>; 2784 2785 nvidia,aspm-cmrt-us = <60>; 2786 nvidia,aspm-pwr-on-t-us = <20>; 2787 nvidia,aspm-l0s-entrance-latency-us = <3>; 2788 2789 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2790 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2791 interconnect-names = "dma-mem", "write"; 2792 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2793 iommu-map-mask = <0x0>; 2794 dma-coherent; 2795 }; 2796 2797 gpu@17000000 { 2798 compatible = "nvidia,gv11b"; 2799 reg = <0x0 0x17000000 0x0 0x1000000>, 2800 <0x0 0x18000000 0x0 0x1000000>; 2801 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2803 interrupt-names = "stall", "nonstall"; 2804 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2805 <&bpmp TEGRA194_CLK_GPU_PWR>, 2806 <&bpmp TEGRA194_CLK_FUSE>; 2807 clock-names = "gpu", "pwr", "fuse"; 2808 resets = <&bpmp TEGRA194_RESET_GPU>; 2809 reset-names = "gpu"; 2810 dma-coherent; 2811 2812 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2813 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2814 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2815 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2816 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2817 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2818 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2819 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2820 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2821 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2822 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2823 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2824 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2825 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2826 "read-1", "read-1-hp", "write-1", 2827 "read-2", "read-2-hp", "write-2", 2828 "read-3", "read-3-hp", "write-3"; 2829 }; 2830 }; 2831 2832 sram@40000000 { 2833 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2834 reg = <0x0 0x40000000 0x0 0x50000>; 2835 2836 #address-cells = <1>; 2837 #size-cells = <1>; 2838 ranges = <0x0 0x0 0x40000000 0x50000>; 2839 2840 no-memory-wc; 2841 2842 cpu_bpmp_tx: sram@4e000 { 2843 reg = <0x4e000 0x1000>; 2844 label = "cpu-bpmp-tx"; 2845 pool; 2846 }; 2847 2848 cpu_bpmp_rx: sram@4f000 { 2849 reg = <0x4f000 0x1000>; 2850 label = "cpu-bpmp-rx"; 2851 pool; 2852 }; 2853 }; 2854 2855 bpmp: bpmp { 2856 compatible = "nvidia,tegra186-bpmp"; 2857 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2858 TEGRA_HSP_DB_MASTER_BPMP>; 2859 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2860 #clock-cells = <1>; 2861 #reset-cells = <1>; 2862 #power-domain-cells = <1>; 2863 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2864 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2865 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2866 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2867 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2868 iommus = <&smmu TEGRA194_SID_BPMP>; 2869 2870 bpmp_i2c: i2c { 2871 compatible = "nvidia,tegra186-bpmp-i2c"; 2872 nvidia,bpmp-bus-id = <5>; 2873 #address-cells = <1>; 2874 #size-cells = <0>; 2875 }; 2876 2877 bpmp_thermal: thermal { 2878 compatible = "nvidia,tegra186-bpmp-thermal"; 2879 #thermal-sensor-cells = <1>; 2880 }; 2881 }; 2882 2883 cpus { 2884 compatible = "nvidia,tegra194-ccplex"; 2885 nvidia,bpmp = <&bpmp>; 2886 #address-cells = <1>; 2887 #size-cells = <0>; 2888 2889 cpu0_0: cpu@0 { 2890 compatible = "nvidia,tegra194-carmel"; 2891 device_type = "cpu"; 2892 reg = <0x000>; 2893 enable-method = "psci"; 2894 i-cache-size = <131072>; 2895 i-cache-line-size = <64>; 2896 i-cache-sets = <512>; 2897 d-cache-size = <65536>; 2898 d-cache-line-size = <64>; 2899 d-cache-sets = <256>; 2900 next-level-cache = <&l2c_0>; 2901 }; 2902 2903 cpu0_1: cpu@1 { 2904 compatible = "nvidia,tegra194-carmel"; 2905 device_type = "cpu"; 2906 reg = <0x001>; 2907 enable-method = "psci"; 2908 i-cache-size = <131072>; 2909 i-cache-line-size = <64>; 2910 i-cache-sets = <512>; 2911 d-cache-size = <65536>; 2912 d-cache-line-size = <64>; 2913 d-cache-sets = <256>; 2914 next-level-cache = <&l2c_0>; 2915 }; 2916 2917 cpu1_0: cpu@100 { 2918 compatible = "nvidia,tegra194-carmel"; 2919 device_type = "cpu"; 2920 reg = <0x100>; 2921 enable-method = "psci"; 2922 i-cache-size = <131072>; 2923 i-cache-line-size = <64>; 2924 i-cache-sets = <512>; 2925 d-cache-size = <65536>; 2926 d-cache-line-size = <64>; 2927 d-cache-sets = <256>; 2928 next-level-cache = <&l2c_1>; 2929 }; 2930 2931 cpu1_1: cpu@101 { 2932 compatible = "nvidia,tegra194-carmel"; 2933 device_type = "cpu"; 2934 reg = <0x101>; 2935 enable-method = "psci"; 2936 i-cache-size = <131072>; 2937 i-cache-line-size = <64>; 2938 i-cache-sets = <512>; 2939 d-cache-size = <65536>; 2940 d-cache-line-size = <64>; 2941 d-cache-sets = <256>; 2942 next-level-cache = <&l2c_1>; 2943 }; 2944 2945 cpu2_0: cpu@200 { 2946 compatible = "nvidia,tegra194-carmel"; 2947 device_type = "cpu"; 2948 reg = <0x200>; 2949 enable-method = "psci"; 2950 i-cache-size = <131072>; 2951 i-cache-line-size = <64>; 2952 i-cache-sets = <512>; 2953 d-cache-size = <65536>; 2954 d-cache-line-size = <64>; 2955 d-cache-sets = <256>; 2956 next-level-cache = <&l2c_2>; 2957 }; 2958 2959 cpu2_1: cpu@201 { 2960 compatible = "nvidia,tegra194-carmel"; 2961 device_type = "cpu"; 2962 reg = <0x201>; 2963 enable-method = "psci"; 2964 i-cache-size = <131072>; 2965 i-cache-line-size = <64>; 2966 i-cache-sets = <512>; 2967 d-cache-size = <65536>; 2968 d-cache-line-size = <64>; 2969 d-cache-sets = <256>; 2970 next-level-cache = <&l2c_2>; 2971 }; 2972 2973 cpu3_0: cpu@300 { 2974 compatible = "nvidia,tegra194-carmel"; 2975 device_type = "cpu"; 2976 reg = <0x300>; 2977 enable-method = "psci"; 2978 i-cache-size = <131072>; 2979 i-cache-line-size = <64>; 2980 i-cache-sets = <512>; 2981 d-cache-size = <65536>; 2982 d-cache-line-size = <64>; 2983 d-cache-sets = <256>; 2984 next-level-cache = <&l2c_3>; 2985 }; 2986 2987 cpu3_1: cpu@301 { 2988 compatible = "nvidia,tegra194-carmel"; 2989 device_type = "cpu"; 2990 reg = <0x301>; 2991 enable-method = "psci"; 2992 i-cache-size = <131072>; 2993 i-cache-line-size = <64>; 2994 i-cache-sets = <512>; 2995 d-cache-size = <65536>; 2996 d-cache-line-size = <64>; 2997 d-cache-sets = <256>; 2998 next-level-cache = <&l2c_3>; 2999 }; 3000 3001 cpu-map { 3002 cluster0 { 3003 core0 { 3004 cpu = <&cpu0_0>; 3005 }; 3006 3007 core1 { 3008 cpu = <&cpu0_1>; 3009 }; 3010 }; 3011 3012 cluster1 { 3013 core0 { 3014 cpu = <&cpu1_0>; 3015 }; 3016 3017 core1 { 3018 cpu = <&cpu1_1>; 3019 }; 3020 }; 3021 3022 cluster2 { 3023 core0 { 3024 cpu = <&cpu2_0>; 3025 }; 3026 3027 core1 { 3028 cpu = <&cpu2_1>; 3029 }; 3030 }; 3031 3032 cluster3 { 3033 core0 { 3034 cpu = <&cpu3_0>; 3035 }; 3036 3037 core1 { 3038 cpu = <&cpu3_1>; 3039 }; 3040 }; 3041 }; 3042 3043 l2c_0: l2-cache0 { 3044 compatible = "cache"; 3045 cache-unified; 3046 cache-size = <2097152>; 3047 cache-line-size = <64>; 3048 cache-sets = <2048>; 3049 cache-level = <2>; 3050 next-level-cache = <&l3c>; 3051 }; 3052 3053 l2c_1: l2-cache1 { 3054 compatible = "cache"; 3055 cache-unified; 3056 cache-size = <2097152>; 3057 cache-line-size = <64>; 3058 cache-sets = <2048>; 3059 cache-level = <2>; 3060 next-level-cache = <&l3c>; 3061 }; 3062 3063 l2c_2: l2-cache2 { 3064 compatible = "cache"; 3065 cache-unified; 3066 cache-size = <2097152>; 3067 cache-line-size = <64>; 3068 cache-sets = <2048>; 3069 cache-level = <2>; 3070 next-level-cache = <&l3c>; 3071 }; 3072 3073 l2c_3: l2-cache3 { 3074 compatible = "cache"; 3075 cache-unified; 3076 cache-size = <2097152>; 3077 cache-line-size = <64>; 3078 cache-sets = <2048>; 3079 cache-level = <2>; 3080 next-level-cache = <&l3c>; 3081 }; 3082 3083 l3c: l3-cache { 3084 compatible = "cache"; 3085 cache-unified; 3086 cache-size = <4194304>; 3087 cache-line-size = <64>; 3088 cache-level = <3>; 3089 cache-sets = <4096>; 3090 }; 3091 }; 3092 3093 pmu { 3094 compatible = "nvidia,carmel-pmu"; 3095 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3103 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3104 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3105 }; 3106 3107 psci { 3108 compatible = "arm,psci-1.0"; 3109 status = "okay"; 3110 method = "smc"; 3111 }; 3112 3113 tcu: serial { 3114 compatible = "nvidia,tegra194-tcu"; 3115 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3116 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3117 mbox-names = "rx", "tx"; 3118 }; 3119 3120 sound { 3121 status = "disabled"; 3122 3123 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3124 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3125 clock-names = "pll_a", "plla_out0"; 3126 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3127 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3128 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3129 assigned-clock-parents = <0>, 3130 <&bpmp TEGRA194_CLK_PLLA>, 3131 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3132 /* 3133 * PLLA supports dynamic ramp. Below initial rate is chosen 3134 * for this to work and oscillate between base rates required 3135 * for 8x and 11.025x sample rate streams. 3136 */ 3137 assigned-clock-rates = <258000000>; 3138 }; 3139 3140 thermal-zones { 3141 cpu-thermal { 3142 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3143 status = "disabled"; 3144 }; 3145 3146 gpu-thermal { 3147 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3148 status = "disabled"; 3149 }; 3150 3151 aux-thermal { 3152 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3153 status = "disabled"; 3154 }; 3155 3156 pllx-thermal { 3157 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3158 status = "disabled"; 3159 }; 3160 3161 ao-thermal { 3162 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3163 status = "disabled"; 3164 }; 3165 3166 tj-thermal { 3167 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3168 status = "disabled"; 3169 }; 3170 }; 3171 3172 timer { 3173 compatible = "arm,armv8-timer"; 3174 interrupts = <GIC_PPI 13 3175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3176 <GIC_PPI 14 3177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3178 <GIC_PPI 11 3179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3180 <GIC_PPI 10 3181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3182 interrupt-parent = <&gic>; 3183 always-on; 3184 }; 3185}; 3186