1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 gpio-ranges = <&pinmux 0 0 140>; 40 }; 41 42 pinmux: pinmux@2430000 { 43 compatible = "nvidia,tegra186-pinmux"; 44 reg = <0x0 0x2430000 0x0 0x15000>; 45 }; 46 47 ethernet@2490000 { 48 compatible = "nvidia,tegra186-eqos", 49 "snps,dwc-qos-ethernet-4.10"; 50 reg = <0x0 0x02490000 0x0 0x10000>; 51 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 52 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 53 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 54 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 55 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 56 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 57 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 58 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 59 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 60 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 61 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 62 <&bpmp TEGRA186_CLK_EQOS_AXI>, 63 <&bpmp TEGRA186_CLK_EQOS_RX>, 64 <&bpmp TEGRA186_CLK_EQOS_TX>, 65 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 66 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 67 resets = <&bpmp TEGRA186_RESET_EQOS>; 68 reset-names = "eqos"; 69 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 70 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 71 interconnect-names = "dma-mem", "write"; 72 iommus = <&smmu TEGRA186_SID_EQOS>; 73 status = "disabled"; 74 75 snps,write-requests = <1>; 76 snps,read-requests = <3>; 77 snps,burst-map = <0x7>; 78 snps,txpbl = <32>; 79 snps,rxpbl = <8>; 80 }; 81 82 gpcdma: dma-controller@2600000 { 83 compatible = "nvidia,tegra186-gpcdma"; 84 reg = <0x0 0x2600000 0x0 0x210000>; 85 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 86 reset-names = "gpcdma"; 87 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 119 #dma-cells = <1>; 120 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 121 dma-coherent; 122 dma-channel-mask = <0xfffffffe>; 123 status = "okay"; 124 }; 125 126 aconnect@2900000 { 127 compatible = "nvidia,tegra186-aconnect", 128 "nvidia,tegra210-aconnect"; 129 clocks = <&bpmp TEGRA186_CLK_APE>, 130 <&bpmp TEGRA186_CLK_APB2APE>; 131 clock-names = "ape", "apb2ape"; 132 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 136 status = "disabled"; 137 138 tegra_ahub: ahub@2900800 { 139 compatible = "nvidia,tegra186-ahub"; 140 reg = <0x0 0x02900800 0x0 0x800>; 141 clocks = <&bpmp TEGRA186_CLK_AHUB>; 142 clock-names = "ahub"; 143 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 144 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 145 assigned-clock-rates = <81600000>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 149 status = "disabled"; 150 151 tegra_i2s1: i2s@2901000 { 152 compatible = "nvidia,tegra186-i2s", 153 "nvidia,tegra210-i2s"; 154 reg = <0x0 0x2901000 0x0 0x100>; 155 clocks = <&bpmp TEGRA186_CLK_I2S1>, 156 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 157 clock-names = "i2s", "sync_input"; 158 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 159 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 160 assigned-clock-rates = <1536000>; 161 sound-name-prefix = "I2S1"; 162 status = "disabled"; 163 }; 164 165 tegra_i2s2: i2s@2901100 { 166 compatible = "nvidia,tegra186-i2s", 167 "nvidia,tegra210-i2s"; 168 reg = <0x0 0x2901100 0x0 0x100>; 169 clocks = <&bpmp TEGRA186_CLK_I2S2>, 170 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 171 clock-names = "i2s", "sync_input"; 172 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 173 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 174 assigned-clock-rates = <1536000>; 175 sound-name-prefix = "I2S2"; 176 status = "disabled"; 177 }; 178 179 tegra_i2s3: i2s@2901200 { 180 compatible = "nvidia,tegra186-i2s", 181 "nvidia,tegra210-i2s"; 182 reg = <0x0 0x2901200 0x0 0x100>; 183 clocks = <&bpmp TEGRA186_CLK_I2S3>, 184 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 185 clock-names = "i2s", "sync_input"; 186 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 187 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 188 assigned-clock-rates = <1536000>; 189 sound-name-prefix = "I2S3"; 190 status = "disabled"; 191 }; 192 193 tegra_i2s4: i2s@2901300 { 194 compatible = "nvidia,tegra186-i2s", 195 "nvidia,tegra210-i2s"; 196 reg = <0x0 0x2901300 0x0 0x100>; 197 clocks = <&bpmp TEGRA186_CLK_I2S4>, 198 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 199 clock-names = "i2s", "sync_input"; 200 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 201 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 202 assigned-clock-rates = <1536000>; 203 sound-name-prefix = "I2S4"; 204 status = "disabled"; 205 }; 206 207 tegra_i2s5: i2s@2901400 { 208 compatible = "nvidia,tegra186-i2s", 209 "nvidia,tegra210-i2s"; 210 reg = <0x0 0x2901400 0x0 0x100>; 211 clocks = <&bpmp TEGRA186_CLK_I2S5>, 212 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 213 clock-names = "i2s", "sync_input"; 214 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 215 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 216 assigned-clock-rates = <1536000>; 217 sound-name-prefix = "I2S5"; 218 status = "disabled"; 219 }; 220 221 tegra_i2s6: i2s@2901500 { 222 compatible = "nvidia,tegra186-i2s", 223 "nvidia,tegra210-i2s"; 224 reg = <0x0 0x2901500 0x0 0x100>; 225 clocks = <&bpmp TEGRA186_CLK_I2S6>, 226 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 227 clock-names = "i2s", "sync_input"; 228 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 229 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 230 assigned-clock-rates = <1536000>; 231 sound-name-prefix = "I2S6"; 232 status = "disabled"; 233 }; 234 235 tegra_sfc1: sfc@2902000 { 236 compatible = "nvidia,tegra186-sfc", 237 "nvidia,tegra210-sfc"; 238 reg = <0x0 0x2902000 0x0 0x200>; 239 sound-name-prefix = "SFC1"; 240 status = "disabled"; 241 }; 242 243 tegra_sfc2: sfc@2902200 { 244 compatible = "nvidia,tegra186-sfc", 245 "nvidia,tegra210-sfc"; 246 reg = <0x0 0x2902200 0x0 0x200>; 247 sound-name-prefix = "SFC2"; 248 status = "disabled"; 249 }; 250 251 tegra_sfc3: sfc@2902400 { 252 compatible = "nvidia,tegra186-sfc", 253 "nvidia,tegra210-sfc"; 254 reg = <0x0 0x2902400 0x0 0x200>; 255 sound-name-prefix = "SFC3"; 256 status = "disabled"; 257 }; 258 259 tegra_sfc4: sfc@2902600 { 260 compatible = "nvidia,tegra186-sfc", 261 "nvidia,tegra210-sfc"; 262 reg = <0x0 0x2902600 0x0 0x200>; 263 sound-name-prefix = "SFC4"; 264 status = "disabled"; 265 }; 266 267 tegra_amx1: amx@2903000 { 268 compatible = "nvidia,tegra186-amx", 269 "nvidia,tegra210-amx"; 270 reg = <0x0 0x2903000 0x0 0x100>; 271 sound-name-prefix = "AMX1"; 272 status = "disabled"; 273 }; 274 275 tegra_amx2: amx@2903100 { 276 compatible = "nvidia,tegra186-amx", 277 "nvidia,tegra210-amx"; 278 reg = <0x0 0x2903100 0x0 0x100>; 279 sound-name-prefix = "AMX2"; 280 status = "disabled"; 281 }; 282 283 tegra_amx3: amx@2903200 { 284 compatible = "nvidia,tegra186-amx", 285 "nvidia,tegra210-amx"; 286 reg = <0x0 0x2903200 0x0 0x100>; 287 sound-name-prefix = "AMX3"; 288 status = "disabled"; 289 }; 290 291 tegra_amx4: amx@2903300 { 292 compatible = "nvidia,tegra186-amx", 293 "nvidia,tegra210-amx"; 294 reg = <0x0 0x2903300 0x0 0x100>; 295 sound-name-prefix = "AMX4"; 296 status = "disabled"; 297 }; 298 299 tegra_adx1: adx@2903800 { 300 compatible = "nvidia,tegra186-adx", 301 "nvidia,tegra210-adx"; 302 reg = <0x0 0x2903800 0x0 0x100>; 303 sound-name-prefix = "ADX1"; 304 status = "disabled"; 305 }; 306 307 tegra_adx2: adx@2903900 { 308 compatible = "nvidia,tegra186-adx", 309 "nvidia,tegra210-adx"; 310 reg = <0x0 0x2903900 0x0 0x100>; 311 sound-name-prefix = "ADX2"; 312 status = "disabled"; 313 }; 314 315 tegra_adx3: adx@2903a00 { 316 compatible = "nvidia,tegra186-adx", 317 "nvidia,tegra210-adx"; 318 reg = <0x0 0x2903a00 0x0 0x100>; 319 sound-name-prefix = "ADX3"; 320 status = "disabled"; 321 }; 322 323 tegra_adx4: adx@2903b00 { 324 compatible = "nvidia,tegra186-adx", 325 "nvidia,tegra210-adx"; 326 reg = <0x0 0x2903b00 0x0 0x100>; 327 sound-name-prefix = "ADX4"; 328 status = "disabled"; 329 }; 330 331 tegra_dmic1: dmic@2904000 { 332 compatible = "nvidia,tegra210-dmic"; 333 reg = <0x0 0x2904000 0x0 0x100>; 334 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 335 clock-names = "dmic"; 336 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 337 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 338 assigned-clock-rates = <3072000>; 339 sound-name-prefix = "DMIC1"; 340 status = "disabled"; 341 }; 342 343 tegra_dmic2: dmic@2904100 { 344 compatible = "nvidia,tegra210-dmic"; 345 reg = <0x0 0x2904100 0x0 0x100>; 346 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 347 clock-names = "dmic"; 348 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 349 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 350 assigned-clock-rates = <3072000>; 351 sound-name-prefix = "DMIC2"; 352 status = "disabled"; 353 }; 354 355 tegra_dmic3: dmic@2904200 { 356 compatible = "nvidia,tegra210-dmic"; 357 reg = <0x0 0x2904200 0x0 0x100>; 358 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 359 clock-names = "dmic"; 360 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 361 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 362 assigned-clock-rates = <3072000>; 363 sound-name-prefix = "DMIC3"; 364 status = "disabled"; 365 }; 366 367 tegra_dmic4: dmic@2904300 { 368 compatible = "nvidia,tegra210-dmic"; 369 reg = <0x0 0x2904300 0x0 0x100>; 370 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 371 clock-names = "dmic"; 372 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 373 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 374 assigned-clock-rates = <3072000>; 375 sound-name-prefix = "DMIC4"; 376 status = "disabled"; 377 }; 378 379 tegra_dspk1: dspk@2905000 { 380 compatible = "nvidia,tegra186-dspk"; 381 reg = <0x0 0x2905000 0x0 0x100>; 382 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 383 clock-names = "dspk"; 384 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 385 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 386 assigned-clock-rates = <12288000>; 387 sound-name-prefix = "DSPK1"; 388 status = "disabled"; 389 }; 390 391 tegra_dspk2: dspk@2905100 { 392 compatible = "nvidia,tegra186-dspk"; 393 reg = <0x0 0x2905100 0x0 0x100>; 394 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 395 clock-names = "dspk"; 396 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 397 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 398 assigned-clock-rates = <12288000>; 399 sound-name-prefix = "DSPK2"; 400 status = "disabled"; 401 }; 402 403 tegra_ope1: processing-engine@2908000 { 404 compatible = "nvidia,tegra186-ope", 405 "nvidia,tegra210-ope"; 406 reg = <0x0 0x2908000 0x0 0x100>; 407 #address-cells = <2>; 408 #size-cells = <2>; 409 ranges; 410 sound-name-prefix = "OPE1"; 411 status = "disabled"; 412 413 equalizer@2908100 { 414 compatible = "nvidia,tegra186-peq", 415 "nvidia,tegra210-peq"; 416 reg = <0x0 0x2908100 0x0 0x100>; 417 }; 418 419 dynamic-range-compressor@2908200 { 420 compatible = "nvidia,tegra186-mbdrc", 421 "nvidia,tegra210-mbdrc"; 422 reg = <0x0 0x2908200 0x0 0x200>; 423 }; 424 }; 425 426 tegra_mvc1: mvc@290a000 { 427 compatible = "nvidia,tegra186-mvc", 428 "nvidia,tegra210-mvc"; 429 reg = <0x0 0x290a000 0x0 0x200>; 430 sound-name-prefix = "MVC1"; 431 status = "disabled"; 432 }; 433 434 tegra_mvc2: mvc@290a200 { 435 compatible = "nvidia,tegra186-mvc", 436 "nvidia,tegra210-mvc"; 437 reg = <0x0 0x290a200 0x0 0x200>; 438 sound-name-prefix = "MVC2"; 439 status = "disabled"; 440 }; 441 442 tegra_amixer: amixer@290bb00 { 443 compatible = "nvidia,tegra186-amixer", 444 "nvidia,tegra210-amixer"; 445 reg = <0x0 0x290bb00 0x0 0x800>; 446 sound-name-prefix = "MIXER1"; 447 status = "disabled"; 448 }; 449 450 tegra_admaif: admaif@290f000 { 451 compatible = "nvidia,tegra186-admaif"; 452 reg = <0x0 0x0290f000 0x0 0x1000>; 453 dmas = <&adma 1>, <&adma 1>, 454 <&adma 2>, <&adma 2>, 455 <&adma 3>, <&adma 3>, 456 <&adma 4>, <&adma 4>, 457 <&adma 5>, <&adma 5>, 458 <&adma 6>, <&adma 6>, 459 <&adma 7>, <&adma 7>, 460 <&adma 8>, <&adma 8>, 461 <&adma 9>, <&adma 9>, 462 <&adma 10>, <&adma 10>, 463 <&adma 11>, <&adma 11>, 464 <&adma 12>, <&adma 12>, 465 <&adma 13>, <&adma 13>, 466 <&adma 14>, <&adma 14>, 467 <&adma 15>, <&adma 15>, 468 <&adma 16>, <&adma 16>, 469 <&adma 17>, <&adma 17>, 470 <&adma 18>, <&adma 18>, 471 <&adma 19>, <&adma 19>, 472 <&adma 20>, <&adma 20>; 473 dma-names = "rx1", "tx1", 474 "rx2", "tx2", 475 "rx3", "tx3", 476 "rx4", "tx4", 477 "rx5", "tx5", 478 "rx6", "tx6", 479 "rx7", "tx7", 480 "rx8", "tx8", 481 "rx9", "tx9", 482 "rx10", "tx10", 483 "rx11", "tx11", 484 "rx12", "tx12", 485 "rx13", "tx13", 486 "rx14", "tx14", 487 "rx15", "tx15", 488 "rx16", "tx16", 489 "rx17", "tx17", 490 "rx18", "tx18", 491 "rx19", "tx19", 492 "rx20", "tx20"; 493 status = "disabled"; 494 }; 495 496 tegra_asrc: asrc@2910000 { 497 compatible = "nvidia,tegra186-asrc"; 498 reg = <0x0 0x2910000 0x0 0x2000>; 499 sound-name-prefix = "ASRC1"; 500 status = "disabled"; 501 }; 502 }; 503 504 adma: dma-controller@2930000 { 505 compatible = "nvidia,tegra186-adma"; 506 reg = <0x0 0x02930000 0x0 0x20000>; 507 interrupt-parent = <&agic>; 508 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 540 #dma-cells = <1>; 541 clocks = <&bpmp TEGRA186_CLK_AHUB>; 542 clock-names = "d_audio"; 543 status = "disabled"; 544 }; 545 546 agic: interrupt-controller@2a40000 { 547 compatible = "nvidia,tegra186-agic", 548 "nvidia,tegra210-agic"; 549 #interrupt-cells = <3>; 550 interrupt-controller; 551 reg = <0x0 0x02a41000 0x0 0x1000>, 552 <0x0 0x02a42000 0x0 0x2000>; 553 interrupts = <GIC_SPI 145 554 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 555 clocks = <&bpmp TEGRA186_CLK_APE>; 556 clock-names = "clk"; 557 status = "disabled"; 558 }; 559 }; 560 561 mc: memory-controller@2c00000 { 562 compatible = "nvidia,tegra186-mc"; 563 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 564 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 565 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 566 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 567 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 568 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 569 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 570 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 571 status = "disabled"; 572 573 #interconnect-cells = <1>; 574 #address-cells = <2>; 575 #size-cells = <2>; 576 577 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 578 579 /* 580 * Memory clients have access to all 40 bits that the memory 581 * controller can address. 582 */ 583 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 584 585 emc: external-memory-controller@2c60000 { 586 compatible = "nvidia,tegra186-emc"; 587 reg = <0x0 0x02c60000 0x0 0x50000>; 588 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&bpmp TEGRA186_CLK_EMC>; 590 clock-names = "emc"; 591 592 #interconnect-cells = <0>; 593 594 nvidia,bpmp = <&bpmp>; 595 }; 596 }; 597 598 timer@3010000 { 599 compatible = "nvidia,tegra186-timer"; 600 reg = <0x0 0x03010000 0x0 0x000e0000>; 601 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 611 status = "okay"; 612 }; 613 614 uarta: serial@3100000 { 615 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 616 reg = <0x0 0x03100000 0x0 0x40>; 617 reg-shift = <2>; 618 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&bpmp TEGRA186_CLK_UARTA>; 620 resets = <&bpmp TEGRA186_RESET_UARTA>; 621 dmas = <&gpcdma 8>, <&gpcdma 8>; 622 dma-names = "rx", "tx"; 623 status = "disabled"; 624 }; 625 626 uartb: serial@3110000 { 627 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 628 reg = <0x0 0x03110000 0x0 0x40>; 629 reg-shift = <2>; 630 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&bpmp TEGRA186_CLK_UARTB>; 632 resets = <&bpmp TEGRA186_RESET_UARTB>; 633 dmas = <&gpcdma 9>, <&gpcdma 9>; 634 dma-names = "rx", "tx"; 635 status = "disabled"; 636 }; 637 638 uartd: serial@3130000 { 639 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 640 reg = <0x0 0x03130000 0x0 0x40>; 641 reg-shift = <2>; 642 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA186_CLK_UARTD>; 644 resets = <&bpmp TEGRA186_RESET_UARTD>; 645 dmas = <&gpcdma 19>, <&gpcdma 19>; 646 dma-names = "rx", "tx"; 647 status = "disabled"; 648 }; 649 650 uarte: serial@3140000 { 651 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 652 reg = <0x0 0x03140000 0x0 0x40>; 653 reg-shift = <2>; 654 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&bpmp TEGRA186_CLK_UARTE>; 656 resets = <&bpmp TEGRA186_RESET_UARTE>; 657 dmas = <&gpcdma 20>, <&gpcdma 20>; 658 dma-names = "rx", "tx"; 659 status = "disabled"; 660 }; 661 662 uartf: serial@3150000 { 663 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 664 reg = <0x0 0x03150000 0x0 0x40>; 665 reg-shift = <2>; 666 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&bpmp TEGRA186_CLK_UARTF>; 668 resets = <&bpmp TEGRA186_RESET_UARTF>; 669 dmas = <&gpcdma 12>, <&gpcdma 12>; 670 dma-names = "rx", "tx"; 671 status = "disabled"; 672 }; 673 674 gen1_i2c: i2c@3160000 { 675 compatible = "nvidia,tegra186-i2c"; 676 reg = <0x0 0x03160000 0x0 0x10000>; 677 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 clocks = <&bpmp TEGRA186_CLK_I2C1>; 681 clock-names = "div-clk"; 682 resets = <&bpmp TEGRA186_RESET_I2C1>; 683 reset-names = "i2c"; 684 dmas = <&gpcdma 21>, <&gpcdma 21>; 685 dma-names = "rx", "tx"; 686 status = "disabled"; 687 }; 688 689 cam_i2c: i2c@3180000 { 690 compatible = "nvidia,tegra186-i2c"; 691 reg = <0x0 0x03180000 0x0 0x10000>; 692 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 clocks = <&bpmp TEGRA186_CLK_I2C3>; 696 clock-names = "div-clk"; 697 resets = <&bpmp TEGRA186_RESET_I2C3>; 698 reset-names = "i2c"; 699 dmas = <&gpcdma 23>, <&gpcdma 23>; 700 dma-names = "rx", "tx"; 701 status = "disabled"; 702 }; 703 704 /* shares pads with dpaux1 */ 705 dp_aux_ch1_i2c: i2c@3190000 { 706 compatible = "nvidia,tegra186-i2c"; 707 reg = <0x0 0x03190000 0x0 0x10000>; 708 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&bpmp TEGRA186_CLK_I2C4>; 712 clock-names = "div-clk"; 713 resets = <&bpmp TEGRA186_RESET_I2C4>; 714 reset-names = "i2c"; 715 pinctrl-names = "default", "idle"; 716 pinctrl-0 = <&state_dpaux1_i2c>; 717 pinctrl-1 = <&state_dpaux1_off>; 718 dmas = <&gpcdma 26>, <&gpcdma 26>; 719 dma-names = "rx", "tx"; 720 status = "disabled"; 721 }; 722 723 /* controlled by BPMP, should not be enabled */ 724 pwr_i2c: i2c@31a0000 { 725 compatible = "nvidia,tegra186-i2c"; 726 reg = <0x0 0x031a0000 0x0 0x10000>; 727 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 clocks = <&bpmp TEGRA186_CLK_I2C5>; 731 clock-names = "div-clk"; 732 resets = <&bpmp TEGRA186_RESET_I2C5>; 733 reset-names = "i2c"; 734 status = "disabled"; 735 }; 736 737 /* shares pads with dpaux0 */ 738 dp_aux_ch0_i2c: i2c@31b0000 { 739 compatible = "nvidia,tegra186-i2c"; 740 reg = <0x0 0x031b0000 0x0 0x10000>; 741 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&bpmp TEGRA186_CLK_I2C6>; 745 clock-names = "div-clk"; 746 resets = <&bpmp TEGRA186_RESET_I2C6>; 747 reset-names = "i2c"; 748 pinctrl-names = "default", "idle"; 749 pinctrl-0 = <&state_dpaux_i2c>; 750 pinctrl-1 = <&state_dpaux_off>; 751 dmas = <&gpcdma 30>, <&gpcdma 30>; 752 dma-names = "rx", "tx"; 753 status = "disabled"; 754 }; 755 756 gen7_i2c: i2c@31c0000 { 757 compatible = "nvidia,tegra186-i2c"; 758 reg = <0x0 0x031c0000 0x0 0x10000>; 759 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 clocks = <&bpmp TEGRA186_CLK_I2C7>; 763 clock-names = "div-clk"; 764 resets = <&bpmp TEGRA186_RESET_I2C7>; 765 reset-names = "i2c"; 766 dmas = <&gpcdma 27>, <&gpcdma 27>; 767 dma-names = "rx", "tx"; 768 status = "disabled"; 769 }; 770 771 gen9_i2c: i2c@31e0000 { 772 compatible = "nvidia,tegra186-i2c"; 773 reg = <0x0 0x031e0000 0x0 0x10000>; 774 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 clocks = <&bpmp TEGRA186_CLK_I2C9>; 778 clock-names = "div-clk"; 779 resets = <&bpmp TEGRA186_RESET_I2C9>; 780 reset-names = "i2c"; 781 dmas = <&gpcdma 31>, <&gpcdma 31>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 pwm1: pwm@3280000 { 787 compatible = "nvidia,tegra186-pwm"; 788 reg = <0x0 0x3280000 0x0 0x10000>; 789 clocks = <&bpmp TEGRA186_CLK_PWM1>; 790 resets = <&bpmp TEGRA186_RESET_PWM1>; 791 reset-names = "pwm"; 792 status = "disabled"; 793 #pwm-cells = <2>; 794 }; 795 796 pwm2: pwm@3290000 { 797 compatible = "nvidia,tegra186-pwm"; 798 reg = <0x0 0x3290000 0x0 0x10000>; 799 clocks = <&bpmp TEGRA186_CLK_PWM2>; 800 resets = <&bpmp TEGRA186_RESET_PWM2>; 801 reset-names = "pwm"; 802 status = "disabled"; 803 #pwm-cells = <2>; 804 }; 805 806 pwm3: pwm@32a0000 { 807 compatible = "nvidia,tegra186-pwm"; 808 reg = <0x0 0x32a0000 0x0 0x10000>; 809 clocks = <&bpmp TEGRA186_CLK_PWM3>; 810 resets = <&bpmp TEGRA186_RESET_PWM3>; 811 reset-names = "pwm"; 812 status = "disabled"; 813 #pwm-cells = <2>; 814 }; 815 816 pwm5: pwm@32c0000 { 817 compatible = "nvidia,tegra186-pwm"; 818 reg = <0x0 0x32c0000 0x0 0x10000>; 819 clocks = <&bpmp TEGRA186_CLK_PWM5>; 820 resets = <&bpmp TEGRA186_RESET_PWM5>; 821 reset-names = "pwm"; 822 status = "disabled"; 823 #pwm-cells = <2>; 824 }; 825 826 pwm6: pwm@32d0000 { 827 compatible = "nvidia,tegra186-pwm"; 828 reg = <0x0 0x32d0000 0x0 0x10000>; 829 clocks = <&bpmp TEGRA186_CLK_PWM6>; 830 resets = <&bpmp TEGRA186_RESET_PWM6>; 831 reset-names = "pwm"; 832 status = "disabled"; 833 #pwm-cells = <2>; 834 }; 835 836 pwm7: pwm@32e0000 { 837 compatible = "nvidia,tegra186-pwm"; 838 reg = <0x0 0x32e0000 0x0 0x10000>; 839 clocks = <&bpmp TEGRA186_CLK_PWM7>; 840 resets = <&bpmp TEGRA186_RESET_PWM7>; 841 reset-names = "pwm"; 842 status = "disabled"; 843 #pwm-cells = <2>; 844 }; 845 846 pwm8: pwm@32f0000 { 847 compatible = "nvidia,tegra186-pwm"; 848 reg = <0x0 0x32f0000 0x0 0x10000>; 849 clocks = <&bpmp TEGRA186_CLK_PWM8>; 850 resets = <&bpmp TEGRA186_RESET_PWM8>; 851 reset-names = "pwm"; 852 status = "disabled"; 853 #pwm-cells = <2>; 854 }; 855 856 sdmmc1: mmc@3400000 { 857 compatible = "nvidia,tegra186-sdhci"; 858 reg = <0x0 0x03400000 0x0 0x10000>; 859 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 861 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 862 clock-names = "sdhci", "tmclk"; 863 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 864 reset-names = "sdhci"; 865 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 866 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 867 interconnect-names = "dma-mem", "write"; 868 iommus = <&smmu TEGRA186_SID_SDMMC1>; 869 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 870 pinctrl-0 = <&sdmmc1_3v3>; 871 pinctrl-1 = <&sdmmc1_1v8>; 872 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 873 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 874 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 875 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 876 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 877 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 878 nvidia,default-tap = <0x5>; 879 nvidia,default-trim = <0xb>; 880 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 881 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 882 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 883 status = "disabled"; 884 }; 885 886 sdmmc2: mmc@3420000 { 887 compatible = "nvidia,tegra186-sdhci"; 888 reg = <0x0 0x03420000 0x0 0x10000>; 889 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 891 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 892 clock-names = "sdhci", "tmclk"; 893 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 894 reset-names = "sdhci"; 895 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 896 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 897 interconnect-names = "dma-mem", "write"; 898 iommus = <&smmu TEGRA186_SID_SDMMC2>; 899 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 900 pinctrl-0 = <&sdmmc2_3v3>; 901 pinctrl-1 = <&sdmmc2_1v8>; 902 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 903 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 904 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 905 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 906 nvidia,default-tap = <0x5>; 907 nvidia,default-trim = <0xb>; 908 status = "disabled"; 909 }; 910 911 sdmmc3: mmc@3440000 { 912 compatible = "nvidia,tegra186-sdhci"; 913 reg = <0x0 0x03440000 0x0 0x10000>; 914 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 916 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 917 clock-names = "sdhci", "tmclk"; 918 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 919 reset-names = "sdhci"; 920 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 921 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 922 interconnect-names = "dma-mem", "write"; 923 iommus = <&smmu TEGRA186_SID_SDMMC3>; 924 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 925 pinctrl-0 = <&sdmmc3_3v3>; 926 pinctrl-1 = <&sdmmc3_1v8>; 927 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 928 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 929 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 930 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 931 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 932 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 933 nvidia,default-tap = <0x5>; 934 nvidia,default-trim = <0xb>; 935 status = "disabled"; 936 }; 937 938 sdmmc4: mmc@3460000 { 939 compatible = "nvidia,tegra186-sdhci"; 940 reg = <0x0 0x03460000 0x0 0x10000>; 941 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 943 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 944 clock-names = "sdhci", "tmclk"; 945 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 946 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 947 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 948 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 949 reset-names = "sdhci"; 950 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 951 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 952 interconnect-names = "dma-mem", "write"; 953 iommus = <&smmu TEGRA186_SID_SDMMC4>; 954 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 955 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 956 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 959 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 960 nvidia,default-tap = <0x9>; 961 nvidia,default-trim = <0x5>; 962 nvidia,dqs-trim = <63>; 963 mmc-hs400-1_8v; 964 supports-cqe; 965 status = "disabled"; 966 }; 967 968 sata@3507000 { 969 compatible = "nvidia,tegra186-ahci"; 970 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 971 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 972 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 973 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 974 975 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 976 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 977 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 978 interconnect-names = "dma-mem", "write"; 979 iommus = <&smmu TEGRA186_SID_SATA>; 980 981 clocks = <&bpmp TEGRA186_CLK_SATA>, 982 <&bpmp TEGRA186_CLK_SATA_OOB>; 983 clock-names = "sata", "sata-oob"; 984 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 985 <&bpmp TEGRA186_CLK_SATA_OOB>; 986 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 987 <&bpmp TEGRA186_CLK_PLLP>; 988 assigned-clock-rates = <102000000>, 989 <204000000>; 990 resets = <&bpmp TEGRA186_RESET_SATA>, 991 <&bpmp TEGRA186_RESET_SATACOLD>; 992 reset-names = "sata", "sata-cold"; 993 status = "disabled"; 994 }; 995 996 hda@3510000 { 997 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 998 reg = <0x0 0x03510000 0x0 0x10000>; 999 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&bpmp TEGRA186_CLK_HDA>, 1001 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 1002 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 1003 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1004 resets = <&bpmp TEGRA186_RESET_HDA>, 1005 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 1006 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1007 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1008 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1009 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1010 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1011 interconnect-names = "dma-mem", "write"; 1012 iommus = <&smmu TEGRA186_SID_HDA>; 1013 status = "disabled"; 1014 }; 1015 1016 padctl: padctl@3520000 { 1017 compatible = "nvidia,tegra186-xusb-padctl"; 1018 reg = <0x0 0x03520000 0x0 0x1000>, 1019 <0x0 0x03540000 0x0 0x1000>; 1020 reg-names = "padctl", "ao"; 1021 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1022 1023 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1024 reset-names = "padctl"; 1025 1026 status = "disabled"; 1027 1028 pads { 1029 usb2 { 1030 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1031 clock-names = "trk"; 1032 status = "disabled"; 1033 1034 lanes { 1035 usb2-0 { 1036 status = "disabled"; 1037 #phy-cells = <0>; 1038 }; 1039 1040 usb2-1 { 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 1045 usb2-2 { 1046 status = "disabled"; 1047 #phy-cells = <0>; 1048 }; 1049 }; 1050 }; 1051 1052 hsic { 1053 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1054 clock-names = "trk"; 1055 status = "disabled"; 1056 1057 lanes { 1058 hsic-0 { 1059 status = "disabled"; 1060 #phy-cells = <0>; 1061 }; 1062 }; 1063 }; 1064 1065 usb3 { 1066 status = "disabled"; 1067 1068 lanes { 1069 usb3-0 { 1070 status = "disabled"; 1071 #phy-cells = <0>; 1072 }; 1073 1074 usb3-1 { 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 1079 usb3-2 { 1080 status = "disabled"; 1081 #phy-cells = <0>; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 ports { 1088 usb2-0 { 1089 status = "disabled"; 1090 }; 1091 1092 usb2-1 { 1093 status = "disabled"; 1094 }; 1095 1096 usb2-2 { 1097 status = "disabled"; 1098 }; 1099 1100 hsic-0 { 1101 status = "disabled"; 1102 }; 1103 1104 usb3-0 { 1105 status = "disabled"; 1106 }; 1107 1108 usb3-1 { 1109 status = "disabled"; 1110 }; 1111 1112 usb3-2 { 1113 status = "disabled"; 1114 }; 1115 }; 1116 }; 1117 1118 usb@3530000 { 1119 compatible = "nvidia,tegra186-xusb"; 1120 reg = <0x0 0x03530000 0x0 0x8000>, 1121 <0x0 0x03538000 0x0 0x1000>; 1122 reg-names = "hcd", "fpci"; 1123 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1126 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1127 <&bpmp TEGRA186_CLK_XUSB_SS>, 1128 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1129 <&bpmp TEGRA186_CLK_CLK_M>, 1130 <&bpmp TEGRA186_CLK_XUSB_FS>, 1131 <&bpmp TEGRA186_CLK_PLLU>, 1132 <&bpmp TEGRA186_CLK_CLK_M>, 1133 <&bpmp TEGRA186_CLK_PLLE>; 1134 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1135 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1136 "pll_u_480m", "clk_m", "pll_e"; 1137 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1138 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1139 power-domain-names = "xusb_host", "xusb_ss"; 1140 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1141 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1142 interconnect-names = "dma-mem", "write"; 1143 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 1148 nvidia,xusb-padctl = <&padctl>; 1149 }; 1150 1151 usb@3550000 { 1152 compatible = "nvidia,tegra186-xudc"; 1153 reg = <0x0 0x03550000 0x0 0x8000>, 1154 <0x0 0x03558000 0x0 0x1000>; 1155 reg-names = "base", "fpci"; 1156 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1158 <&bpmp TEGRA186_CLK_XUSB_SS>, 1159 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1160 <&bpmp TEGRA186_CLK_XUSB_FS>; 1161 clock-names = "dev", "ss", "ss_src", "fs_src"; 1162 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1163 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1164 interconnect-names = "dma-mem", "write"; 1165 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1166 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1167 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1168 power-domain-names = "dev", "ss"; 1169 nvidia,xusb-padctl = <&padctl>; 1170 status = "disabled"; 1171 }; 1172 1173 fuse@3820000 { 1174 compatible = "nvidia,tegra186-efuse"; 1175 reg = <0x0 0x03820000 0x0 0x10000>; 1176 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1177 clock-names = "fuse"; 1178 }; 1179 1180 gic: interrupt-controller@3881000 { 1181 compatible = "arm,gic-400"; 1182 #address-cells = <0>; 1183 #interrupt-cells = <3>; 1184 interrupt-controller; 1185 reg = <0x0 0x03881000 0x0 0x1000>, 1186 <0x0 0x03882000 0x0 0x2000>, 1187 <0x0 0x03884000 0x0 0x2000>, 1188 <0x0 0x03886000 0x0 0x2000>; 1189 interrupts = <GIC_PPI 9 1190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1191 interrupt-parent = <&gic>; 1192 }; 1193 1194 cec@3960000 { 1195 compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec"; 1196 reg = <0x0 0x03960000 0x0 0x10000>; 1197 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&bpmp TEGRA186_CLK_CEC>; 1199 clock-names = "cec"; 1200 status = "disabled"; 1201 }; 1202 1203 hsp_top0: hsp@3c00000 { 1204 compatible = "nvidia,tegra186-hsp"; 1205 reg = <0x0 0x03c00000 0x0 0xa0000>; 1206 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1207 interrupt-names = "doorbell"; 1208 #mbox-cells = <2>; 1209 status = "disabled"; 1210 }; 1211 1212 gen2_i2c: i2c@c240000 { 1213 compatible = "nvidia,tegra186-i2c"; 1214 reg = <0x0 0x0c240000 0x0 0x10000>; 1215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1219 clock-names = "div-clk"; 1220 resets = <&bpmp TEGRA186_RESET_I2C2>; 1221 reset-names = "i2c"; 1222 dmas = <&gpcdma 22>, <&gpcdma 22>; 1223 dma-names = "rx", "tx"; 1224 status = "disabled"; 1225 }; 1226 1227 gen8_i2c: i2c@c250000 { 1228 compatible = "nvidia,tegra186-i2c"; 1229 reg = <0x0 0x0c250000 0x0 0x10000>; 1230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1234 clock-names = "div-clk"; 1235 resets = <&bpmp TEGRA186_RESET_I2C8>; 1236 reset-names = "i2c"; 1237 dmas = <&gpcdma 0>, <&gpcdma 0>; 1238 dma-names = "rx", "tx"; 1239 status = "disabled"; 1240 }; 1241 1242 uartc: serial@c280000 { 1243 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1244 reg = <0x0 0x0c280000 0x0 0x40>; 1245 reg-shift = <2>; 1246 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1248 resets = <&bpmp TEGRA186_RESET_UARTC>; 1249 dmas = <&gpcdma 3>, <&gpcdma 3>; 1250 dma-names = "rx", "tx"; 1251 status = "disabled"; 1252 }; 1253 1254 uartg: serial@c290000 { 1255 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1256 reg = <0x0 0x0c290000 0x0 0x40>; 1257 reg-shift = <2>; 1258 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1260 resets = <&bpmp TEGRA186_RESET_UARTG>; 1261 dmas = <&gpcdma 2>, <&gpcdma 2>; 1262 dma-names = "rx", "tx"; 1263 status = "disabled"; 1264 }; 1265 1266 rtc: rtc@c2a0000 { 1267 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1268 reg = <0 0x0c2a0000 0 0x10000>; 1269 interrupt-parent = <&pmc>; 1270 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1272 clock-names = "rtc"; 1273 status = "disabled"; 1274 }; 1275 1276 gpio_aon: gpio@c2f0000 { 1277 compatible = "nvidia,tegra186-gpio-aon"; 1278 reg-names = "security", "gpio"; 1279 reg = <0x0 0xc2f0000 0x0 0x1000>, 1280 <0x0 0xc2f1000 0x0 0x1000>; 1281 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1282 gpio-controller; 1283 #gpio-cells = <2>; 1284 gpio-ranges = <&pinmux_aon 0 0 47>; 1285 interrupt-controller; 1286 #interrupt-cells = <2>; 1287 }; 1288 1289 pinmux_aon: pinmux@c300000 { 1290 compatible = "nvidia,tegra186-pinmux-aon"; 1291 reg = <0x0 0xc300000 0x0 0x4000>; 1292 }; 1293 1294 pwm4: pwm@c340000 { 1295 compatible = "nvidia,tegra186-pwm"; 1296 reg = <0x0 0xc340000 0x0 0x10000>; 1297 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1298 resets = <&bpmp TEGRA186_RESET_PWM4>; 1299 reset-names = "pwm"; 1300 status = "disabled"; 1301 #pwm-cells = <2>; 1302 }; 1303 1304 pmc: pmc@c360000 { 1305 compatible = "nvidia,tegra186-pmc"; 1306 reg = <0 0x0c360000 0 0x10000>, 1307 <0 0x0c370000 0 0x10000>, 1308 <0 0x0c380000 0 0x10000>, 1309 <0 0x0c390000 0 0x10000>; 1310 reg-names = "pmc", "wake", "aotag", "scratch"; 1311 1312 #interrupt-cells = <2>; 1313 interrupt-controller; 1314 1315 sdmmc1_1v8: sdmmc1-1v8 { 1316 pins = "sdmmc1-hv"; 1317 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1318 }; 1319 1320 sdmmc1_3v3: sdmmc1-3v3 { 1321 pins = "sdmmc1-hv"; 1322 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1323 }; 1324 1325 sdmmc2_1v8: sdmmc2-1v8 { 1326 pins = "sdmmc2-hv"; 1327 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1328 }; 1329 1330 sdmmc2_3v3: sdmmc2-3v3 { 1331 pins = "sdmmc2-hv"; 1332 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1333 }; 1334 1335 sdmmc3_1v8: sdmmc3-1v8 { 1336 pins = "sdmmc3-hv"; 1337 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1338 }; 1339 1340 sdmmc3_3v3: sdmmc3-3v3 { 1341 pins = "sdmmc3-hv"; 1342 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1343 }; 1344 }; 1345 1346 ccplex@e000000 { 1347 compatible = "nvidia,tegra186-ccplex-cluster"; 1348 reg = <0x0 0x0e000000 0x0 0x400000>; 1349 1350 nvidia,bpmp = <&bpmp>; 1351 }; 1352 1353 pcie@10003000 { 1354 compatible = "nvidia,tegra186-pcie"; 1355 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1356 device_type = "pci"; 1357 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1358 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1359 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1360 reg-names = "pads", "afi", "cs"; 1361 1362 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1363 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1364 interrupt-names = "intr", "msi"; 1365 1366 #interrupt-cells = <1>; 1367 interrupt-map-mask = <0 0 0 0>; 1368 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1369 1370 bus-range = <0x00 0xff>; 1371 #address-cells = <3>; 1372 #size-cells = <2>; 1373 1374 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1375 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1376 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1377 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1378 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1379 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1380 1381 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1382 <&bpmp TEGRA186_CLK_AFI>, 1383 <&bpmp TEGRA186_CLK_PLLE>; 1384 clock-names = "pex", "afi", "pll_e"; 1385 1386 resets = <&bpmp TEGRA186_RESET_PCIE>, 1387 <&bpmp TEGRA186_RESET_AFI>, 1388 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1389 reset-names = "pex", "afi", "pcie_x"; 1390 1391 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1392 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1393 interconnect-names = "dma-mem", "write"; 1394 1395 iommus = <&smmu TEGRA186_SID_AFI>; 1396 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1397 iommu-map-mask = <0x0>; 1398 1399 status = "disabled"; 1400 1401 pci@1,0 { 1402 device_type = "pci"; 1403 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1404 reg = <0x000800 0 0 0 0>; 1405 status = "disabled"; 1406 1407 #address-cells = <3>; 1408 #size-cells = <2>; 1409 ranges; 1410 1411 nvidia,num-lanes = <2>; 1412 }; 1413 1414 pci@2,0 { 1415 device_type = "pci"; 1416 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1417 reg = <0x001000 0 0 0 0>; 1418 status = "disabled"; 1419 1420 #address-cells = <3>; 1421 #size-cells = <2>; 1422 ranges; 1423 1424 nvidia,num-lanes = <1>; 1425 }; 1426 1427 pci@3,0 { 1428 device_type = "pci"; 1429 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1430 reg = <0x001800 0 0 0 0>; 1431 status = "disabled"; 1432 1433 #address-cells = <3>; 1434 #size-cells = <2>; 1435 ranges; 1436 1437 nvidia,num-lanes = <1>; 1438 }; 1439 }; 1440 1441 smmu: iommu@12000000 { 1442 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1443 reg = <0 0x12000000 0 0x800000>; 1444 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1509 stream-match-mask = <0x7f80>; 1510 #global-interrupts = <1>; 1511 #iommu-cells = <1>; 1512 1513 nvidia,memory-controller = <&mc>; 1514 }; 1515 1516 host1x@13e00000 { 1517 compatible = "nvidia,tegra186-host1x"; 1518 reg = <0x0 0x13e00000 0x0 0x10000>, 1519 <0x0 0x13e10000 0x0 0x10000>; 1520 reg-names = "hypervisor", "vm"; 1521 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1523 interrupt-names = "syncpt", "host1x"; 1524 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1525 clock-names = "host1x"; 1526 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1527 reset-names = "host1x"; 1528 1529 #address-cells = <2>; 1530 #size-cells = <2>; 1531 1532 ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>; 1533 1534 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1535 interconnect-names = "dma-mem"; 1536 1537 iommus = <&smmu TEGRA186_SID_HOST1X>; 1538 1539 /* Context isolation domains */ 1540 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1541 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1542 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1543 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1544 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1545 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1546 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1547 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1548 1549 dpaux1: dpaux@15040000 { 1550 compatible = "nvidia,tegra186-dpaux"; 1551 reg = <0x0 0x15040000 0x0 0x10000>; 1552 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1553 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1554 <&bpmp TEGRA186_CLK_PLLDP>; 1555 clock-names = "dpaux", "parent"; 1556 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1557 reset-names = "dpaux"; 1558 status = "disabled"; 1559 1560 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1561 1562 state_dpaux1_aux: pinmux-aux { 1563 groups = "dpaux-io"; 1564 function = "aux"; 1565 }; 1566 1567 state_dpaux1_i2c: pinmux-i2c { 1568 groups = "dpaux-io"; 1569 function = "i2c"; 1570 }; 1571 1572 state_dpaux1_off: pinmux-off { 1573 groups = "dpaux-io"; 1574 function = "off"; 1575 }; 1576 1577 i2c-bus { 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 }; 1581 }; 1582 1583 display-hub@15200000 { 1584 compatible = "nvidia,tegra186-display"; 1585 reg = <0x0 0x15200000 0x0 0x00040000>; 1586 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1587 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1588 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1589 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1590 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1591 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1592 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1593 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1594 "wgrp3", "wgrp4", "wgrp5"; 1595 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1596 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1597 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1598 clock-names = "disp", "dsc", "hub"; 1599 status = "disabled"; 1600 1601 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1602 1603 #address-cells = <2>; 1604 #size-cells = <2>; 1605 1606 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1607 1608 display@15200000 { 1609 compatible = "nvidia,tegra186-dc"; 1610 reg = <0x0 0x15200000 0x0 0x10000>; 1611 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1613 clock-names = "dc"; 1614 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1615 reset-names = "dc"; 1616 1617 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1618 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1619 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1620 interconnect-names = "dma-mem", "read-1"; 1621 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1622 1623 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1624 nvidia,head = <0>; 1625 }; 1626 1627 display@15210000 { 1628 compatible = "nvidia,tegra186-dc"; 1629 reg = <0x0 0x15210000 0x0 0x10000>; 1630 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1632 clock-names = "dc"; 1633 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1634 reset-names = "dc"; 1635 1636 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1637 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1638 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1639 interconnect-names = "dma-mem", "read-1"; 1640 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1641 1642 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1643 nvidia,head = <1>; 1644 }; 1645 1646 display@15220000 { 1647 compatible = "nvidia,tegra186-dc"; 1648 reg = <0x0 0x15220000 0x0 0x10000>; 1649 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1651 clock-names = "dc"; 1652 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1653 reset-names = "dc"; 1654 1655 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1656 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1657 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1658 interconnect-names = "dma-mem", "read-1"; 1659 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1660 1661 nvidia,outputs = <&sor0 &sor1>; 1662 nvidia,head = <2>; 1663 }; 1664 }; 1665 1666 dsia: dsi@15300000 { 1667 compatible = "nvidia,tegra186-dsi"; 1668 reg = <0x0 0x15300000 0x0 0x10000>; 1669 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&bpmp TEGRA186_CLK_DSI>, 1671 <&bpmp TEGRA186_CLK_DSIA_LP>, 1672 <&bpmp TEGRA186_CLK_PLLD>; 1673 clock-names = "dsi", "lp", "parent"; 1674 resets = <&bpmp TEGRA186_RESET_DSI>; 1675 reset-names = "dsi"; 1676 status = "disabled"; 1677 1678 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1679 }; 1680 1681 vic@15340000 { 1682 compatible = "nvidia,tegra186-vic"; 1683 reg = <0x0 0x15340000 0x0 0x40000>; 1684 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1685 clocks = <&bpmp TEGRA186_CLK_VIC>; 1686 clock-names = "vic"; 1687 resets = <&bpmp TEGRA186_RESET_VIC>; 1688 reset-names = "vic"; 1689 1690 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1691 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1692 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1693 interconnect-names = "dma-mem", "write"; 1694 iommus = <&smmu TEGRA186_SID_VIC>; 1695 }; 1696 1697 nvjpg@15380000 { 1698 compatible = "nvidia,tegra186-nvjpg"; 1699 reg = <0x0 0x15380000 0x0 0x40000>; 1700 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1701 clock-names = "nvjpg"; 1702 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1703 reset-names = "nvjpg"; 1704 1705 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1706 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1707 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1708 interconnect-names = "dma-mem", "write"; 1709 iommus = <&smmu TEGRA186_SID_NVJPG>; 1710 }; 1711 1712 dsib: dsi@15400000 { 1713 compatible = "nvidia,tegra186-dsi"; 1714 reg = <0x0 0x15400000 0x0 0x10000>; 1715 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1716 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1717 <&bpmp TEGRA186_CLK_DSIB_LP>, 1718 <&bpmp TEGRA186_CLK_PLLD>; 1719 clock-names = "dsi", "lp", "parent"; 1720 resets = <&bpmp TEGRA186_RESET_DSIB>; 1721 reset-names = "dsi"; 1722 status = "disabled"; 1723 1724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1725 }; 1726 1727 nvdec@15480000 { 1728 compatible = "nvidia,tegra186-nvdec"; 1729 reg = <0x0 0x15480000 0x0 0x40000>; 1730 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1731 clock-names = "nvdec"; 1732 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1733 reset-names = "nvdec"; 1734 1735 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1736 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1737 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1738 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1739 interconnect-names = "dma-mem", "read-1", "write"; 1740 iommus = <&smmu TEGRA186_SID_NVDEC>; 1741 }; 1742 1743 nvenc@154c0000 { 1744 compatible = "nvidia,tegra186-nvenc"; 1745 reg = <0x0 0x154c0000 0x0 0x40000>; 1746 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1747 clock-names = "nvenc"; 1748 resets = <&bpmp TEGRA186_RESET_NVENC>; 1749 reset-names = "nvenc"; 1750 1751 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1752 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1753 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1754 interconnect-names = "dma-mem", "write"; 1755 iommus = <&smmu TEGRA186_SID_NVENC>; 1756 }; 1757 1758 sor0: sor@15540000 { 1759 compatible = "nvidia,tegra186-sor"; 1760 reg = <0x0 0x15540000 0x0 0x10000>; 1761 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1762 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1763 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1764 <&bpmp TEGRA186_CLK_PLLD2>, 1765 <&bpmp TEGRA186_CLK_PLLDP>, 1766 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1767 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1768 clock-names = "sor", "out", "parent", "dp", "safe", 1769 "pad"; 1770 resets = <&bpmp TEGRA186_RESET_SOR0>; 1771 reset-names = "sor"; 1772 pinctrl-0 = <&state_dpaux_aux>; 1773 pinctrl-1 = <&state_dpaux_i2c>; 1774 pinctrl-2 = <&state_dpaux_off>; 1775 pinctrl-names = "aux", "i2c", "off"; 1776 status = "disabled"; 1777 1778 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1779 nvidia,interface = <0>; 1780 }; 1781 1782 sor1: sor@15580000 { 1783 compatible = "nvidia,tegra186-sor"; 1784 reg = <0x0 0x15580000 0x0 0x10000>; 1785 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1786 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1787 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1788 <&bpmp TEGRA186_CLK_PLLD3>, 1789 <&bpmp TEGRA186_CLK_PLLDP>, 1790 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1791 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1792 clock-names = "sor", "out", "parent", "dp", "safe", 1793 "pad"; 1794 resets = <&bpmp TEGRA186_RESET_SOR1>; 1795 reset-names = "sor"; 1796 pinctrl-0 = <&state_dpaux1_aux>; 1797 pinctrl-1 = <&state_dpaux1_i2c>; 1798 pinctrl-2 = <&state_dpaux1_off>; 1799 pinctrl-names = "aux", "i2c", "off"; 1800 status = "disabled"; 1801 1802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1803 nvidia,interface = <1>; 1804 }; 1805 1806 dpaux: dpaux@155c0000 { 1807 compatible = "nvidia,tegra186-dpaux"; 1808 reg = <0x0 0x155c0000 0x0 0x10000>; 1809 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1810 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1811 <&bpmp TEGRA186_CLK_PLLDP>; 1812 clock-names = "dpaux", "parent"; 1813 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1814 reset-names = "dpaux"; 1815 status = "disabled"; 1816 1817 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1818 1819 state_dpaux_aux: pinmux-aux { 1820 groups = "dpaux-io"; 1821 function = "aux"; 1822 }; 1823 1824 state_dpaux_i2c: pinmux-i2c { 1825 groups = "dpaux-io"; 1826 function = "i2c"; 1827 }; 1828 1829 state_dpaux_off: pinmux-off { 1830 groups = "dpaux-io"; 1831 function = "off"; 1832 }; 1833 1834 i2c-bus { 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 }; 1838 }; 1839 1840 padctl@15880000 { 1841 compatible = "nvidia,tegra186-dsi-padctl"; 1842 reg = <0x0 0x15880000 0x0 0x10000>; 1843 resets = <&bpmp TEGRA186_RESET_DSI>; 1844 reset-names = "dsi"; 1845 status = "disabled"; 1846 }; 1847 1848 dsic: dsi@15900000 { 1849 compatible = "nvidia,tegra186-dsi"; 1850 reg = <0x0 0x15900000 0x0 0x10000>; 1851 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1853 <&bpmp TEGRA186_CLK_DSIC_LP>, 1854 <&bpmp TEGRA186_CLK_PLLD>; 1855 clock-names = "dsi", "lp", "parent"; 1856 resets = <&bpmp TEGRA186_RESET_DSIC>; 1857 reset-names = "dsi"; 1858 status = "disabled"; 1859 1860 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1861 }; 1862 1863 dsid: dsi@15940000 { 1864 compatible = "nvidia,tegra186-dsi"; 1865 reg = <0x0 0x15940000 0x0 0x10000>; 1866 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1867 clocks = <&bpmp TEGRA186_CLK_DSID>, 1868 <&bpmp TEGRA186_CLK_DSID_LP>, 1869 <&bpmp TEGRA186_CLK_PLLD>; 1870 clock-names = "dsi", "lp", "parent"; 1871 resets = <&bpmp TEGRA186_RESET_DSID>; 1872 reset-names = "dsi"; 1873 status = "disabled"; 1874 1875 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1876 }; 1877 }; 1878 1879 gpu@17000000 { 1880 compatible = "nvidia,gp10b"; 1881 reg = <0x0 0x17000000 0x0 0x1000000>, 1882 <0x0 0x18000000 0x0 0x1000000>; 1883 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1885 interrupt-names = "stall", "nonstall"; 1886 1887 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1888 <&bpmp TEGRA186_CLK_GPU>; 1889 clock-names = "gpu", "pwr"; 1890 resets = <&bpmp TEGRA186_RESET_GPU>; 1891 reset-names = "gpu"; 1892 status = "disabled"; 1893 1894 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1895 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1896 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1897 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1898 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1899 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1900 }; 1901 1902 sram@30000000 { 1903 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1904 reg = <0x0 0x30000000 0x0 0x50000>; 1905 #address-cells = <1>; 1906 #size-cells = <1>; 1907 ranges = <0x0 0x0 0x30000000 0x50000>; 1908 no-memory-wc; 1909 1910 cpu_bpmp_tx: sram@4e000 { 1911 reg = <0x4e000 0x1000>; 1912 label = "cpu-bpmp-tx"; 1913 pool; 1914 }; 1915 1916 cpu_bpmp_rx: sram@4f000 { 1917 reg = <0x4f000 0x1000>; 1918 label = "cpu-bpmp-rx"; 1919 pool; 1920 }; 1921 }; 1922 1923 bpmp: bpmp { 1924 compatible = "nvidia,tegra186-bpmp"; 1925 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1926 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1927 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1928 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1929 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1930 iommus = <&smmu TEGRA186_SID_BPMP>; 1931 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1932 TEGRA_HSP_DB_MASTER_BPMP>; 1933 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1934 #clock-cells = <1>; 1935 #reset-cells = <1>; 1936 #power-domain-cells = <1>; 1937 1938 bpmp_i2c: i2c { 1939 compatible = "nvidia,tegra186-bpmp-i2c"; 1940 nvidia,bpmp-bus-id = <5>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 status = "disabled"; 1944 }; 1945 1946 bpmp_thermal: thermal { 1947 compatible = "nvidia,tegra186-bpmp-thermal"; 1948 #thermal-sensor-cells = <1>; 1949 }; 1950 }; 1951 1952 cpus { 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 1956 denver_0: cpu@0 { 1957 compatible = "nvidia,tegra186-denver"; 1958 device_type = "cpu"; 1959 i-cache-size = <0x20000>; 1960 i-cache-line-size = <64>; 1961 i-cache-sets = <512>; 1962 d-cache-size = <0x10000>; 1963 d-cache-line-size = <64>; 1964 d-cache-sets = <256>; 1965 next-level-cache = <&L2_DENVER>; 1966 reg = <0x000>; 1967 }; 1968 1969 denver_1: cpu@1 { 1970 compatible = "nvidia,tegra186-denver"; 1971 device_type = "cpu"; 1972 i-cache-size = <0x20000>; 1973 i-cache-line-size = <64>; 1974 i-cache-sets = <512>; 1975 d-cache-size = <0x10000>; 1976 d-cache-line-size = <64>; 1977 d-cache-sets = <256>; 1978 next-level-cache = <&L2_DENVER>; 1979 reg = <0x001>; 1980 }; 1981 1982 ca57_0: cpu@2 { 1983 compatible = "arm,cortex-a57"; 1984 device_type = "cpu"; 1985 i-cache-size = <0xC000>; 1986 i-cache-line-size = <64>; 1987 i-cache-sets = <256>; 1988 d-cache-size = <0x8000>; 1989 d-cache-line-size = <64>; 1990 d-cache-sets = <256>; 1991 next-level-cache = <&L2_A57>; 1992 reg = <0x100>; 1993 }; 1994 1995 ca57_1: cpu@3 { 1996 compatible = "arm,cortex-a57"; 1997 device_type = "cpu"; 1998 i-cache-size = <0xC000>; 1999 i-cache-line-size = <64>; 2000 i-cache-sets = <256>; 2001 d-cache-size = <0x8000>; 2002 d-cache-line-size = <64>; 2003 d-cache-sets = <256>; 2004 next-level-cache = <&L2_A57>; 2005 reg = <0x101>; 2006 }; 2007 2008 ca57_2: cpu@4 { 2009 compatible = "arm,cortex-a57"; 2010 device_type = "cpu"; 2011 i-cache-size = <0xC000>; 2012 i-cache-line-size = <64>; 2013 i-cache-sets = <256>; 2014 d-cache-size = <0x8000>; 2015 d-cache-line-size = <64>; 2016 d-cache-sets = <256>; 2017 next-level-cache = <&L2_A57>; 2018 reg = <0x102>; 2019 }; 2020 2021 ca57_3: cpu@5 { 2022 compatible = "arm,cortex-a57"; 2023 device_type = "cpu"; 2024 i-cache-size = <0xC000>; 2025 i-cache-line-size = <64>; 2026 i-cache-sets = <256>; 2027 d-cache-size = <0x8000>; 2028 d-cache-line-size = <64>; 2029 d-cache-sets = <256>; 2030 next-level-cache = <&L2_A57>; 2031 reg = <0x103>; 2032 }; 2033 2034 L2_DENVER: l2-cache0 { 2035 compatible = "cache"; 2036 cache-unified; 2037 cache-level = <2>; 2038 cache-size = <0x200000>; 2039 cache-line-size = <64>; 2040 cache-sets = <2048>; 2041 }; 2042 2043 L2_A57: l2-cache1 { 2044 compatible = "cache"; 2045 cache-unified; 2046 cache-level = <2>; 2047 cache-size = <0x200000>; 2048 cache-line-size = <64>; 2049 cache-sets = <2048>; 2050 }; 2051 }; 2052 2053 pmu-a57 { 2054 compatible = "arm,cortex-a57-pmu"; 2055 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2059 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2060 }; 2061 2062 pmu-denver { 2063 compatible = "nvidia,denver-pmu"; 2064 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2066 interrupt-affinity = <&denver_0 &denver_1>; 2067 }; 2068 2069 sound { 2070 status = "disabled"; 2071 2072 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2073 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2074 clock-names = "pll_a", "plla_out0"; 2075 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2076 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2077 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2078 assigned-clock-parents = <0>, 2079 <&bpmp TEGRA186_CLK_PLLA>, 2080 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2081 /* 2082 * PLLA supports dynamic ramp. Below initial rate is chosen 2083 * for this to work and oscillate between base rates required 2084 * for 8x and 11.025x sample rate streams. 2085 */ 2086 assigned-clock-rates = <258000000>; 2087 2088 iommus = <&smmu TEGRA186_SID_APE>; 2089 }; 2090 2091 thermal-zones { 2092 /* Cortex-A57 cluster */ 2093 cpu-thermal { 2094 polling-delay = <0>; 2095 polling-delay-passive = <1000>; 2096 2097 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2098 2099 trips { 2100 critical { 2101 temperature = <101000>; 2102 hysteresis = <0>; 2103 type = "critical"; 2104 }; 2105 }; 2106 2107 cooling-maps { 2108 }; 2109 }; 2110 2111 /* Denver cluster */ 2112 aux-thermal { 2113 polling-delay = <0>; 2114 polling-delay-passive = <1000>; 2115 2116 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2117 2118 trips { 2119 critical { 2120 temperature = <101000>; 2121 hysteresis = <0>; 2122 type = "critical"; 2123 }; 2124 }; 2125 2126 cooling-maps { 2127 }; 2128 }; 2129 2130 gpu-thermal { 2131 polling-delay = <0>; 2132 polling-delay-passive = <1000>; 2133 2134 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2135 2136 trips { 2137 critical { 2138 temperature = <101000>; 2139 hysteresis = <0>; 2140 type = "critical"; 2141 }; 2142 }; 2143 2144 cooling-maps { 2145 }; 2146 }; 2147 2148 pll-thermal { 2149 polling-delay = <0>; 2150 polling-delay-passive = <1000>; 2151 2152 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2153 2154 trips { 2155 critical { 2156 temperature = <101000>; 2157 hysteresis = <0>; 2158 type = "critical"; 2159 }; 2160 }; 2161 2162 cooling-maps { 2163 }; 2164 }; 2165 2166 ao-thermal { 2167 polling-delay = <0>; 2168 polling-delay-passive = <1000>; 2169 2170 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2171 2172 trips { 2173 critical { 2174 temperature = <101000>; 2175 hysteresis = <0>; 2176 type = "critical"; 2177 }; 2178 }; 2179 2180 cooling-maps { 2181 }; 2182 }; 2183 }; 2184 2185 timer { 2186 compatible = "arm,armv8-timer"; 2187 interrupts = <GIC_PPI 13 2188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2189 <GIC_PPI 14 2190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 11 2192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2193 <GIC_PPI 10 2194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2195 interrupt-parent = <&gic>; 2196 always-on; 2197 }; 2198}; 2199