1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _NGBE_TYPE_H_ 5 #define _NGBE_TYPE_H_ 6 7 #include <linux/types.h> 8 #include <linux/netdevice.h> 9 10 /************ NGBE_register.h ************/ 11 /* Device IDs */ 12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101 14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102 15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103 16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104 17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105 18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106 19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107 20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108 21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109 22 #define NGBE_DEV_ID_EM_WX1860A1 0x010a 23 #define NGBE_DEV_ID_EM_WX1860A1L 0x010b 24 25 /* Subsystem ID */ 26 #define NGBE_SUBID_M88E1512_SFP 0x0003 27 #define NGBE_SUBID_OCP_CARD 0x0040 28 #define NGBE_SUBID_LY_M88E1512_SFP 0x0050 29 #define NGBE_SUBID_M88E1512_RJ45 0x0051 30 #define NGBE_SUBID_M88E1512_MIX 0x0052 31 #define NGBE_SUBID_YT8521S_SFP 0x0060 32 #define NGBE_SUBID_INTERNAL_YT8521S_SFP 0x0061 33 #define NGBE_SUBID_YT8521S_SFP_GPIO 0x0062 34 #define NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO 0x0064 35 #define NGBE_SUBID_LY_YT8521S_SFP 0x0070 36 #define NGBE_SUBID_RGMII_FPGA 0x0080 37 38 #define NGBE_OEM_MASK 0x00FF 39 40 /**************** EM Registers ****************************/ 41 /* chip control Registers */ 42 #define NGBE_MIS_PRB_CTL 0x10010 43 /* FMGR Registers */ 44 #define NGBE_SPI_ILDR_STATUS 0x10120 45 #define NGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 46 #define NGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 47 48 /* Checksum and EEPROM pointers */ 49 #define NGBE_CALSUM_COMMAND 0xE9 50 #define NGBE_CALSUM_CAP_STATUS 0x10224 51 #define NGBE_EEPROM_VERSION_STORE_REG 0x1022C 52 #define NGBE_SAN_MAC_ADDR_PTR 0x18 53 #define NGBE_DEVICE_CAPS 0x1C 54 #define NGBE_EEPROM_VERSION_L 0x1D 55 #define NGBE_EEPROM_VERSION_H 0x1E 56 57 /* GPIO Registers */ 58 #define NGBE_GPIO_DR 0x14800 59 #define NGBE_GPIO_DDR 0x14804 60 /*GPIO bit */ 61 #define NGBE_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 62 #define NGBE_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 63 #define NGBE_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 64 #define NGBE_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 65 66 /* Extended Interrupt Enable Set */ 67 #define NGBE_PX_MISC_IEN_DEV_RST BIT(10) 68 #define NGBE_PX_MISC_IEN_TIMESYNC BIT(11) 69 #define NGBE_PX_MISC_IEN_ETH_LK BIT(18) 70 #define NGBE_PX_MISC_IEN_INT_ERR BIT(20) 71 #define NGBE_PX_MISC_IC_VF_MBOX BIT(23) 72 #define NGBE_PX_MISC_IEN_GPIO BIT(26) 73 #define NGBE_PX_MISC_IEN_MASK ( \ 74 NGBE_PX_MISC_IEN_DEV_RST | \ 75 NGBE_PX_MISC_IEN_TIMESYNC | \ 76 NGBE_PX_MISC_IEN_ETH_LK | \ 77 NGBE_PX_MISC_IEN_INT_ERR | \ 78 NGBE_PX_MISC_IC_VF_MBOX | \ 79 NGBE_PX_MISC_IEN_GPIO) 80 81 /* Extended Interrupt Cause Read */ 82 #define NGBE_PX_MISC_IC_TIMESYNC BIT(11) /* time sync */ 83 84 #define NGBE_INTR_ALL 0x1FF 85 #define NGBE_INTR_MISC(A) BIT((A)->msix_entry->entry) 86 87 #define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4)) 88 #define NGBE_CFG_LAN_SPEED 0x14440 89 #define NGBE_CFG_PORT_ST 0x14404 90 91 #define NGBE_FW_EEPROM_CHECKSUM_CMD 0xE9 92 #define NGBE_FW_NVM_DATA_OFFSET 3 93 #define NGBE_FW_CMD_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 94 #define NGBE_FW_CMD_ST_PASS 0x80658383 95 #define NGBE_FW_CMD_ST_FAIL 0x70657376 96 97 #define NGBE_MAX_FDIR_INDICES 7 98 #define NGBE_MAX_RSS_INDICES 8 99 100 #define NGBE_MAX_RX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 101 #define NGBE_MAX_TX_QUEUES (NGBE_MAX_FDIR_INDICES + 1) 102 103 #define NGBE_ETH_LENGTH_OF_ADDRESS 6 104 #define NGBE_MAX_MSIX_VECTORS 0x09 105 #define NGBE_RAR_ENTRIES 32 106 #define NGBE_RX_PB_SIZE 42 107 #define NGBE_MC_TBL_SIZE 128 108 #define NGBE_SP_VFT_TBL_SIZE 128 109 #define NGBE_TDB_PB_SZ (20 * 1024) /* 160KB Packet Buffer */ 110 111 /* TX/RX descriptor defines */ 112 #define NGBE_DEFAULT_TXD 512 /* default ring size */ 113 #define NGBE_DEFAULT_TX_WORK 256 114 #define NGBE_MAX_TXD 8192 115 #define NGBE_MIN_TXD 128 116 117 #define NGBE_DEFAULT_RXD 512 /* default ring size */ 118 #define NGBE_DEFAULT_RX_WORK 256 119 #define NGBE_MAX_RXD 8192 120 #define NGBE_MIN_RXD 128 121 122 #define NGBE_MAX_VFS_DRV_LIMIT 7 123 extern char ngbe_driver_name[]; 124 125 void ngbe_down(struct wx *wx); 126 void ngbe_up(struct wx *wx); 127 int ngbe_setup_tc(struct net_device *dev, u8 tc); 128 void ngbe_do_reset(struct net_device *netdev, bool reinit); 129 130 #endif /* _NGBE_TYPE_H_ */ 131