1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #include <linux/gfp.h> 38 #include <linux/hardirq.h> 39 #include <linux/sched.h> 40 41 #include <asm/io.h> 42 43 #include <rdma/ib_pack.h> 44 45 #include "mthca_dev.h" 46 #include "mthca_cmd.h" 47 #include "mthca_memfree.h" 48 49 enum { 50 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE 51 }; 52 53 enum { 54 MTHCA_CQ_ENTRY_SIZE = 0x20 55 }; 56 57 enum { 58 MTHCA_ATOMIC_BYTE_LEN = 8 59 }; 60 61 /* 62 * Must be packed because start is 64 bits but only aligned to 32 bits. 63 */ 64 struct mthca_cq_context { 65 __be32 flags; 66 __be64 start; 67 __be32 logsize_usrpage; 68 __be32 error_eqn; /* Tavor only */ 69 __be32 comp_eqn; 70 __be32 pd; 71 __be32 lkey; 72 __be32 last_notified_index; 73 __be32 solicit_producer_index; 74 __be32 consumer_index; 75 __be32 producer_index; 76 __be32 cqn; 77 __be32 ci_db; /* Arbel only */ 78 __be32 state_db; /* Arbel only */ 79 u32 reserved; 80 } __packed; 81 82 #define MTHCA_CQ_STATUS_OK ( 0 << 28) 83 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28) 84 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28) 85 #define MTHCA_CQ_FLAG_TR ( 1 << 18) 86 #define MTHCA_CQ_FLAG_OI ( 1 << 17) 87 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8) 88 #define MTHCA_CQ_STATE_ARMED ( 1 << 8) 89 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8) 90 #define MTHCA_EQ_STATE_FIRED (10 << 8) 91 92 enum { 93 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe 94 }; 95 96 enum { 97 SYNDROME_LOCAL_LENGTH_ERR = 0x01, 98 SYNDROME_LOCAL_QP_OP_ERR = 0x02, 99 SYNDROME_LOCAL_EEC_OP_ERR = 0x03, 100 SYNDROME_LOCAL_PROT_ERR = 0x04, 101 SYNDROME_WR_FLUSH_ERR = 0x05, 102 SYNDROME_MW_BIND_ERR = 0x06, 103 SYNDROME_BAD_RESP_ERR = 0x10, 104 SYNDROME_LOCAL_ACCESS_ERR = 0x11, 105 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 106 SYNDROME_REMOTE_ACCESS_ERR = 0x13, 107 SYNDROME_REMOTE_OP_ERR = 0x14, 108 SYNDROME_RETRY_EXC_ERR = 0x15, 109 SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 110 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, 111 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, 112 SYNDROME_REMOTE_ABORTED_ERR = 0x22, 113 SYNDROME_INVAL_EECN_ERR = 0x23, 114 SYNDROME_INVAL_EEC_STATE_ERR = 0x24 115 }; 116 117 struct mthca_cqe { 118 __be32 my_qpn; 119 __be32 my_ee; 120 __be32 rqpn; 121 u8 sl_ipok; 122 u8 g_mlpath; 123 __be16 rlid; 124 __be32 imm_etype_pkey_eec; 125 __be32 byte_cnt; 126 __be32 wqe; 127 u8 opcode; 128 u8 is_send; 129 u8 reserved; 130 u8 owner; 131 }; 132 133 struct mthca_err_cqe { 134 __be32 my_qpn; 135 u32 reserved1[3]; 136 u8 syndrome; 137 u8 vendor_err; 138 __be16 db_cnt; 139 u32 reserved2; 140 __be32 wqe; 141 u8 opcode; 142 u8 reserved3[2]; 143 u8 owner; 144 }; 145 146 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 147 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7) 148 149 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24) 150 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24) 151 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) 152 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24) 153 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) 154 155 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) 156 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24) 157 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) 158 159 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf, 160 int entry) 161 { 162 if (buf->is_direct) 163 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE); 164 else 165 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf 166 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE; 167 } 168 169 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry) 170 { 171 return get_cqe_from_buf(&cq->buf, entry); 172 } 173 174 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe) 175 { 176 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; 177 } 178 179 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq) 180 { 181 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); 182 } 183 184 static inline void set_cqe_hw(struct mthca_cqe *cqe) 185 { 186 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW; 187 } 188 189 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr) 190 { 191 __be32 *cqe = cqe_ptr; 192 193 (void) cqe; /* avoid warning if mthca_dbg compiled away... */ 194 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 195 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]), 196 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]), 197 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7])); 198 } 199 200 /* 201 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index 202 * should be correct before calling update_cons_index(). 203 */ 204 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 205 int incr) 206 { 207 if (mthca_is_memfree(dev)) { 208 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 209 wmb(); 210 } else { 211 mthca_write64(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn, incr - 1, 212 dev->kar + MTHCA_CQ_DOORBELL, 213 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 214 } 215 } 216 217 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) 218 { 219 struct mthca_cq *cq; 220 221 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 222 223 if (!cq) { 224 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 225 return; 226 } 227 228 ++cq->arm_sn; 229 230 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 231 } 232 233 void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 234 enum ib_event_type event_type) 235 { 236 struct mthca_cq *cq; 237 struct ib_event event; 238 239 spin_lock(&dev->cq_table.lock); 240 241 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 242 if (cq) 243 ++cq->refcount; 244 245 spin_unlock(&dev->cq_table.lock); 246 247 if (!cq) { 248 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 249 return; 250 } 251 252 event.device = &dev->ib_dev; 253 event.event = event_type; 254 event.element.cq = &cq->ibcq; 255 if (cq->ibcq.event_handler) 256 cq->ibcq.event_handler(&event, cq->ibcq.cq_context); 257 258 spin_lock(&dev->cq_table.lock); 259 if (!--cq->refcount) 260 wake_up(&cq->wait); 261 spin_unlock(&dev->cq_table.lock); 262 } 263 264 static inline int is_recv_cqe(struct mthca_cqe *cqe) 265 { 266 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 267 MTHCA_ERROR_CQE_OPCODE_MASK) 268 return !(cqe->opcode & 0x01); 269 else 270 return !(cqe->is_send & 0x80); 271 } 272 273 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn, 274 struct mthca_srq *srq) 275 { 276 struct mthca_cqe *cqe; 277 u32 prod_index; 278 int i, nfreed = 0; 279 280 spin_lock_irq(&cq->lock); 281 282 /* 283 * First we need to find the current producer index, so we 284 * know where to start cleaning from. It doesn't matter if HW 285 * adds new entries after this loop -- the QP we're worried 286 * about is already in RESET, so the new entries won't come 287 * from our QP and therefore don't need to be checked. 288 */ 289 for (prod_index = cq->cons_index; 290 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); 291 ++prod_index) 292 if (prod_index == cq->cons_index + cq->ibcq.cqe) 293 break; 294 295 if (0) 296 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", 297 qpn, cq->cqn, cq->cons_index, prod_index); 298 299 /* 300 * Now sweep backwards through the CQ, removing CQ entries 301 * that match our QP by copying older entries on top of them. 302 */ 303 while (prod_index != cq->cons_index) { 304 --prod_index; 305 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 306 if (cqe->my_qpn == cpu_to_be32(qpn)) { 307 if (srq && is_recv_cqe(cqe)) 308 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe)); 309 ++nfreed; 310 } else if (nfreed) 311 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), 312 cqe, MTHCA_CQ_ENTRY_SIZE); 313 } 314 315 if (nfreed) { 316 for (i = 0; i < nfreed; ++i) 317 set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe)); 318 wmb(); 319 cq->cons_index += nfreed; 320 update_cons_index(dev, cq, nfreed); 321 } 322 323 spin_unlock_irq(&cq->lock); 324 } 325 326 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq) 327 { 328 int i; 329 330 /* 331 * In Tavor mode, the hardware keeps the consumer and producer 332 * indices mod the CQ size. Since we might be making the CQ 333 * bigger, we need to deal with the case where the producer 334 * index wrapped around before the CQ was resized. 335 */ 336 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) && 337 cq->ibcq.cqe < cq->resize_buf->cqe) { 338 cq->cons_index &= cq->ibcq.cqe; 339 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe))) 340 cq->cons_index -= cq->ibcq.cqe + 1; 341 } 342 343 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) 344 memcpy(get_cqe_from_buf(&cq->resize_buf->buf, 345 i & cq->resize_buf->cqe), 346 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE); 347 } 348 349 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent) 350 { 351 int ret; 352 int i; 353 354 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE, 355 MTHCA_MAX_DIRECT_CQ_SIZE, 356 &buf->queue, &buf->is_direct, 357 &dev->driver_pd, 1, &buf->mr); 358 if (ret) 359 return ret; 360 361 for (i = 0; i < nent; ++i) 362 set_cqe_hw(get_cqe_from_buf(buf, i)); 363 364 return 0; 365 } 366 367 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe) 368 { 369 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue, 370 buf->is_direct, &buf->mr); 371 } 372 373 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq, 374 struct mthca_qp *qp, int wqe_index, int is_send, 375 struct mthca_err_cqe *cqe, 376 struct ib_wc *entry, int *free_cqe) 377 { 378 int dbd; 379 __be32 new_wqe; 380 381 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 382 mthca_dbg(dev, "local QP operation err " 383 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", 384 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe), 385 cq->cqn, cq->cons_index); 386 dump_cqe(dev, cqe); 387 } 388 389 /* 390 * For completions in error, only work request ID, status, vendor error 391 * (and freed resource count for RD) have to be set. 392 */ 393 switch (cqe->syndrome) { 394 case SYNDROME_LOCAL_LENGTH_ERR: 395 entry->status = IB_WC_LOC_LEN_ERR; 396 break; 397 case SYNDROME_LOCAL_QP_OP_ERR: 398 entry->status = IB_WC_LOC_QP_OP_ERR; 399 break; 400 case SYNDROME_LOCAL_EEC_OP_ERR: 401 entry->status = IB_WC_LOC_EEC_OP_ERR; 402 break; 403 case SYNDROME_LOCAL_PROT_ERR: 404 entry->status = IB_WC_LOC_PROT_ERR; 405 break; 406 case SYNDROME_WR_FLUSH_ERR: 407 entry->status = IB_WC_WR_FLUSH_ERR; 408 break; 409 case SYNDROME_MW_BIND_ERR: 410 entry->status = IB_WC_MW_BIND_ERR; 411 break; 412 case SYNDROME_BAD_RESP_ERR: 413 entry->status = IB_WC_BAD_RESP_ERR; 414 break; 415 case SYNDROME_LOCAL_ACCESS_ERR: 416 entry->status = IB_WC_LOC_ACCESS_ERR; 417 break; 418 case SYNDROME_REMOTE_INVAL_REQ_ERR: 419 entry->status = IB_WC_REM_INV_REQ_ERR; 420 break; 421 case SYNDROME_REMOTE_ACCESS_ERR: 422 entry->status = IB_WC_REM_ACCESS_ERR; 423 break; 424 case SYNDROME_REMOTE_OP_ERR: 425 entry->status = IB_WC_REM_OP_ERR; 426 break; 427 case SYNDROME_RETRY_EXC_ERR: 428 entry->status = IB_WC_RETRY_EXC_ERR; 429 break; 430 case SYNDROME_RNR_RETRY_EXC_ERR: 431 entry->status = IB_WC_RNR_RETRY_EXC_ERR; 432 break; 433 case SYNDROME_LOCAL_RDD_VIOL_ERR: 434 entry->status = IB_WC_LOC_RDD_VIOL_ERR; 435 break; 436 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: 437 entry->status = IB_WC_REM_INV_RD_REQ_ERR; 438 break; 439 case SYNDROME_REMOTE_ABORTED_ERR: 440 entry->status = IB_WC_REM_ABORT_ERR; 441 break; 442 case SYNDROME_INVAL_EECN_ERR: 443 entry->status = IB_WC_INV_EECN_ERR; 444 break; 445 case SYNDROME_INVAL_EEC_STATE_ERR: 446 entry->status = IB_WC_INV_EEC_STATE_ERR; 447 break; 448 default: 449 entry->status = IB_WC_GENERAL_ERR; 450 break; 451 } 452 453 entry->vendor_err = cqe->vendor_err; 454 455 /* 456 * Mem-free HCAs always generate one CQE per WQE, even in the 457 * error case, so we don't have to check the doorbell count, etc. 458 */ 459 if (mthca_is_memfree(dev)) 460 return; 461 462 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 463 464 /* 465 * If we're at the end of the WQE chain, or we've used up our 466 * doorbell count, free the CQE. Otherwise just update it for 467 * the next poll operation. 468 */ 469 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd)) 470 return; 471 472 be16_add_cpu(&cqe->db_cnt, -dbd); 473 cqe->wqe = new_wqe; 474 cqe->syndrome = SYNDROME_WR_FLUSH_ERR; 475 476 *free_cqe = 0; 477 } 478 479 static inline int mthca_poll_one(struct mthca_dev *dev, 480 struct mthca_cq *cq, 481 struct mthca_qp **cur_qp, 482 int *freed, 483 struct ib_wc *entry) 484 { 485 struct mthca_wq *wq; 486 struct mthca_cqe *cqe; 487 int wqe_index; 488 int is_error; 489 int is_send; 490 int free_cqe = 1; 491 int err = 0; 492 u16 checksum; 493 494 cqe = next_cqe_sw(cq); 495 if (!cqe) 496 return -EAGAIN; 497 498 /* 499 * Make sure we read CQ entry contents after we've checked the 500 * ownership bit. 501 */ 502 rmb(); 503 504 if (0) { 505 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", 506 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn), 507 be32_to_cpu(cqe->wqe)); 508 dump_cqe(dev, cqe); 509 } 510 511 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 512 MTHCA_ERROR_CQE_OPCODE_MASK; 513 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80; 514 515 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { 516 /* 517 * We do not have to take the QP table lock here, 518 * because CQs will be locked while QPs are removed 519 * from the table. 520 */ 521 *cur_qp = mthca_array_get(&dev->qp_table.qp, 522 be32_to_cpu(cqe->my_qpn) & 523 (dev->limits.num_qps - 1)); 524 if (!*cur_qp) { 525 mthca_warn(dev, "CQ entry for unknown QP %06x\n", 526 be32_to_cpu(cqe->my_qpn) & 0xffffff); 527 err = -EINVAL; 528 goto out; 529 } 530 } 531 532 entry->qp = &(*cur_qp)->ibqp; 533 534 if (is_send) { 535 wq = &(*cur_qp)->sq; 536 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset) 537 >> wq->wqe_shift); 538 entry->wr_id = (*cur_qp)->wrid[wqe_index + 539 (*cur_qp)->rq.max]; 540 } else if ((*cur_qp)->ibqp.srq) { 541 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq); 542 u32 wqe = be32_to_cpu(cqe->wqe); 543 wq = NULL; 544 wqe_index = wqe >> srq->wqe_shift; 545 entry->wr_id = srq->wrid[wqe_index]; 546 mthca_free_srq_wqe(srq, wqe); 547 } else { 548 s32 wqe; 549 wq = &(*cur_qp)->rq; 550 wqe = be32_to_cpu(cqe->wqe); 551 wqe_index = wqe >> wq->wqe_shift; 552 /* 553 * WQE addr == base - 1 might be reported in receive completion 554 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and 555 * Arbel FW 5.1.400. This bug should be fixed in later FW revs. 556 */ 557 if (unlikely(wqe_index < 0)) 558 wqe_index = wq->max - 1; 559 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 560 } 561 562 if (wq) { 563 if (wq->last_comp < wqe_index) 564 wq->tail += wqe_index - wq->last_comp; 565 else 566 wq->tail += wqe_index + wq->max - wq->last_comp; 567 568 wq->last_comp = wqe_index; 569 } 570 571 if (is_error) { 572 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 573 (struct mthca_err_cqe *) cqe, 574 entry, &free_cqe); 575 goto out; 576 } 577 578 if (is_send) { 579 entry->wc_flags = 0; 580 switch (cqe->opcode) { 581 case MTHCA_OPCODE_RDMA_WRITE: 582 entry->opcode = IB_WC_RDMA_WRITE; 583 break; 584 case MTHCA_OPCODE_RDMA_WRITE_IMM: 585 entry->opcode = IB_WC_RDMA_WRITE; 586 entry->wc_flags |= IB_WC_WITH_IMM; 587 break; 588 case MTHCA_OPCODE_SEND: 589 entry->opcode = IB_WC_SEND; 590 break; 591 case MTHCA_OPCODE_SEND_IMM: 592 entry->opcode = IB_WC_SEND; 593 entry->wc_flags |= IB_WC_WITH_IMM; 594 break; 595 case MTHCA_OPCODE_RDMA_READ: 596 entry->opcode = IB_WC_RDMA_READ; 597 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 598 break; 599 case MTHCA_OPCODE_ATOMIC_CS: 600 entry->opcode = IB_WC_COMP_SWAP; 601 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 602 break; 603 case MTHCA_OPCODE_ATOMIC_FA: 604 entry->opcode = IB_WC_FETCH_ADD; 605 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 606 break; 607 default: 608 entry->opcode = 0xFF; 609 break; 610 } 611 } else { 612 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 613 switch (cqe->opcode & 0x1f) { 614 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: 615 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: 616 entry->wc_flags = IB_WC_WITH_IMM; 617 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 618 entry->opcode = IB_WC_RECV; 619 break; 620 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: 621 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: 622 entry->wc_flags = IB_WC_WITH_IMM; 623 entry->ex.imm_data = cqe->imm_etype_pkey_eec; 624 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; 625 break; 626 default: 627 entry->wc_flags = 0; 628 entry->opcode = IB_WC_RECV; 629 break; 630 } 631 entry->slid = be16_to_cpu(cqe->rlid); 632 entry->sl = cqe->sl_ipok >> 4; 633 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 634 entry->dlid_path_bits = cqe->g_mlpath & 0x7f; 635 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 636 entry->wc_flags |= cqe->g_mlpath & 0x80 ? IB_WC_GRH : 0; 637 checksum = (be32_to_cpu(cqe->rqpn) >> 24) | 638 ((be32_to_cpu(cqe->my_ee) >> 16) & 0xff00); 639 entry->wc_flags |= (cqe->sl_ipok & 1 && checksum == 0xffff) ? 640 IB_WC_IP_CSUM_OK : 0; 641 } 642 643 entry->status = IB_WC_SUCCESS; 644 645 out: 646 if (likely(free_cqe)) { 647 set_cqe_hw(cqe); 648 ++(*freed); 649 ++cq->cons_index; 650 } 651 652 return err; 653 } 654 655 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 656 struct ib_wc *entry) 657 { 658 struct mthca_dev *dev = to_mdev(ibcq->device); 659 struct mthca_cq *cq = to_mcq(ibcq); 660 struct mthca_qp *qp = NULL; 661 unsigned long flags; 662 int err = 0; 663 int freed = 0; 664 int npolled; 665 666 spin_lock_irqsave(&cq->lock, flags); 667 668 npolled = 0; 669 repoll: 670 while (npolled < num_entries) { 671 err = mthca_poll_one(dev, cq, &qp, 672 &freed, entry + npolled); 673 if (err) 674 break; 675 ++npolled; 676 } 677 678 if (freed) { 679 wmb(); 680 update_cons_index(dev, cq, freed); 681 } 682 683 /* 684 * If a CQ resize is in progress and we discovered that the 685 * old buffer is empty, then peek in the new buffer, and if 686 * it's not empty, switch to the new buffer and continue 687 * polling there. 688 */ 689 if (unlikely(err == -EAGAIN && cq->resize_buf && 690 cq->resize_buf->state == CQ_RESIZE_READY)) { 691 /* 692 * In Tavor mode, the hardware keeps the producer 693 * index modulo the CQ size. Since we might be making 694 * the CQ bigger, we need to mask our consumer index 695 * using the size of the old CQ buffer before looking 696 * in the new CQ buffer. 697 */ 698 if (!mthca_is_memfree(dev)) 699 cq->cons_index &= cq->ibcq.cqe; 700 701 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, 702 cq->cons_index & cq->resize_buf->cqe))) { 703 struct mthca_cq_buf tbuf; 704 int tcqe; 705 706 tbuf = cq->buf; 707 tcqe = cq->ibcq.cqe; 708 cq->buf = cq->resize_buf->buf; 709 cq->ibcq.cqe = cq->resize_buf->cqe; 710 711 cq->resize_buf->buf = tbuf; 712 cq->resize_buf->cqe = tcqe; 713 cq->resize_buf->state = CQ_RESIZE_SWAPPED; 714 715 goto repoll; 716 } 717 } 718 719 spin_unlock_irqrestore(&cq->lock, flags); 720 721 return err == 0 || err == -EAGAIN ? npolled : err; 722 } 723 724 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 725 { 726 u32 dbhi = ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 727 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 728 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 729 to_mcq(cq)->cqn; 730 731 mthca_write64(dbhi, 0xffffffff, to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 732 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 733 734 return 0; 735 } 736 737 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 738 { 739 struct mthca_cq *cq = to_mcq(ibcq); 740 __be32 db_rec[2]; 741 u32 dbhi; 742 u32 sn = cq->arm_sn & 3; 743 744 db_rec[0] = cpu_to_be32(cq->cons_index); 745 db_rec[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 746 ((flags & IB_CQ_SOLICITED_MASK) == 747 IB_CQ_SOLICITED ? 1 : 2)); 748 749 mthca_write_db_rec(db_rec, cq->arm_db); 750 751 /* 752 * Make sure that the doorbell record in host memory is 753 * written before ringing the doorbell via PCI MMIO. 754 */ 755 wmb(); 756 757 dbhi = (sn << 28) | 758 ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 759 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 760 MTHCA_ARBEL_CQ_DB_REQ_NOT) | cq->cqn; 761 762 mthca_write64(dbhi, cq->cons_index, 763 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 764 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 765 766 return 0; 767 } 768 769 int mthca_init_cq(struct mthca_dev *dev, int nent, 770 struct mthca_ucontext *ctx, u32 pdn, 771 struct mthca_cq *cq) 772 { 773 struct mthca_mailbox *mailbox; 774 struct mthca_cq_context *cq_context; 775 int err = -ENOMEM; 776 777 cq->ibcq.cqe = nent - 1; 778 cq->is_kernel = !ctx; 779 780 cq->cqn = mthca_alloc(&dev->cq_table.alloc); 781 if (cq->cqn == -1) 782 return -ENOMEM; 783 784 if (mthca_is_memfree(dev)) { 785 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn); 786 if (err) 787 goto err_out; 788 789 if (cq->is_kernel) { 790 cq->arm_sn = 1; 791 792 err = -ENOMEM; 793 794 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, 795 cq->cqn, &cq->set_ci_db); 796 if (cq->set_ci_db_index < 0) 797 goto err_out_icm; 798 799 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM, 800 cq->cqn, &cq->arm_db); 801 if (cq->arm_db_index < 0) 802 goto err_out_ci; 803 } 804 } 805 806 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 807 if (IS_ERR(mailbox)) { 808 err = PTR_ERR(mailbox); 809 goto err_out_arm; 810 } 811 812 cq_context = mailbox->buf; 813 814 if (cq->is_kernel) { 815 err = mthca_alloc_cq_buf(dev, &cq->buf, nent); 816 if (err) 817 goto err_out_mailbox; 818 } 819 820 spin_lock_init(&cq->lock); 821 cq->refcount = 1; 822 init_waitqueue_head(&cq->wait); 823 mutex_init(&cq->mutex); 824 825 memset(cq_context, 0, sizeof *cq_context); 826 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 827 MTHCA_CQ_STATE_DISARMED | 828 MTHCA_CQ_FLAG_TR); 829 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 830 if (ctx) 831 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 832 else 833 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 834 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); 835 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn); 836 cq_context->pd = cpu_to_be32(pdn); 837 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); 838 cq_context->cqn = cpu_to_be32(cq->cqn); 839 840 if (mthca_is_memfree(dev)) { 841 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index); 842 cq_context->state_db = cpu_to_be32(cq->arm_db_index); 843 } 844 845 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn); 846 if (err) { 847 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err); 848 goto err_out_free_mr; 849 } 850 851 spin_lock_irq(&dev->cq_table.lock); 852 err = mthca_array_set(&dev->cq_table.cq, 853 cq->cqn & (dev->limits.num_cqs - 1), cq); 854 if (err) { 855 spin_unlock_irq(&dev->cq_table.lock); 856 goto err_out_free_mr; 857 } 858 spin_unlock_irq(&dev->cq_table.lock); 859 860 cq->cons_index = 0; 861 862 mthca_free_mailbox(dev, mailbox); 863 864 return 0; 865 866 err_out_free_mr: 867 if (cq->is_kernel) 868 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 869 870 err_out_mailbox: 871 mthca_free_mailbox(dev, mailbox); 872 873 err_out_arm: 874 if (cq->is_kernel && mthca_is_memfree(dev)) 875 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 876 877 err_out_ci: 878 if (cq->is_kernel && mthca_is_memfree(dev)) 879 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 880 881 err_out_icm: 882 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 883 884 err_out: 885 mthca_free(&dev->cq_table.alloc, cq->cqn); 886 887 return err; 888 } 889 890 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq) 891 { 892 int c; 893 894 spin_lock_irq(&dev->cq_table.lock); 895 c = cq->refcount; 896 spin_unlock_irq(&dev->cq_table.lock); 897 898 return c; 899 } 900 901 void mthca_free_cq(struct mthca_dev *dev, 902 struct mthca_cq *cq) 903 { 904 struct mthca_mailbox *mailbox; 905 int err; 906 907 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 908 if (IS_ERR(mailbox)) { 909 mthca_warn(dev, "No memory for mailbox to free CQ.\n"); 910 return; 911 } 912 913 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn); 914 if (err) 915 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err); 916 917 if (0) { 918 __be32 *ctx = mailbox->buf; 919 int j; 920 921 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 922 cq->cqn, cq->cons_index, 923 cq->is_kernel ? !!next_cqe_sw(cq) : 0); 924 for (j = 0; j < 16; ++j) 925 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j])); 926 } 927 928 spin_lock_irq(&dev->cq_table.lock); 929 mthca_array_clear(&dev->cq_table.cq, 930 cq->cqn & (dev->limits.num_cqs - 1)); 931 --cq->refcount; 932 spin_unlock_irq(&dev->cq_table.lock); 933 934 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) 935 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector); 936 else 937 synchronize_irq(dev->pdev->irq); 938 939 wait_event(cq->wait, !get_cq_refcount(dev, cq)); 940 941 if (cq->is_kernel) { 942 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 943 if (mthca_is_memfree(dev)) { 944 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 945 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 946 } 947 } 948 949 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 950 mthca_free(&dev->cq_table.alloc, cq->cqn); 951 mthca_free_mailbox(dev, mailbox); 952 } 953 954 int mthca_init_cq_table(struct mthca_dev *dev) 955 { 956 int err; 957 958 spin_lock_init(&dev->cq_table.lock); 959 960 err = mthca_alloc_init(&dev->cq_table.alloc, 961 dev->limits.num_cqs, 962 (1 << 24) - 1, 963 dev->limits.reserved_cqs); 964 if (err) 965 return err; 966 967 err = mthca_array_init(&dev->cq_table.cq, 968 dev->limits.num_cqs); 969 if (err) 970 mthca_alloc_cleanup(&dev->cq_table.alloc); 971 972 return err; 973 } 974 975 void mthca_cleanup_cq_table(struct mthca_dev *dev) 976 { 977 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); 978 mthca_alloc_cleanup(&dev->cq_table.alloc); 979 } 980