1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12#include <dt-bindings/memory/mediatek,mt8188-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 15#include <dt-bindings/power/mediatek,mt8188-power.h> 16#include <dt-bindings/reset/mt8188-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8188"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 ethdr0 = ðdr0; 30 gce0 = &gce0; 31 gce1 = &gce1; 32 merge1 = &merge1; 33 merge2 = &merge2; 34 merge3 = &merge3; 35 merge4 = &merge4; 36 merge5 = &merge5; 37 mutex0 = &mutex0; 38 mutex1 = &mutex1; 39 padding0 = &padding0; 40 padding1 = &padding1; 41 padding2 = &padding2; 42 padding3 = &padding3; 43 padding4 = &padding4; 44 padding5 = &padding5; 45 padding6 = &padding6; 46 padding7 = &padding7; 47 vdo1-rdma0 = &vdo1_rdma0; 48 vdo1-rdma1 = &vdo1_rdma1; 49 vdo1-rdma2 = &vdo1_rdma2; 50 vdo1-rdma3 = &vdo1_rdma3; 51 vdo1-rdma4 = &vdo1_rdma4; 52 vdo1-rdma5 = &vdo1_rdma5; 53 vdo1-rdma6 = &vdo1_rdma6; 54 vdo1-rdma7 = &vdo1_rdma7; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x000>; 65 enable-method = "psci"; 66 clock-frequency = <2000000000>; 67 capacity-dmips-mhz = <282>; 68 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 69 i-cache-size = <32768>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <128>; 72 d-cache-size = <32768>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_0>; 76 performance-domains = <&performance 0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x100>; 84 enable-method = "psci"; 85 clock-frequency = <2000000000>; 86 capacity-dmips-mhz = <282>; 87 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 88 i-cache-size = <32768>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <128>; 91 d-cache-size = <32768>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_0>; 95 performance-domains = <&performance 0>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x200>; 103 enable-method = "psci"; 104 clock-frequency = <2000000000>; 105 capacity-dmips-mhz = <282>; 106 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 107 i-cache-size = <32768>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <128>; 110 d-cache-size = <32768>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_0>; 114 performance-domains = <&performance 0>; 115 #cooling-cells = <2>; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x300>; 122 enable-method = "psci"; 123 clock-frequency = <2000000000>; 124 capacity-dmips-mhz = <282>; 125 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 126 i-cache-size = <32768>; 127 i-cache-line-size = <64>; 128 i-cache-sets = <128>; 129 d-cache-size = <32768>; 130 d-cache-line-size = <64>; 131 d-cache-sets = <128>; 132 next-level-cache = <&l2_0>; 133 performance-domains = <&performance 0>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a55"; 140 reg = <0x400>; 141 enable-method = "psci"; 142 clock-frequency = <2000000000>; 143 capacity-dmips-mhz = <282>; 144 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 145 i-cache-size = <32768>; 146 i-cache-line-size = <64>; 147 i-cache-sets = <128>; 148 d-cache-size = <32768>; 149 d-cache-line-size = <64>; 150 d-cache-sets = <128>; 151 next-level-cache = <&l2_0>; 152 performance-domains = <&performance 0>; 153 #cooling-cells = <2>; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a55"; 159 reg = <0x500>; 160 enable-method = "psci"; 161 clock-frequency = <2000000000>; 162 capacity-dmips-mhz = <282>; 163 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 164 i-cache-size = <32768>; 165 i-cache-line-size = <64>; 166 i-cache-sets = <128>; 167 d-cache-size = <32768>; 168 d-cache-line-size = <64>; 169 d-cache-sets = <128>; 170 next-level-cache = <&l2_0>; 171 performance-domains = <&performance 0>; 172 #cooling-cells = <2>; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a78"; 178 reg = <0x600>; 179 enable-method = "psci"; 180 clock-frequency = <2600000000>; 181 capacity-dmips-mhz = <1024>; 182 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 183 i-cache-size = <65536>; 184 i-cache-line-size = <64>; 185 i-cache-sets = <256>; 186 d-cache-size = <65536>; 187 d-cache-line-size = <64>; 188 d-cache-sets = <256>; 189 next-level-cache = <&l2_1>; 190 performance-domains = <&performance 1>; 191 #cooling-cells = <2>; 192 }; 193 194 cpu7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,cortex-a78"; 197 reg = <0x700>; 198 enable-method = "psci"; 199 clock-frequency = <2600000000>; 200 capacity-dmips-mhz = <1024>; 201 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 202 i-cache-size = <65536>; 203 i-cache-line-size = <64>; 204 i-cache-sets = <256>; 205 d-cache-size = <65536>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <256>; 208 next-level-cache = <&l2_1>; 209 performance-domains = <&performance 1>; 210 #cooling-cells = <2>; 211 }; 212 213 cpu-map { 214 cluster0 { 215 core0 { 216 cpu = <&cpu0>; 217 }; 218 219 core1 { 220 cpu = <&cpu1>; 221 }; 222 223 core2 { 224 cpu = <&cpu2>; 225 }; 226 227 core3 { 228 cpu = <&cpu3>; 229 }; 230 231 core4 { 232 cpu = <&cpu4>; 233 }; 234 235 core5 { 236 cpu = <&cpu5>; 237 }; 238 239 core6 { 240 cpu = <&cpu6>; 241 }; 242 243 core7 { 244 cpu = <&cpu7>; 245 }; 246 }; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 252 cpu_off_l: cpu-off-l { 253 compatible = "arm,idle-state"; 254 arm,psci-suspend-param = <0x00010000>; 255 local-timer-stop; 256 entry-latency-us = <50>; 257 exit-latency-us = <95>; 258 min-residency-us = <580>; 259 }; 260 261 cpu_off_b: cpu-off-b { 262 compatible = "arm,idle-state"; 263 arm,psci-suspend-param = <0x00010000>; 264 local-timer-stop; 265 entry-latency-us = <45>; 266 exit-latency-us = <140>; 267 min-residency-us = <740>; 268 }; 269 270 cluster_off_l: cluster-off-l { 271 compatible = "arm,idle-state"; 272 arm,psci-suspend-param = <0x01010010>; 273 local-timer-stop; 274 entry-latency-us = <55>; 275 exit-latency-us = <155>; 276 min-residency-us = <840>; 277 }; 278 279 cluster_off_b: cluster-off-b { 280 compatible = "arm,idle-state"; 281 arm,psci-suspend-param = <0x01010010>; 282 local-timer-stop; 283 entry-latency-us = <50>; 284 exit-latency-us = <200>; 285 min-residency-us = <1000>; 286 }; 287 }; 288 289 l2_0: l2-cache0 { 290 compatible = "cache"; 291 cache-level = <2>; 292 cache-size = <131072>; 293 cache-line-size = <64>; 294 cache-sets = <512>; 295 next-level-cache = <&l3_0>; 296 cache-unified; 297 }; 298 299 l2_1: l2-cache1 { 300 compatible = "cache"; 301 cache-level = <2>; 302 cache-size = <262144>; 303 cache-line-size = <64>; 304 cache-sets = <512>; 305 next-level-cache = <&l3_0>; 306 cache-unified; 307 }; 308 309 l3_0: l3-cache { 310 compatible = "cache"; 311 cache-level = <3>; 312 cache-size = <2097152>; 313 cache-line-size = <64>; 314 cache-sets = <2048>; 315 cache-unified; 316 }; 317 }; 318 319 clk13m: oscillator-13m { 320 compatible = "fixed-clock"; 321 #clock-cells = <0>; 322 clock-frequency = <13000000>; 323 clock-output-names = "clk13m"; 324 }; 325 326 clk26m: oscillator-26m { 327 compatible = "fixed-clock"; 328 #clock-cells = <0>; 329 clock-frequency = <26000000>; 330 clock-output-names = "clk26m"; 331 }; 332 333 clk32k: oscillator-32k { 334 compatible = "fixed-clock"; 335 #clock-cells = <0>; 336 clock-frequency = <32768>; 337 clock-output-names = "clk32k"; 338 }; 339 340 gpu_opp_table: opp-table-gpu { 341 compatible = "operating-points-v2"; 342 opp-shared; 343 344 opp-390000000 { 345 opp-hz = /bits/ 64 <390000000>; 346 opp-microvolt = <575000>; 347 opp-supported-hw = <0xff>; 348 }; 349 opp-431000000 { 350 opp-hz = /bits/ 64 <431000000>; 351 opp-microvolt = <587500>; 352 opp-supported-hw = <0xff>; 353 }; 354 opp-473000000 { 355 opp-hz = /bits/ 64 <473000000>; 356 opp-microvolt = <600000>; 357 opp-supported-hw = <0xff>; 358 }; 359 opp-515000000 { 360 opp-hz = /bits/ 64 <515000000>; 361 opp-microvolt = <612500>; 362 opp-supported-hw = <0xff>; 363 }; 364 opp-556000000 { 365 opp-hz = /bits/ 64 <556000000>; 366 opp-microvolt = <625000>; 367 opp-supported-hw = <0xff>; 368 }; 369 opp-598000000 { 370 opp-hz = /bits/ 64 <598000000>; 371 opp-microvolt = <637500>; 372 opp-supported-hw = <0xff>; 373 }; 374 opp-640000000 { 375 opp-hz = /bits/ 64 <640000000>; 376 opp-microvolt = <650000>; 377 opp-supported-hw = <0xff>; 378 }; 379 opp-670000000 { 380 opp-hz = /bits/ 64 <670000000>; 381 opp-microvolt = <662500>; 382 opp-supported-hw = <0xff>; 383 }; 384 opp-700000000 { 385 opp-hz = /bits/ 64 <700000000>; 386 opp-microvolt = <675000>; 387 opp-supported-hw = <0xff>; 388 }; 389 opp-730000000 { 390 opp-hz = /bits/ 64 <730000000>; 391 opp-microvolt = <687500>; 392 opp-supported-hw = <0xff>; 393 }; 394 opp-760000000 { 395 opp-hz = /bits/ 64 <760000000>; 396 opp-microvolt = <700000>; 397 opp-supported-hw = <0xff>; 398 }; 399 opp-790000000 { 400 opp-hz = /bits/ 64 <790000000>; 401 opp-microvolt = <712500>; 402 opp-supported-hw = <0xff>; 403 }; 404 opp-835000000 { 405 opp-hz = /bits/ 64 <835000000>; 406 opp-microvolt = <731250>; 407 opp-supported-hw = <0xff>; 408 }; 409 opp-880000000 { 410 opp-hz = /bits/ 64 <880000000>; 411 opp-microvolt = <750000>; 412 opp-supported-hw = <0xff>; 413 }; 414 opp-915000000 { 415 opp-hz = /bits/ 64 <915000000>; 416 opp-microvolt = <775000>; 417 opp-supported-hw = <0x8f>; 418 }; 419 opp-915000000-5 { 420 opp-hz = /bits/ 64 <915000000>; 421 opp-microvolt = <762500>; 422 opp-supported-hw = <0x30>; 423 }; 424 opp-915000000-6 { 425 opp-hz = /bits/ 64 <915000000>; 426 opp-microvolt = <750000>; 427 opp-supported-hw = <0x70>; 428 }; 429 opp-950000000 { 430 opp-hz = /bits/ 64 <950000000>; 431 opp-microvolt = <800000>; 432 opp-supported-hw = <0x8f>; 433 }; 434 opp-950000000-5 { 435 opp-hz = /bits/ 64 <950000000>; 436 opp-microvolt = <775000>; 437 opp-supported-hw = <0x30>; 438 }; 439 opp-950000000-6 { 440 opp-hz = /bits/ 64 <950000000>; 441 opp-microvolt = <750000>; 442 opp-supported-hw = <0x70>; 443 }; 444 }; 445 446 pmu-a55 { 447 compatible = "arm,cortex-a55-pmu"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 450 }; 451 452 pmu-a78 { 453 compatible = "arm,cortex-a78-pmu"; 454 interrupt-parent = <&gic>; 455 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 456 }; 457 458 psci { 459 compatible = "arm,psci-1.0"; 460 method = "smc"; 461 }; 462 463 sound: sound { 464 mediatek,platform = <&afe>; 465 status = "disabled"; 466 }; 467 468 thermal_zones: thermal-zones { 469 cpu-little0-thermal { 470 polling-delay = <1000>; 471 polling-delay-passive = <150>; 472 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; 473 474 trips { 475 cpu_little0_alert0: trip-alert0 { 476 temperature = <85000>; 477 hysteresis = <2000>; 478 type = "passive"; 479 }; 480 481 cpu_little0_alert1: trip-alert1 { 482 temperature = <95000>; 483 hysteresis = <2000>; 484 type = "hot"; 485 }; 486 487 cpu_little0_crit: trip-crit { 488 temperature = <100000>; 489 hysteresis = <0>; 490 type = "critical"; 491 }; 492 }; 493 494 cooling-maps { 495 map0 { 496 trip = <&cpu_little0_alert0>; 497 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 498 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 499 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 500 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 501 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 502 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 503 }; 504 }; 505 }; 506 507 cpu-little1-thermal { 508 polling-delay = <1000>; 509 polling-delay-passive = <150>; 510 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; 511 512 trips { 513 cpu_little1_alert0: trip-alert0 { 514 temperature = <85000>; 515 hysteresis = <2000>; 516 type = "passive"; 517 }; 518 519 cpu_little1_alert1: trip-alert1 { 520 temperature = <95000>; 521 hysteresis = <2000>; 522 type = "hot"; 523 }; 524 525 cpu_little1_crit: trip-crit { 526 temperature = <100000>; 527 hysteresis = <0>; 528 type = "critical"; 529 }; 530 }; 531 532 cooling-maps { 533 map0 { 534 trip = <&cpu_little1_alert0>; 535 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 536 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 537 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 541 }; 542 }; 543 }; 544 545 cpu-little2-thermal { 546 polling-delay = <1000>; 547 polling-delay-passive = <150>; 548 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; 549 550 trips { 551 cpu_little2_alert0: trip-alert0 { 552 temperature = <85000>; 553 hysteresis = <2000>; 554 type = "passive"; 555 }; 556 557 cpu_little2_alert1: trip-alert1 { 558 temperature = <95000>; 559 hysteresis = <2000>; 560 type = "hot"; 561 }; 562 563 cpu_little2_crit: trip-crit { 564 temperature = <100000>; 565 hysteresis = <0>; 566 type = "critical"; 567 }; 568 }; 569 570 cooling-maps { 571 map0 { 572 trip = <&cpu_little2_alert0>; 573 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 574 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 575 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 576 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 577 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 578 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 579 }; 580 }; 581 }; 582 583 cpu-little3-thermal { 584 polling-delay = <1000>; 585 polling-delay-passive = <150>; 586 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; 587 588 trips { 589 cpu_little3_alert0: trip-alert0 { 590 temperature = <85000>; 591 hysteresis = <2000>; 592 type = "passive"; 593 }; 594 595 cpu_little3_alert1: trip-alert1 { 596 temperature = <95000>; 597 hysteresis = <2000>; 598 type = "hot"; 599 }; 600 601 cpu_little3_crit: trip-crit { 602 temperature = <100000>; 603 hysteresis = <0>; 604 type = "critical"; 605 }; 606 }; 607 608 cooling-maps { 609 map0 { 610 trip = <&cpu_little3_alert0>; 611 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 612 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 613 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 614 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 615 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 616 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 617 }; 618 }; 619 }; 620 621 cpu-big0-thermal { 622 polling-delay = <1000>; 623 polling-delay-passive = <100>; 624 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; 625 626 trips { 627 cpu_big0_alert0: trip-alert0 { 628 temperature = <85000>; 629 hysteresis = <2000>; 630 type = "passive"; 631 }; 632 633 cpu_big0_alert1: trip-alert1 { 634 temperature = <95000>; 635 hysteresis = <2000>; 636 type = "hot"; 637 }; 638 639 cpu_big0_crit: trip-crit { 640 temperature = <100000>; 641 hysteresis = <0>; 642 type = "critical"; 643 }; 644 }; 645 646 cooling-maps { 647 map0 { 648 trip = <&cpu_big0_alert0>; 649 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 650 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 651 }; 652 }; 653 }; 654 655 cpu-big1-thermal { 656 polling-delay = <1000>; 657 polling-delay-passive = <100>; 658 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; 659 660 trips { 661 cpu_big1_alert0: trip-alert0 { 662 temperature = <85000>; 663 hysteresis = <2000>; 664 type = "passive"; 665 }; 666 667 cpu_big1_alert1: trip-alert1 { 668 temperature = <95000>; 669 hysteresis = <2000>; 670 type = "hot"; 671 }; 672 673 cpu_big1_crit: trip-crit { 674 temperature = <100000>; 675 hysteresis = <0>; 676 type = "critical"; 677 }; 678 }; 679 680 cooling-maps { 681 map0 { 682 trip = <&cpu_big1_alert0>; 683 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 684 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 685 }; 686 }; 687 }; 688 689 apu-thermal { 690 polling-delay = <1000>; 691 polling-delay-passive = <250>; 692 thermal-sensors = <&lvts_ap MT8188_AP_APU>; 693 694 trips { 695 apu_alert0: trip-alert0 { 696 temperature = <85000>; 697 hysteresis = <2000>; 698 type = "passive"; 699 }; 700 701 apu_alert1: trip-alert1 { 702 temperature = <95000>; 703 hysteresis = <2000>; 704 type = "hot"; 705 }; 706 707 apu_crit: trip-crit { 708 temperature = <100000>; 709 hysteresis = <0>; 710 type = "critical"; 711 }; 712 }; 713 }; 714 715 gpu-thermal { 716 polling-delay = <1000>; 717 polling-delay-passive = <250>; 718 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; 719 720 trips { 721 gpu_alert0: trip-alert0 { 722 temperature = <85000>; 723 hysteresis = <2000>; 724 type = "passive"; 725 }; 726 727 gpu_alert1: trip-alert1 { 728 temperature = <95000>; 729 hysteresis = <2000>; 730 type = "hot"; 731 }; 732 733 gpu_crit: trip-crit { 734 temperature = <100000>; 735 hysteresis = <0>; 736 type = "critical"; 737 }; 738 }; 739 740 cooling-maps { 741 map0 { 742 trip = <&gpu_alert0>; 743 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 744 }; 745 }; 746 }; 747 748 gpu1-thermal { 749 polling-delay = <1000>; 750 polling-delay-passive = <250>; 751 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; 752 753 trips { 754 gpu1_alert0: trip-alert0 { 755 temperature = <85000>; 756 hysteresis = <2000>; 757 type = "passive"; 758 }; 759 760 gpu1_alert1: trip-alert1 { 761 temperature = <95000>; 762 hysteresis = <2000>; 763 type = "hot"; 764 }; 765 766 gpu1_crit: trip-crit { 767 temperature = <100000>; 768 hysteresis = <0>; 769 type = "critical"; 770 }; 771 }; 772 773 cooling-maps { 774 map0 { 775 trip = <&gpu1_alert0>; 776 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 777 }; 778 }; 779 }; 780 781 adsp-thermal { 782 polling-delay = <1000>; 783 polling-delay-passive = <250>; 784 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; 785 786 trips { 787 soc_alert0: trip-alert0 { 788 temperature = <85000>; 789 hysteresis = <2000>; 790 type = "passive"; 791 }; 792 793 soc_alert1: trip-alert1 { 794 temperature = <95000>; 795 hysteresis = <2000>; 796 type = "hot"; 797 }; 798 799 soc_crit: trip-crit { 800 temperature = <100000>; 801 hysteresis = <0>; 802 type = "critical"; 803 }; 804 }; 805 }; 806 807 vdo-thermal { 808 polling-delay = <1000>; 809 polling-delay-passive = <250>; 810 thermal-sensors = <&lvts_ap MT8188_AP_VDO>; 811 812 trips { 813 soc1_alert0: trip-alert0 { 814 temperature = <85000>; 815 hysteresis = <2000>; 816 type = "passive"; 817 }; 818 819 soc1_alert1: trip-alert1 { 820 temperature = <95000>; 821 hysteresis = <2000>; 822 type = "hot"; 823 }; 824 825 soc1_crit: trip-crit { 826 temperature = <100000>; 827 hysteresis = <0>; 828 type = "critical"; 829 }; 830 }; 831 }; 832 833 infra-thermal { 834 polling-delay = <1000>; 835 polling-delay-passive = <250>; 836 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; 837 838 trips { 839 soc2_alert0: trip-alert0 { 840 temperature = <85000>; 841 hysteresis = <2000>; 842 type = "passive"; 843 }; 844 845 soc2_alert1: trip-alert1 { 846 temperature = <95000>; 847 hysteresis = <2000>; 848 type = "hot"; 849 }; 850 851 soc2_crit: trip-crit { 852 temperature = <100000>; 853 hysteresis = <0>; 854 type = "critical"; 855 }; 856 }; 857 }; 858 859 cam1-thermal { 860 polling-delay = <1000>; 861 polling-delay-passive = <250>; 862 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; 863 864 trips { 865 cam1_alert0: trip-alert0 { 866 temperature = <85000>; 867 hysteresis = <2000>; 868 type = "passive"; 869 }; 870 871 cam1_alert1: trip-alert1 { 872 temperature = <95000>; 873 hysteresis = <2000>; 874 type = "hot"; 875 }; 876 877 cam1_crit: trip-crit { 878 temperature = <100000>; 879 hysteresis = <0>; 880 type = "critical"; 881 }; 882 }; 883 }; 884 885 cam2-thermal { 886 polling-delay = <1000>; 887 polling-delay-passive = <250>; 888 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; 889 890 trips { 891 cam2_alert0: trip-alert0 { 892 temperature = <85000>; 893 hysteresis = <2000>; 894 type = "passive"; 895 }; 896 897 cam2_alert1: trip-alert1 { 898 temperature = <95000>; 899 hysteresis = <2000>; 900 type = "hot"; 901 }; 902 903 cam2_crit: trip-crit { 904 temperature = <100000>; 905 hysteresis = <0>; 906 type = "critical"; 907 }; 908 }; 909 }; 910 }; 911 912 timer: timer { 913 compatible = "arm,armv8-timer"; 914 interrupt-parent = <&gic>; 915 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 916 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 917 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 918 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 919 clock-frequency = <13000000>; 920 }; 921 922 soc { 923 #address-cells = <2>; 924 #size-cells = <2>; 925 compatible = "simple-bus"; 926 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 927 ranges; 928 929 performance: performance-controller@11bc10 { 930 compatible = "mediatek,cpufreq-hw"; 931 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 932 #performance-domain-cells = <1>; 933 }; 934 935 gic: interrupt-controller@c000000 { 936 compatible = "arm,gic-v3"; 937 #interrupt-cells = <4>; 938 #redistributor-regions = <1>; 939 interrupt-parent = <&gic>; 940 interrupt-controller; 941 reg = <0 0x0c000000 0 0x40000>, 942 <0 0x0c040000 0 0x200000>; 943 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 944 945 ppi-partitions { 946 ppi_cluster0: interrupt-partition-0 { 947 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 948 }; 949 950 ppi_cluster1: interrupt-partition-1 { 951 affinity = <&cpu6 &cpu7>; 952 }; 953 }; 954 }; 955 956 topckgen: syscon@10000000 { 957 compatible = "mediatek,mt8188-topckgen", "syscon"; 958 reg = <0 0x10000000 0 0x1000>; 959 #clock-cells = <1>; 960 }; 961 962 infracfg_ao: syscon@10001000 { 963 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 964 reg = <0 0x10001000 0 0x1000>; 965 #clock-cells = <1>; 966 #reset-cells = <1>; 967 }; 968 969 pericfg: syscon@10003000 { 970 compatible = "mediatek,mt8188-pericfg", "syscon"; 971 reg = <0 0x10003000 0 0x1000>; 972 #clock-cells = <1>; 973 }; 974 975 pio: pinctrl@10005000 { 976 compatible = "mediatek,mt8188-pinctrl"; 977 reg = <0 0x10005000 0 0x1000>, 978 <0 0x11c00000 0 0x1000>, 979 <0 0x11e10000 0 0x1000>, 980 <0 0x11e20000 0 0x1000>, 981 <0 0x11ea0000 0 0x1000>, 982 <0 0x1000b000 0 0x1000>; 983 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 984 "iocfg_lm", "iocfg_rt", "eint"; 985 gpio-controller; 986 #gpio-cells = <2>; 987 gpio-ranges = <&pio 0 0 176>; 988 interrupt-controller; 989 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 990 #interrupt-cells = <2>; 991 }; 992 993 scpsys: syscon@10006000 { 994 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; 995 reg = <0 0x10006000 0 0x1000>; 996 997 /* System Power Manager */ 998 spm: power-controller { 999 compatible = "mediatek,mt8188-power-controller"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 #power-domain-cells = <1>; 1003 1004 /* power domain of the SoC */ 1005 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { 1006 reg = <MT8188_POWER_DOMAIN_MFG0>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 #power-domain-cells = <1>; 1010 1011 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { 1012 reg = <MT8188_POWER_DOMAIN_MFG1>; 1013 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 1014 <&topckgen CLK_TOP_MFG_CORE_TMP>; 1015 clock-names = "mfg", "alt"; 1016 mediatek,infracfg = <&infracfg_ao>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 #power-domain-cells = <1>; 1020 1021 power-domain@MT8188_POWER_DOMAIN_MFG2 { 1022 reg = <MT8188_POWER_DOMAIN_MFG2>; 1023 #power-domain-cells = <0>; 1024 }; 1025 1026 power-domain@MT8188_POWER_DOMAIN_MFG3 { 1027 reg = <MT8188_POWER_DOMAIN_MFG3>; 1028 #power-domain-cells = <0>; 1029 }; 1030 1031 power-domain@MT8188_POWER_DOMAIN_MFG4 { 1032 reg = <MT8188_POWER_DOMAIN_MFG4>; 1033 #power-domain-cells = <0>; 1034 }; 1035 }; 1036 }; 1037 1038 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { 1039 reg = <MT8188_POWER_DOMAIN_VPPSYS0>; 1040 clocks = <&topckgen CLK_TOP_VPP>, 1041 <&topckgen CLK_TOP_CAM>, 1042 <&topckgen CLK_TOP_CCU>, 1043 <&topckgen CLK_TOP_IMG>, 1044 <&topckgen CLK_TOP_VENC>, 1045 <&topckgen CLK_TOP_VDEC>, 1046 <&topckgen CLK_TOP_WPE_VPP>, 1047 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, 1048 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, 1049 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, 1050 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, 1051 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, 1052 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, 1053 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, 1054 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, 1055 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, 1056 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, 1057 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, 1058 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, 1059 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 1060 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 1061 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 1062 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 1063 <&vppsys0 CLK_VPP0_SMI_RSI>, 1064 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1065 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1066 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, 1067 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 1068 clock-names = "top", "cam", "ccu", "img", "venc", 1069 "vdec", "wpe", "cfgck", "cfgxo", 1070 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", 1071 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", 1072 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", 1073 "ss-sram-rdr", "ss-iommu", "ss-imgcam", 1074 "ss-emi", "ss-subcmn-rdr", "ss-rsi", 1075 "ss-cmn-l4", "ss-vdec1", "ss-wpe", 1076 "ss-cvdo-ve1"; 1077 mediatek,infracfg = <&infracfg_ao>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 #power-domain-cells = <1>; 1081 1082 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { 1083 reg = <MT8188_POWER_DOMAIN_VDOSYS0>; 1084 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, 1085 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, 1086 <&vdosys0 CLK_VDO0_SMI_GALS>, 1087 <&vdosys0 CLK_VDO0_SMI_COMMON>, 1088 <&vdosys0 CLK_VDO0_SMI_EMI>, 1089 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 1090 <&vdosys0 CLK_VDO0_SMI_LARB>, 1091 <&vdosys0 CLK_VDO0_SMI_RSI>, 1092 <&vdosys0 CLK_VDO0_APB_BUS>; 1093 clock-names = "cfgck", "cfgxo", "ss-gals", 1094 "ss-cmn", "ss-emi", "ss-iommu", 1095 "ss-larb", "ss-rsi", "ss-bus"; 1096 mediatek,infracfg = <&infracfg_ao>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 #power-domain-cells = <1>; 1100 1101 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { 1102 reg = <MT8188_POWER_DOMAIN_VPPSYS1>; 1103 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, 1104 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, 1105 <&vppsys1 CLK_VPP1_GALS5>, 1106 <&vppsys1 CLK_VPP1_GALS6>, 1107 <&vppsys1 CLK_VPP1_LARB5>, 1108 <&vppsys1 CLK_VPP1_LARB6>; 1109 clock-names = "cfgck", "cfgxo", 1110 "ss-vpp1-g5", "ss-vpp1-g6", 1111 "ss-vpp1-l5", "ss-vpp1-l6"; 1112 mediatek,infracfg = <&infracfg_ao>; 1113 #power-domain-cells = <0>; 1114 }; 1115 1116 power-domain@MT8188_POWER_DOMAIN_VDEC0 { 1117 reg = <MT8188_POWER_DOMAIN_VDEC0>; 1118 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 1119 clock-names = "ss-vdec1-soc-l1"; 1120 mediatek,infracfg = <&infracfg_ao>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 #power-domain-cells = <1>; 1124 1125 power-domain@MT8188_POWER_DOMAIN_VDEC1 { 1126 reg = <MT8188_POWER_DOMAIN_VDEC1>; 1127 clocks = <&vdecsys CLK_VDEC2_LARB1>; 1128 clock-names = "ss-vdec2-l1"; 1129 mediatek,infracfg = <&infracfg_ao>; 1130 #power-domain-cells = <0>; 1131 }; 1132 }; 1133 1134 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { 1135 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; 1136 clocks = <&topckgen CLK_TOP_CAM>, 1137 <&topckgen CLK_TOP_CCU>, 1138 <&topckgen CLK_TOP_CCU_AHB>, 1139 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; 1140 clock-names = "cam", "ccu", "bus", "cfgck"; 1141 mediatek,infracfg = <&infracfg_ao>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 #power-domain-cells = <1>; 1145 1146 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { 1147 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; 1148 clocks = <&camsys CLK_CAM_MAIN_LARB13>, 1149 <&camsys CLK_CAM_MAIN_LARB14>, 1150 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, 1151 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, 1152 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; 1153 clock-names= "ss-cam-l13", "ss-cam-l14", 1154 "ss-cam-mm0", "ss-cam-mm1", 1155 "ss-camsys"; 1156 mediatek,infracfg = <&infracfg_ao>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 #power-domain-cells = <1>; 1160 1161 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { 1162 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; 1163 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, 1164 <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1165 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1166 clock-names = "ss-camb-sub", 1167 "ss-camb-raw", 1168 "ss-camb-yuv"; 1169 #power-domain-cells = <0>; 1170 }; 1171 1172 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { 1173 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; 1174 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, 1175 <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1176 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1177 clock-names = "ss-cama-sub", 1178 "ss-cama-raw", 1179 "ss-cama-yuv"; 1180 #power-domain-cells = <0>; 1181 }; 1182 }; 1183 }; 1184 1185 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { 1186 reg = <MT8188_POWER_DOMAIN_VDOSYS1>; 1187 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, 1188 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, 1189 <&vdosys1 CLK_VDO1_SMI_LARB2>, 1190 <&vdosys1 CLK_VDO1_SMI_LARB3>, 1191 <&vdosys1 CLK_VDO1_GALS>; 1192 clock-names = "cfgck", "cfgxo", "ss-larb2", 1193 "ss-larb3", "ss-gals"; 1194 mediatek,infracfg = <&infracfg_ao>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 #power-domain-cells = <1>; 1198 1199 power-domain@MT8188_POWER_DOMAIN_HDMI_TX { 1200 reg = <MT8188_POWER_DOMAIN_HDMI_TX>; 1201 clocks = <&topckgen CLK_TOP_HDMI_APB>, 1202 <&topckgen CLK_TOP_HDCP_24M>; 1203 clock-names = "bus", "hdcp"; 1204 mediatek,infracfg = <&infracfg_ao>; 1205 #power-domain-cells = <0>; 1206 }; 1207 1208 power-domain@MT8188_POWER_DOMAIN_DP_TX { 1209 reg = <MT8188_POWER_DOMAIN_DP_TX>; 1210 mediatek,infracfg = <&infracfg_ao>; 1211 #power-domain-cells = <0>; 1212 }; 1213 1214 power-domain@MT8188_POWER_DOMAIN_EDP_TX { 1215 reg = <MT8188_POWER_DOMAIN_EDP_TX>; 1216 mediatek,infracfg = <&infracfg_ao>; 1217 #power-domain-cells = <0>; 1218 }; 1219 }; 1220 1221 power-domain@MT8188_POWER_DOMAIN_VENC { 1222 reg = <MT8188_POWER_DOMAIN_VENC>; 1223 clocks = <&vencsys CLK_VENC1_LARB>, 1224 <&vencsys CLK_VENC1_VENC>, 1225 <&vencsys CLK_VENC1_GALS>, 1226 <&vencsys CLK_VENC1_GALS_SRAM>; 1227 clock-names = "ss-ve1-larb", "ss-ve1-core", 1228 "ss-ve1-gals", "ss-ve1-sram"; 1229 mediatek,infracfg = <&infracfg_ao>; 1230 #power-domain-cells = <0>; 1231 }; 1232 1233 power-domain@MT8188_POWER_DOMAIN_WPE { 1234 reg = <MT8188_POWER_DOMAIN_WPE>; 1235 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 1236 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; 1237 clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; 1238 mediatek,infracfg = <&infracfg_ao>; 1239 #power-domain-cells = <0>; 1240 }; 1241 }; 1242 }; 1243 1244 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { 1245 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1246 mediatek,infracfg = <&infracfg_ao>; 1247 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1248 clock-names = "ss-pextp-fmem"; 1249 #power-domain-cells = <0>; 1250 }; 1251 1252 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { 1253 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; 1254 clocks = <&topckgen CLK_TOP_SENINF>, 1255 <&topckgen CLK_TOP_SENINF1>; 1256 clock-names = "seninf0", "seninf1"; 1257 #power-domain-cells = <0>; 1258 }; 1259 1260 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { 1261 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 1262 #power-domain-cells = <0>; 1263 }; 1264 1265 power-domain@MT8188_POWER_DOMAIN_ADSP_AO { 1266 reg = <MT8188_POWER_DOMAIN_ADSP_AO>; 1267 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1268 <&topckgen CLK_TOP_ADSP>; 1269 clock-names = "bus", "main"; 1270 mediatek,infracfg = <&infracfg_ao>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 #power-domain-cells = <1>; 1274 1275 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { 1276 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; 1277 mediatek,infracfg = <&infracfg_ao>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 #power-domain-cells = <1>; 1281 1282 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { 1283 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; 1284 clocks = <&topckgen CLK_TOP_ASM_H>; 1285 clock-names = "asm"; 1286 mediatek,infracfg = <&infracfg_ao>; 1287 #power-domain-cells = <0>; 1288 }; 1289 1290 power-domain@MT8188_POWER_DOMAIN_AUDIO { 1291 reg = <MT8188_POWER_DOMAIN_AUDIO>; 1292 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 1293 <&topckgen CLK_TOP_AUD_INTBUS>, 1294 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; 1295 clock-names = "a1sys", "intbus", "adspck"; 1296 mediatek,infracfg = <&infracfg_ao>; 1297 #power-domain-cells = <0>; 1298 }; 1299 1300 power-domain@MT8188_POWER_DOMAIN_ADSP { 1301 reg = <MT8188_POWER_DOMAIN_ADSP>; 1302 mediatek,infracfg = <&infracfg_ao>; 1303 #power-domain-cells = <0>; 1304 }; 1305 }; 1306 }; 1307 1308 power-domain@MT8188_POWER_DOMAIN_ETHER { 1309 reg = <MT8188_POWER_DOMAIN_ETHER>; 1310 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1311 clock-names = "ethermac"; 1312 mediatek,infracfg = <&infracfg_ao>; 1313 #power-domain-cells = <0>; 1314 }; 1315 }; 1316 }; 1317 1318 watchdog: watchdog@10007000 { 1319 compatible = "mediatek,mt8188-wdt"; 1320 reg = <0 0x10007000 0 0x100>; 1321 mediatek,disable-extrst; 1322 #reset-cells = <1>; 1323 }; 1324 1325 apmixedsys: syscon@1000c000 { 1326 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 1327 reg = <0 0x1000c000 0 0x1000>; 1328 #clock-cells = <1>; 1329 }; 1330 1331 systimer: timer@10017000 { 1332 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 1333 reg = <0 0x10017000 0 0x1000>; 1334 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1335 clocks = <&clk13m>; 1336 }; 1337 1338 pwrap: pwrap@10024000 { 1339 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 1340 reg = <0 0x10024000 0 0x1000>; 1341 reg-names = "pwrap"; 1342 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 1343 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1344 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1345 clock-names = "spi", "wrap"; 1346 }; 1347 1348 spmi: spmi@10027000 { 1349 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; 1350 reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; 1351 reg-names = "pmif", "spmimst"; 1352 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; 1353 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1354 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1355 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1356 <&topckgen CLK_TOP_SPMI_M_MST>; 1357 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1358 }; 1359 1360 infra_iommu: iommu@10315000 { 1361 compatible = "mediatek,mt8188-iommu-infra"; 1362 reg = <0 0x10315000 0 0x1000>; 1363 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; 1364 #iommu-cells = <1>; 1365 }; 1366 1367 gce0: mailbox@10320000 { 1368 compatible = "mediatek,mt8188-gce"; 1369 reg = <0 0x10320000 0 0x4000>; 1370 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 1371 #mbox-cells = <2>; 1372 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1373 }; 1374 1375 gce1: mailbox@10330000 { 1376 compatible = "mediatek,mt8188-gce"; 1377 reg = <0 0x10330000 0 0x4000>; 1378 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 1379 #mbox-cells = <2>; 1380 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 1381 }; 1382 1383 scp: scp@10500000 { 1384 compatible = "mediatek,mt8188-scp"; 1385 reg = <0 0x10500000 0 0x100000>, 1386 <0 0x10720000 0 0xe0000>; 1387 reg-names = "sram", "cfg"; 1388 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1389 }; 1390 1391 afe: audio-controller@10b10000 { 1392 compatible = "mediatek,mt8188-afe"; 1393 reg = <0 0x10b10000 0 0x10000>; 1394 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; 1395 assigned-clock-parents = <&clk26m>; 1396 clocks = <&clk26m>, 1397 <&apmixedsys CLK_APMIXED_APLL1>, 1398 <&apmixedsys CLK_APMIXED_APLL2>, 1399 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1400 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1401 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1402 <&topckgen CLK_TOP_APLL12_CK_DIV3>, 1403 <&topckgen CLK_TOP_APLL12_CK_DIV9>, 1404 <&topckgen CLK_TOP_A1SYS_HP>, 1405 <&topckgen CLK_TOP_AUD_INTBUS>, 1406 <&topckgen CLK_TOP_AUDIO_H>, 1407 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1408 <&topckgen CLK_TOP_DPTX>, 1409 <&topckgen CLK_TOP_I2SO1>, 1410 <&topckgen CLK_TOP_I2SO2>, 1411 <&topckgen CLK_TOP_I2SI1>, 1412 <&topckgen CLK_TOP_I2SI2>, 1413 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, 1414 <&topckgen CLK_TOP_APLL1_D4>, 1415 <&topckgen CLK_TOP_APLL2_D4>, 1416 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1417 <&topckgen CLK_TOP_A2SYS>, 1418 <&topckgen CLK_TOP_AUD_IEC>; 1419 clock-names = "clk26m", 1420 "apll1", 1421 "apll2", 1422 "apll12_div0", 1423 "apll12_div1", 1424 "apll12_div2", 1425 "apll12_div3", 1426 "apll12_div9", 1427 "top_a1sys_hp", 1428 "top_aud_intbus", 1429 "top_audio_h", 1430 "top_audio_local_bus", 1431 "top_dptx", 1432 "top_i2so1", 1433 "top_i2so2", 1434 "top_i2si1", 1435 "top_i2si2", 1436 "adsp_audio_26m", 1437 "apll1_d4", 1438 "apll2_d4", 1439 "apll12_div4", 1440 "top_a2sys", 1441 "top_aud_iec"; 1442 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 1443 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; 1444 resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; 1445 reset-names = "audiosys"; 1446 mediatek,infracfg = <&infracfg_ao>; 1447 mediatek,topckgen = <&topckgen>; 1448 status = "disabled"; 1449 }; 1450 1451 adsp: adsp@10b80000 { 1452 compatible = "mediatek,mt8188-dsp"; 1453 reg = <0 0x10b80000 0 0x2000>, 1454 <0 0x10d00000 0 0x80000>, 1455 <0 0x10b8b000 0 0x100>, 1456 <0 0x10b8f000 0 0x1000>; 1457 reg-names = "cfg", "sram", "sec", "bus"; 1458 assigned-clocks = <&topckgen CLK_TOP_ADSP>; 1459 clocks = <&topckgen CLK_TOP_ADSP>, 1460 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 1461 clock-names = "audiodsp", "adsp_bus"; 1462 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1463 mbox-names = "rx", "tx"; 1464 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; 1465 status = "disabled"; 1466 }; 1467 1468 adsp_mailbox0: mailbox@10b86100 { 1469 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1470 reg = <0 0x10b86100 0 0x1000>; 1471 interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; 1472 #mbox-cells = <0>; 1473 }; 1474 1475 adsp_mailbox1: mailbox@10b87100 { 1476 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1477 reg = <0 0x10b87100 0 0x1000>; 1478 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; 1479 #mbox-cells = <0>; 1480 }; 1481 1482 adsp_audio26m: clock-controller@10b91100 { 1483 compatible = "mediatek,mt8188-adsp-audio26m"; 1484 reg = <0 0x10b91100 0 0x100>; 1485 #clock-cells = <1>; 1486 }; 1487 1488 uart0: serial@11001100 { 1489 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1490 reg = <0 0x11001100 0 0x100>; 1491 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1492 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1493 clock-names = "baud", "bus"; 1494 status = "disabled"; 1495 }; 1496 1497 uart1: serial@11001200 { 1498 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1499 reg = <0 0x11001200 0 0x100>; 1500 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1501 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1502 clock-names = "baud", "bus"; 1503 status = "disabled"; 1504 }; 1505 1506 uart2: serial@11001300 { 1507 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1508 reg = <0 0x11001300 0 0x100>; 1509 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1510 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1511 clock-names = "baud", "bus"; 1512 status = "disabled"; 1513 }; 1514 1515 uart3: serial@11001400 { 1516 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1517 reg = <0 0x11001400 0 0x100>; 1518 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1519 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1520 clock-names = "baud", "bus"; 1521 status = "disabled"; 1522 }; 1523 1524 auxadc: adc@11002000 { 1525 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 1526 reg = <0 0x11002000 0 0x1000>; 1527 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1528 clock-names = "main"; 1529 #io-channel-cells = <1>; 1530 status = "disabled"; 1531 }; 1532 1533 pericfg_ao: syscon@11003000 { 1534 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 1535 reg = <0 0x11003000 0 0x1000>; 1536 #clock-cells = <1>; 1537 }; 1538 1539 spi0: spi@1100a000 { 1540 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 reg = <0 0x1100a000 0 0x1000>; 1544 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1545 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1546 <&topckgen CLK_TOP_SPI>, 1547 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1548 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1549 status = "disabled"; 1550 }; 1551 1552 lvts_ap: thermal-sensor@1100b000 { 1553 compatible = "mediatek,mt8188-lvts-ap"; 1554 reg = <0 0x1100b000 0 0xc00>; 1555 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>; 1556 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1557 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; 1558 nvmem-cells = <&lvts_efuse_data1>; 1559 nvmem-cell-names = "lvts-calib-data-1"; 1560 #thermal-sensor-cells = <1>; 1561 }; 1562 1563 disp_pwm0: pwm@1100e000 { 1564 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1565 reg = <0 0x1100e000 0 0x1000>; 1566 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1567 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1568 clock-names = "main", "mm"; 1569 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1570 #pwm-cells = <2>; 1571 status = "disabled"; 1572 }; 1573 1574 disp_pwm1: pwm@1100f000 { 1575 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1576 reg = <0 0x1100f000 0 0x1000>; 1577 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1578 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1579 clock-names = "main", "mm"; 1580 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1581 #pwm-cells = <2>; 1582 status = "disabled"; 1583 }; 1584 1585 spi1: spi@11010000 { 1586 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 reg = <0 0x11010000 0 0x1000>; 1590 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1591 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1592 <&topckgen CLK_TOP_SPI>, 1593 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1594 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1595 status = "disabled"; 1596 }; 1597 1598 spi2: spi@11012000 { 1599 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 reg = <0 0x11012000 0 0x1000>; 1603 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1604 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1605 <&topckgen CLK_TOP_SPI>, 1606 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1607 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1608 status = "disabled"; 1609 }; 1610 1611 spi3: spi@11013000 { 1612 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 reg = <0 0x11013000 0 0x1000>; 1616 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1617 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1618 <&topckgen CLK_TOP_SPI>, 1619 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1620 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1621 status = "disabled"; 1622 }; 1623 1624 spi4: spi@11018000 { 1625 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 reg = <0 0x11018000 0 0x1000>; 1629 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1630 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1631 <&topckgen CLK_TOP_SPI>, 1632 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1633 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1634 status = "disabled"; 1635 }; 1636 1637 spi5: spi@11019000 { 1638 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 reg = <0 0x11019000 0 0x1000>; 1642 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1643 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1644 <&topckgen CLK_TOP_SPI>, 1645 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1646 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1647 status = "disabled"; 1648 }; 1649 1650 eth: ethernet@11021000 { 1651 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", 1652 "snps,dwmac-5.10a"; 1653 reg = <0 0x11021000 0 0x4000>; 1654 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1655 interrupt-names = "macirq"; 1656 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1657 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1658 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1659 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1660 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1661 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1662 clock-names = "axi", "apb", "mac_main", "ptp_ref", 1663 "rmii_internal", "mac_cg"; 1664 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1665 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1666 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1667 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1668 <&topckgen CLK_TOP_ETHPLL_D8>, 1669 <&topckgen CLK_TOP_ETHPLL_D10>; 1670 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; 1671 mediatek,pericfg = <&infracfg_ao>; 1672 snps,axi-config = <&stmmac_axi_setup>; 1673 snps,mtl-rx-config = <&mtl_rx_setup>; 1674 snps,mtl-tx-config = <&mtl_tx_setup>; 1675 snps,txpbl = <16>; 1676 snps,rxpbl = <16>; 1677 snps,clk-csr = <0>; 1678 status = "disabled"; 1679 1680 eth_mdio: mdio { 1681 compatible = "snps,dwmac-mdio"; 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 }; 1685 1686 stmmac_axi_setup: stmmac-axi-config { 1687 snps,blen = <0 0 0 0 16 8 4>; 1688 snps,rd_osr_lmt = <0x7>; 1689 snps,wr_osr_lmt = <0x7>; 1690 }; 1691 1692 mtl_rx_setup: rx-queues-config { 1693 snps,rx-queues-to-use = <4>; 1694 snps,rx-sched-sp; 1695 1696 queue0 { 1697 snps,dcb-algorithm; 1698 snps,map-to-dma-channel = <0x0>; 1699 }; 1700 1701 queue1 { 1702 snps,dcb-algorithm; 1703 snps,map-to-dma-channel = <0x0>; 1704 }; 1705 1706 queue2 { 1707 snps,dcb-algorithm; 1708 snps,map-to-dma-channel = <0x0>; 1709 }; 1710 1711 queue3 { 1712 snps,dcb-algorithm; 1713 snps,map-to-dma-channel = <0x0>; 1714 }; 1715 }; 1716 1717 mtl_tx_setup: tx-queues-config { 1718 snps,tx-queues-to-use = <4>; 1719 snps,tx-sched-wrr; 1720 1721 queue0 { 1722 snps,dcb-algorithm; 1723 snps,priority = <0x0>; 1724 snps,weight = <0x10>; 1725 }; 1726 1727 queue1 { 1728 snps,dcb-algorithm; 1729 snps,priority = <0x1>; 1730 snps,weight = <0x11>; 1731 }; 1732 1733 queue2 { 1734 snps,dcb-algorithm; 1735 snps,priority = <0x2>; 1736 snps,weight = <0x12>; 1737 }; 1738 1739 queue3 { 1740 snps,dcb-algorithm; 1741 snps,priority = <0x3>; 1742 snps,weight = <0x13>; 1743 }; 1744 }; 1745 }; 1746 1747 xhci1: usb@11200000 { 1748 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1749 reg = <0 0x11200000 0 0x1000>, 1750 <0 0x11203e00 0 0x0100>; 1751 reg-names = "mac", "ippc"; 1752 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1753 phys = <&u2port1 PHY_TYPE_USB2>, 1754 <&u3port1 PHY_TYPE_USB3>; 1755 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1756 <&topckgen CLK_TOP_SSUSB_XHCI>; 1757 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1758 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1759 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 1760 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 1761 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1762 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1763 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 1764 wakeup-source; 1765 status = "disabled"; 1766 }; 1767 1768 mmc0: mmc@11230000 { 1769 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1770 reg = <0 0x11230000 0 0x10000>, 1771 <0 0x11f50000 0 0x1000>; 1772 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1773 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1774 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1775 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1776 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 1777 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 1778 status = "disabled"; 1779 }; 1780 1781 mmc1: mmc@11240000 { 1782 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1783 reg = <0 0x11240000 0 0x1000>, 1784 <0 0x11eb0000 0 0x1000>; 1785 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1786 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1787 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1788 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1789 clock-names = "source", "hclk", "source_cg"; 1790 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1791 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1792 status = "disabled"; 1793 }; 1794 1795 lvts_mcu: thermal-sensor@11278000 { 1796 compatible = "mediatek,mt8188-lvts-mcu"; 1797 reg = <0 0x11278000 0 0x1000>; 1798 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 1799 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1800 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; 1801 nvmem-cells = <&lvts_efuse_data1>; 1802 nvmem-cell-names = "lvts-calib-data-1"; 1803 #thermal-sensor-cells = <1>; 1804 }; 1805 1806 i2c0: i2c@11280000 { 1807 compatible = "mediatek,mt8188-i2c"; 1808 reg = <0 0x11280000 0 0x1000>, 1809 <0 0x10220080 0 0x80>; 1810 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 1811 clock-div = <1>; 1812 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 1813 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1814 clock-names = "main", "dma"; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 status = "disabled"; 1818 }; 1819 1820 i2c2: i2c@11281000 { 1821 compatible = "mediatek,mt8188-i2c"; 1822 reg = <0 0x11281000 0 0x1000>, 1823 <0 0x10220180 0 0x80>; 1824 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1825 clock-div = <1>; 1826 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 1827 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1828 clock-names = "main", "dma"; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 status = "disabled"; 1832 }; 1833 1834 i2c3: i2c@11282000 { 1835 compatible = "mediatek,mt8188-i2c"; 1836 reg = <0 0x11282000 0 0x1000>, 1837 <0 0x10220280 0 0x80>; 1838 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1839 clock-div = <1>; 1840 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 1841 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1842 clock-names = "main", "dma"; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 }; 1847 1848 imp_iic_wrap_c: clock-controller@11283000 { 1849 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 1850 reg = <0 0x11283000 0 0x1000>; 1851 #clock-cells = <1>; 1852 }; 1853 1854 xhci2: usb@112a0000 { 1855 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1856 reg = <0 0x112a0000 0 0x1000>, 1857 <0 0x112a3e00 0 0x0100>; 1858 reg-names = "mac", "ippc"; 1859 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1860 phys = <&u2port2 PHY_TYPE_USB2>; 1861 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>, 1862 <&topckgen CLK_TOP_USB_TOP_3P>; 1863 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1864 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1865 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1866 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 1867 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1868 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1869 status = "disabled"; 1870 }; 1871 1872 xhci0: usb@112b0000 { 1873 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1874 reg = <0 0x112b0000 0 0x1000>, 1875 <0 0x112b3e00 0 0x0100>; 1876 reg-names = "mac", "ippc"; 1877 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1878 phys = <&u2port0 PHY_TYPE_USB2>; 1879 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>, 1880 <&topckgen CLK_TOP_USB_TOP_2P>; 1881 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1882 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1883 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1884 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 1885 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1886 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1887 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 1888 wakeup-source; 1889 status = "disabled"; 1890 }; 1891 1892 pcie: pcie@112f0000 { 1893 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; 1894 reg = <0 0x112f0000 0 0x2000>; 1895 reg-names = "pcie-mac"; 1896 ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; 1897 bus-range = <0 0xff>; 1898 device_type = "pci"; 1899 linux,pci-domain = <0>; 1900 #address-cells = <3>; 1901 #size-cells = <2>; 1902 1903 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1904 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1905 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1906 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1907 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1908 <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1909 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", 1910 "peri_26m", "peri_mem"; 1911 1912 #interrupt-cells = <1>; 1913 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1914 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1915 <0 0 0 2 &pcie_intc 1>, 1916 <0 0 0 3 &pcie_intc 2>, 1917 <0 0 0 4 &pcie_intc 3>; 1918 interrupt-map-mask = <0 0 0 7>; 1919 1920 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; 1921 iommu-map-mask = <0>; 1922 1923 phys = <&pcieport PHY_TYPE_PCIE>; 1924 phy-names = "pcie-phy"; 1925 1926 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1927 1928 resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; 1929 reset-names = "mac"; 1930 1931 status = "disabled"; 1932 1933 pcie_intc: interrupt-controller { 1934 #address-cells = <0>; 1935 #interrupt-cells = <1>; 1936 interrupt-controller; 1937 }; 1938 }; 1939 1940 nor_flash: spi@1132c000 { 1941 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 1942 reg = <0 0x1132c000 0 0x1000>; 1943 clocks = <&topckgen CLK_TOP_SPINOR>, 1944 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 1945 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1946 clock-names = "spi", "sf", "axi"; 1947 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1948 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 status = "disabled"; 1952 }; 1953 1954 pciephy: t-phy@11c20700 { 1955 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 1956 ranges = <0 0 0x11c20700 0x700>; 1957 #address-cells = <1>; 1958 #size-cells = <1>; 1959 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 1960 status = "disabled"; 1961 1962 pcieport: pcie-phy@0 { 1963 reg = <0 0x700>; 1964 clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; 1965 clock-names = "ref"; 1966 #phy-cells = <1>; 1967 }; 1968 }; 1969 1970 mipi_tx_config0: dsi-phy@11c80000 { 1971 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 1972 reg = <0 0x11c80000 0 0x1000>; 1973 clocks = <&clk26m>; 1974 clock-output-names = "mipi_tx0_pll"; 1975 #clock-cells = <0>; 1976 #phy-cells = <0>; 1977 status = "disabled"; 1978 }; 1979 1980 mipi_tx_config1: dsi-phy@11c90000 { 1981 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 1982 reg = <0 0x11c90000 0 0x1000>; 1983 clocks = <&clk26m>; 1984 clock-output-names = "mipi_tx0_pll"; 1985 #clock-cells = <0>; 1986 #phy-cells = <0>; 1987 status = "disabled"; 1988 }; 1989 1990 i2c1: i2c@11e00000 { 1991 compatible = "mediatek,mt8188-i2c"; 1992 reg = <0 0x11e00000 0 0x1000>, 1993 <0 0x10220100 0 0x80>; 1994 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1995 clock-div = <1>; 1996 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 1997 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1998 clock-names = "main", "dma"; 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 status = "disabled"; 2002 }; 2003 2004 i2c4: i2c@11e01000 { 2005 compatible = "mediatek,mt8188-i2c"; 2006 reg = <0 0x11e01000 0 0x1000>, 2007 <0 0x10220380 0 0x80>; 2008 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 2009 clock-div = <1>; 2010 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 2011 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2012 clock-names = "main", "dma"; 2013 #address-cells = <1>; 2014 #size-cells = <0>; 2015 status = "disabled"; 2016 }; 2017 2018 imp_iic_wrap_w: clock-controller@11e02000 { 2019 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 2020 reg = <0 0x11e02000 0 0x1000>; 2021 #clock-cells = <1>; 2022 }; 2023 2024 u3phy0: t-phy@11e30000 { 2025 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2026 #address-cells = <1>; 2027 #size-cells = <1>; 2028 ranges = <0x0 0x0 0x11e30000 0x1000>; 2029 status = "disabled"; 2030 2031 u2port0: usb-phy@0 { 2032 reg = <0x0 0x700>; 2033 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 2034 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2035 clock-names = "ref", "da_ref"; 2036 #phy-cells = <1>; 2037 }; 2038 }; 2039 2040 u3phy1: t-phy@11e40000 { 2041 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2042 #address-cells = <1>; 2043 #size-cells = <1>; 2044 ranges = <0x0 0x0 0x11e40000 0x1000>; 2045 status = "disabled"; 2046 2047 u2port1: usb-phy@0 { 2048 reg = <0x0 0x700>; 2049 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 2050 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2051 clock-names = "ref", "da_ref"; 2052 #phy-cells = <1>; 2053 }; 2054 2055 u3port1: usb-phy@700 { 2056 reg = <0x700 0x700>; 2057 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 2058 <&clk26m>; 2059 clock-names = "ref", "da_ref"; 2060 #phy-cells = <1>; 2061 }; 2062 }; 2063 2064 u3phy2: t-phy@11e80000 { 2065 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2066 #address-cells = <1>; 2067 #size-cells = <1>; 2068 ranges = <0x0 0x0 0x11e80000 0x1000>; 2069 status = "disabled"; 2070 2071 u2port2: usb-phy@0 { 2072 reg = <0x0 0x700>; 2073 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 2074 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2075 clock-names = "ref", "da_ref"; 2076 #phy-cells = <1>; 2077 }; 2078 }; 2079 2080 i2c5: i2c@11ec0000 { 2081 compatible = "mediatek,mt8188-i2c"; 2082 reg = <0 0x11ec0000 0 0x1000>, 2083 <0 0x10220480 0 0x80>; 2084 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 2085 clock-div = <1>; 2086 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 2087 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2088 clock-names = "main", "dma"; 2089 #address-cells = <1>; 2090 #size-cells = <0>; 2091 status = "disabled"; 2092 }; 2093 2094 i2c6: i2c@11ec1000 { 2095 compatible = "mediatek,mt8188-i2c"; 2096 reg = <0 0x11ec1000 0 0x1000>, 2097 <0 0x10220600 0 0x80>; 2098 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 2099 clock-div = <1>; 2100 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 2101 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2102 clock-names = "main", "dma"; 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 status = "disabled"; 2106 }; 2107 2108 imp_iic_wrap_en: clock-controller@11ec2000 { 2109 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 2110 reg = <0 0x11ec2000 0 0x1000>; 2111 #clock-cells = <1>; 2112 }; 2113 2114 efuse: efuse@11f20000 { 2115 compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; 2116 reg = <0 0x11f20000 0 0x1000>; 2117 #address-cells = <1>; 2118 #size-cells = <1>; 2119 2120 dp_calib_data: dp-calib@1a0 { 2121 reg = <0x1a0 0xc>; 2122 }; 2123 2124 lvts_efuse_data1: lvts1-calib@1ac { 2125 reg = <0x1ac 0x40>; 2126 }; 2127 2128 socinfo-data1@7a0 { 2129 reg = <0x7a0 0x4>; 2130 }; 2131 2132 socinfo-data2@7e0 { 2133 reg = <0x7e0 0x4>; 2134 }; 2135 }; 2136 2137 gpu: gpu@13000000 { 2138 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; 2139 reg = <0 0x13000000 0 0x4000>; 2140 2141 clocks = <&mfgcfg CLK_MFGCFG_BG3D>; 2142 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 2143 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, 2144 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; 2145 interrupt-names = "job", "mmu", "gpu"; 2146 operating-points-v2 = <&gpu_opp_table>; 2147 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, 2148 <&spm MT8188_POWER_DOMAIN_MFG3>, 2149 <&spm MT8188_POWER_DOMAIN_MFG4>; 2150 power-domain-names = "core0", "core1", "core2"; 2151 #cooling-cells = <2>; 2152 status = "disabled"; 2153 }; 2154 2155 mfgcfg: clock-controller@13fbf000 { 2156 compatible = "mediatek,mt8188-mfgcfg"; 2157 reg = <0 0x13fbf000 0 0x1000>; 2158 #clock-cells = <1>; 2159 }; 2160 2161 vppsys0: syscon@14000000 { 2162 compatible = "mediatek,mt8188-vppsys0", "syscon"; 2163 reg = <0 0x14000000 0 0x1000>; 2164 #clock-cells = <1>; 2165 }; 2166 2167 vpp_smi_common: smi@14012000 { 2168 compatible = "mediatek,mt8188-smi-common-vpp"; 2169 reg = <0 0x14012000 0 0x1000>; 2170 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2171 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; 2172 clock-names = "apb", "smi"; 2173 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2174 }; 2175 2176 larb4: smi@14013000 { 2177 compatible = "mediatek,mt8188-smi-larb"; 2178 reg = <0 0x14013000 0 0x1000>; 2179 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2180 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2181 clock-names = "apb", "smi"; 2182 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2183 mediatek,larb-id = <SMI_L4_ID>; 2184 mediatek,smi = <&vpp_smi_common>; 2185 }; 2186 2187 vpp_iommu: iommu@14018000 { 2188 compatible = "mediatek,mt8188-iommu-vpp"; 2189 reg = <0 0x14018000 0 0x5000>; 2190 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2191 clock-names = "bclk"; 2192 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2193 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2194 #iommu-cells = <1>; 2195 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; 2196 }; 2197 2198 wpesys: clock-controller@14e00000 { 2199 compatible = "mediatek,mt8188-wpesys"; 2200 reg = <0 0x14e00000 0 0x1000>; 2201 #clock-cells = <1>; 2202 }; 2203 2204 wpesys_vpp0: clock-controller@14e02000 { 2205 compatible = "mediatek,mt8188-wpesys-vpp0"; 2206 reg = <0 0x14e02000 0 0x1000>; 2207 #clock-cells = <1>; 2208 }; 2209 2210 larb7: smi@14e04000 { 2211 compatible = "mediatek,mt8188-smi-larb"; 2212 reg = <0 0x14e04000 0 0x1000>; 2213 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 2214 <&wpesys CLK_WPE_TOP_SMI_LARB7>; 2215 clock-names = "apb", "smi"; 2216 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; 2217 mediatek,larb-id = <SMI_L7_ID>; 2218 mediatek,smi = <&vpp_smi_common>; 2219 }; 2220 2221 vppsys1: syscon@14f00000 { 2222 compatible = "mediatek,mt8188-vppsys1", "syscon"; 2223 reg = <0 0x14f00000 0 0x1000>; 2224 #clock-cells = <1>; 2225 }; 2226 2227 larb5: smi@14f02000 { 2228 compatible = "mediatek,mt8188-smi-larb"; 2229 reg = <0 0x14f02000 0 0x1000>; 2230 clocks = <&vppsys1 CLK_VPP1_GALS5>, 2231 <&vppsys1 CLK_VPP1_LARB5>; 2232 clock-names = "apb", "smi"; 2233 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2234 mediatek,larb-id = <SMI_L5_ID>; 2235 mediatek,smi = <&vdo_smi_common>; 2236 }; 2237 2238 larb6: smi@14f03000 { 2239 compatible = "mediatek,mt8188-smi-larb"; 2240 reg = <0 0x14f03000 0 0x1000>; 2241 clocks = <&vppsys1 CLK_VPP1_GALS6>, 2242 <&vppsys1 CLK_VPP1_LARB6>; 2243 clock-names = "apb", "smi"; 2244 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2245 mediatek,larb-id = <SMI_L6_ID>; 2246 mediatek,smi = <&vpp_smi_common>; 2247 }; 2248 2249 imgsys: clock-controller@15000000 { 2250 compatible = "mediatek,mt8188-imgsys"; 2251 reg = <0 0x15000000 0 0x1000>; 2252 #clock-cells = <1>; 2253 }; 2254 2255 imgsys1_dip_top: clock-controller@15110000 { 2256 compatible = "mediatek,mt8188-imgsys1-dip-top"; 2257 reg = <0 0x15110000 0 0x1000>; 2258 #clock-cells = <1>; 2259 }; 2260 2261 imgsys1_dip_nr: clock-controller@15130000 { 2262 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 2263 reg = <0 0x15130000 0 0x1000>; 2264 #clock-cells = <1>; 2265 }; 2266 2267 imgsys_wpe1: clock-controller@15220000 { 2268 compatible = "mediatek,mt8188-imgsys-wpe1"; 2269 reg = <0 0x15220000 0 0x1000>; 2270 #clock-cells = <1>; 2271 }; 2272 2273 ipesys: clock-controller@15330000 { 2274 compatible = "mediatek,mt8188-ipesys"; 2275 reg = <0 0x15330000 0 0x1000>; 2276 #clock-cells = <1>; 2277 }; 2278 2279 imgsys_wpe2: clock-controller@15520000 { 2280 compatible = "mediatek,mt8188-imgsys-wpe2"; 2281 reg = <0 0x15520000 0 0x1000>; 2282 #clock-cells = <1>; 2283 }; 2284 2285 imgsys_wpe3: clock-controller@15620000 { 2286 compatible = "mediatek,mt8188-imgsys-wpe3"; 2287 reg = <0 0x15620000 0 0x1000>; 2288 #clock-cells = <1>; 2289 }; 2290 2291 camsys: clock-controller@16000000 { 2292 compatible = "mediatek,mt8188-camsys"; 2293 reg = <0 0x16000000 0 0x1000>; 2294 #clock-cells = <1>; 2295 }; 2296 2297 camsys_rawa: clock-controller@1604f000 { 2298 compatible = "mediatek,mt8188-camsys-rawa"; 2299 reg = <0 0x1604f000 0 0x1000>; 2300 #clock-cells = <1>; 2301 }; 2302 2303 camsys_yuva: clock-controller@1606f000 { 2304 compatible = "mediatek,mt8188-camsys-yuva"; 2305 reg = <0 0x1606f000 0 0x1000>; 2306 #clock-cells = <1>; 2307 }; 2308 2309 camsys_rawb: clock-controller@1608f000 { 2310 compatible = "mediatek,mt8188-camsys-rawb"; 2311 reg = <0 0x1608f000 0 0x1000>; 2312 #clock-cells = <1>; 2313 }; 2314 2315 camsys_yuvb: clock-controller@160af000 { 2316 compatible = "mediatek,mt8188-camsys-yuvb"; 2317 reg = <0 0x160af000 0 0x1000>; 2318 #clock-cells = <1>; 2319 }; 2320 2321 ccusys: clock-controller@17200000 { 2322 compatible = "mediatek,mt8188-ccusys"; 2323 reg = <0 0x17200000 0 0x1000>; 2324 #clock-cells = <1>; 2325 }; 2326 2327 video_decoder: video-decoder@18000000 { 2328 compatible = "mediatek,mt8188-vcodec-dec"; 2329 reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; 2330 ranges = <0 0 0 0x18000000 0 0x26000>; 2331 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; 2332 #address-cells = <2>; 2333 #size-cells = <2>; 2334 mediatek,scp = <&scp>; 2335 2336 video-codec@10000 { 2337 compatible = "mediatek,mtk-vcodec-lat"; 2338 reg = <0 0x10000 0 0x800>; 2339 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2340 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2341 clocks = <&topckgen CLK_TOP_VDEC>, 2342 <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, 2343 <&vdecsys_soc CLK_VDEC1_SOC_LAT>, 2344 <&topckgen CLK_TOP_UNIVPLL_D6>; 2345 clock-names = "sel", "vdec", "lat", "top"; 2346 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2347 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, 2348 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, 2349 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, 2350 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, 2351 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, 2352 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, 2353 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, 2354 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, 2355 <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; 2356 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2357 }; 2358 2359 video-codec@25000 { 2360 compatible = "mediatek,mtk-vcodec-core"; 2361 reg = <0 0x25000 0 0x1000>; 2362 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2363 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2364 clocks = <&topckgen CLK_TOP_VDEC>, 2365 <&vdecsys CLK_VDEC2_VDEC>, 2366 <&vdecsys CLK_VDEC2_LAT>, 2367 <&topckgen CLK_TOP_UNIVPLL_D6>; 2368 clock-names = "sel", "vdec", "lat", "top"; 2369 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2370 iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, 2371 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, 2372 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, 2373 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, 2374 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, 2375 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, 2376 <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, 2377 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, 2378 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, 2379 <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, 2380 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; 2381 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2382 }; 2383 }; 2384 2385 larb23: smi@1800d000 { 2386 compatible = "mediatek,mt8188-smi-larb"; 2387 reg = <0 0x1800d000 0 0x1000>; 2388 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, 2389 <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 2390 clock-names = "apb", "smi"; 2391 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2392 mediatek,larb-id = <SMI_L23_ID>; 2393 mediatek,smi = <&vpp_smi_common>; 2394 }; 2395 2396 vdecsys_soc: clock-controller@1800f000 { 2397 compatible = "mediatek,mt8188-vdecsys-soc"; 2398 reg = <0 0x1800f000 0 0x1000>; 2399 #clock-cells = <1>; 2400 }; 2401 2402 larb21: smi@1802e000 { 2403 compatible = "mediatek,mt8188-smi-larb"; 2404 reg = <0 0x1802e000 0 0x1000>; 2405 clocks = <&vdecsys CLK_VDEC2_LARB1>, 2406 <&vdecsys CLK_VDEC2_LARB1>; 2407 clock-names = "apb", "smi"; 2408 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2409 mediatek,larb-id = <SMI_L21_ID>; 2410 mediatek,smi = <&vdo_smi_common>; 2411 }; 2412 2413 vdecsys: clock-controller@1802f000 { 2414 compatible = "mediatek,mt8188-vdecsys"; 2415 reg = <0 0x1802f000 0 0x1000>; 2416 #clock-cells = <1>; 2417 }; 2418 2419 vencsys: clock-controller@1a000000 { 2420 compatible = "mediatek,mt8188-vencsys"; 2421 reg = <0 0x1a000000 0 0x1000>; 2422 #clock-cells = <1>; 2423 }; 2424 2425 larb19: smi@1a010000 { 2426 compatible = "mediatek,mt8188-smi-larb"; 2427 reg = <0 0x1a010000 0 0x1000>; 2428 clocks = <&vencsys CLK_VENC1_VENC>, 2429 <&vencsys CLK_VENC1_VENC>; 2430 clock-names = "apb", "smi"; 2431 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2432 mediatek,larb-id = <SMI_L19_ID>; 2433 mediatek,smi = <&vdo_smi_common>; 2434 }; 2435 2436 video_encoder: video-encoder@1a020000 { 2437 compatible = "mediatek,mt8188-vcodec-enc"; 2438 reg = <0 0x1a020000 0 0x10000>; 2439 #address-cells = <2>; 2440 #size-cells = <2>; 2441 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2442 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2443 clocks = <&vencsys CLK_VENC1_VENC>; 2444 clock-names = "venc_sel"; 2445 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2446 iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, 2447 <&vdo_iommu M4U_PORT_L19_VENC_REC>, 2448 <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, 2449 <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, 2450 <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, 2451 <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, 2452 <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, 2453 <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, 2454 <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, 2455 <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, 2456 <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; 2457 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2458 mediatek,scp = <&scp>; 2459 }; 2460 2461 jpeg_encoder: jpeg-encoder@1a030000 { 2462 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; 2463 reg = <0 0x1a030000 0 0x10000>; 2464 clocks = <&vencsys CLK_VENC1_JPGENC>; 2465 clock-names = "jpgenc"; 2466 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2467 iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, 2468 <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, 2469 <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, 2470 <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; 2471 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2472 }; 2473 2474 jpeg_decoder: jpeg-decoder@1a040000 { 2475 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; 2476 reg = <0 0x1a040000 0 0x10000>; 2477 clocks = <&vencsys CLK_VENC1_LARB>, 2478 <&vencsys CLK_VENC1_JPGDEC>; 2479 clock-names = "jpgdec-smi", "jpgdec"; 2480 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 2481 iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, 2482 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, 2483 <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, 2484 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, 2485 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, 2486 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; 2487 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2488 }; 2489 2490 ovl0: ovl@1c000000 { 2491 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; 2492 reg = <0 0x1c000000 0 0x1000>; 2493 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2494 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2495 iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; 2496 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2497 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2498 }; 2499 2500 rdma0: rdma@1c002000 { 2501 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; 2502 reg = <0 0x1c002000 0 0x1000>; 2503 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2504 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2505 iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; 2506 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2507 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2508 }; 2509 2510 color0: color@1c003000 { 2511 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; 2512 reg = <0 0x1c003000 0 0x1000>; 2513 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2514 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2515 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2516 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2517 }; 2518 2519 ccorr0: ccorr@1c004000 { 2520 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2521 reg = <0 0x1c004000 0 0x1000>; 2522 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2523 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2524 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2525 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2526 }; 2527 2528 aal0: aal@1c005000 { 2529 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; 2530 reg = <0 0x1c005000 0 0x1000>; 2531 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2532 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2533 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2534 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2535 }; 2536 2537 gamma0: gamma@1c006000 { 2538 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; 2539 reg = <0 0x1c006000 0 0x1000>; 2540 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2541 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2542 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2543 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2544 }; 2545 2546 dither0: dither@1c007000 { 2547 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; 2548 reg = <0 0x1c007000 0 0x1000>; 2549 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2550 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2551 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2552 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2553 }; 2554 2555 disp_dsi0: dsi@1c008000 { 2556 compatible = "mediatek,mt8188-dsi"; 2557 reg = <0 0x1c008000 0 0x1000>; 2558 clocks = <&vdosys0 CLK_VDO0_DSI0>, 2559 <&vdosys0 CLK_VDO0_DSI0_DSI>, 2560 <&mipi_tx_config0>; 2561 clock-names = "engine", "digital", "hs"; 2562 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 2563 phys = <&mipi_tx_config0>; 2564 phy-names = "dphy"; 2565 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2566 resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; 2567 status = "disabled"; 2568 }; 2569 2570 disp_dsi1: dsi@1c012000 { 2571 compatible = "mediatek,mt8188-dsi"; 2572 reg = <0 0x1c012000 0 0x1000>; 2573 clocks = <&vdosys0 CLK_VDO0_DSI1>, 2574 <&vdosys0 CLK_VDO0_DSI1_DSI>, 2575 <&mipi_tx_config1>; 2576 clock-names = "engine", "digital", "hs"; 2577 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 2578 phys = <&mipi_tx_config1>; 2579 phy-names = "dphy"; 2580 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2581 resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; 2582 status = "disabled"; 2583 }; 2584 2585 dp_intf0: dp-intf@1c015000 { 2586 compatible = "mediatek,mt8188-dp-intf"; 2587 reg = <0 0x1c015000 0 0x1000>; 2588 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2589 <&vdosys0 CLK_VDO0_DP_INTF0>, 2590 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2591 clock-names = "pixel", "engine", "pll"; 2592 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2593 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2594 status = "disabled"; 2595 }; 2596 2597 mutex0: mutex@1c016000 { 2598 compatible = "mediatek,mt8188-disp-mutex"; 2599 reg = <0 0x1c016000 0 0x1000>; 2600 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2601 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2602 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2603 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 2604 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2605 }; 2606 2607 postmask0: postmask@1c01a000 { 2608 compatible = "mediatek,mt8188-disp-postmask", 2609 "mediatek,mt8192-disp-postmask"; 2610 reg = <0 0x1c01a000 0 0x1000>; 2611 clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; 2612 interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; 2613 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2614 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 2615 }; 2616 2617 vdosys0: syscon@1c01d000 { 2618 compatible = "mediatek,mt8188-vdosys0", "syscon"; 2619 reg = <0 0x1c01d000 0 0x1000>; 2620 #clock-cells = <1>; 2621 #reset-cells = <1>; 2622 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2623 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; 2624 }; 2625 2626 larb0: smi@1c022000 { 2627 compatible = "mediatek,mt8188-smi-larb"; 2628 reg = <0 0x1c022000 0 0x1000>; 2629 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2630 <&vdosys0 CLK_VDO0_SMI_LARB>; 2631 clock-names = "apb", "smi"; 2632 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2633 mediatek,larb-id = <SMI_L0_ID>; 2634 mediatek,smi = <&vdo_smi_common>; 2635 }; 2636 2637 larb1: smi@1c023000 { 2638 compatible = "mediatek,mt8188-smi-larb"; 2639 reg = <0 0x1c023000 0 0x1000>; 2640 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2641 <&vdosys0 CLK_VDO0_SMI_LARB>; 2642 clock-names = "apb", "smi"; 2643 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2644 mediatek,larb-id = <SMI_L1_ID>; 2645 mediatek,smi = <&vpp_smi_common>; 2646 }; 2647 2648 vdo_smi_common: smi@1c024000 { 2649 compatible = "mediatek,mt8188-smi-common-vdo"; 2650 reg = <0 0x1c024000 0 0x1000>; 2651 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2652 <&vdosys0 CLK_VDO0_SMI_GALS>; 2653 clock-names = "apb", "smi"; 2654 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2655 }; 2656 2657 vdo_iommu: iommu@1c028000 { 2658 compatible = "mediatek,mt8188-iommu-vdo"; 2659 reg = <0 0x1c028000 0 0x5000>; 2660 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2661 clock-names = "bclk"; 2662 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; 2663 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2664 #iommu-cells = <1>; 2665 mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; 2666 }; 2667 2668 vdosys1: syscon@1c100000 { 2669 compatible = "mediatek,mt8188-vdosys1", "syscon"; 2670 reg = <0 0x1c100000 0 0x1000>; 2671 #clock-cells = <1>; 2672 #reset-cells = <1>; 2673 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2674 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; 2675 }; 2676 2677 mutex1: mutex@1c101000 { 2678 compatible = "mediatek,mt8188-disp-mutex"; 2679 reg = <0 0x1c101000 0 0x1000>; 2680 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2681 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2682 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2683 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 2684 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2685 }; 2686 2687 larb2: smi@1c102000 { 2688 compatible = "mediatek,mt8188-smi-larb"; 2689 reg = <0 0x1c102000 0 0x1000>; 2690 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2691 <&vdosys1 CLK_VDO1_SMI_LARB2>; 2692 clock-names = "apb", "smi"; 2693 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2694 mediatek,larb-id = <SMI_L2_ID>; 2695 mediatek,smi = <&vdo_smi_common>; 2696 }; 2697 2698 larb3: smi@1c103000 { 2699 compatible = "mediatek,mt8188-smi-larb"; 2700 reg = <0 0x1c103000 0 0x1000>; 2701 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2702 <&vdosys1 CLK_VDO1_SMI_LARB3>; 2703 clock-names = "apb", "smi"; 2704 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2705 mediatek,larb-id = <SMI_L3_ID>; 2706 mediatek,smi = <&vpp_smi_common>; 2707 }; 2708 2709 vdo1_rdma0: rdma@1c104000 { 2710 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2711 reg = <0 0x1c104000 0 0x1000>; 2712 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2713 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2714 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; 2715 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2716 #dma-cells = <1>; 2717 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2718 }; 2719 2720 vdo1_rdma1: rdma@1c105000 { 2721 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2722 reg = <0 0x1c105000 0 0x1000>; 2723 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2724 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2725 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; 2726 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2727 #dma-cells = <1>; 2728 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2729 }; 2730 2731 vdo1_rdma2: rdma@1c106000 { 2732 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2733 reg = <0 0x1c106000 0 0x1000>; 2734 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2735 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2736 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; 2737 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2738 #dma-cells = <1>; 2739 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2740 }; 2741 2742 vdo1_rdma3: rdma@1c107000 { 2743 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2744 reg = <0 0x1c107000 0 0x1000>; 2745 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2746 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2747 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; 2748 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2749 #dma-cells = <1>; 2750 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2751 }; 2752 2753 vdo1_rdma4: rdma@1c108000 { 2754 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2755 reg = <0 0x1c108000 0 0x1000>; 2756 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2757 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2758 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; 2759 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2760 #dma-cells = <1>; 2761 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2762 }; 2763 2764 vdo1_rdma5: rdma@1c109000 { 2765 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2766 reg = <0 0x1c109000 0 0x1000>; 2767 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2768 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2769 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; 2770 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2771 #dma-cells = <1>; 2772 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2773 }; 2774 2775 vdo1_rdma6: rdma@1c10a000 { 2776 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2777 reg = <0 0x1c10a000 0 0x1000>; 2778 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2779 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 2780 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; 2781 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2782 #dma-cells = <1>; 2783 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 2784 }; 2785 2786 vdo1_rdma7: rdma@1c10b000 { 2787 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 2788 reg = <0 0x1c10b000 0 0x1000>; 2789 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 2790 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 2791 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; 2792 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2793 #dma-cells = <1>; 2794 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 2795 }; 2796 2797 merge1: merge@1c10c000 { 2798 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2799 reg = <0 0x1c10c000 0 0x1000>; 2800 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 2801 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 2802 clock-names = "merge", "merge_async"; 2803 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 2804 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2805 resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; 2806 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 2807 mediatek,merge-mute; 2808 }; 2809 2810 merge2: merge@1c10d000 { 2811 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2812 reg = <0 0x1c10d000 0 0x1000>; 2813 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 2814 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 2815 clock-names = "merge", "merge_async"; 2816 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 2817 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2818 resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; 2819 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 2820 mediatek,merge-mute; 2821 }; 2822 2823 merge3: merge@1c10e000 { 2824 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2825 reg = <0 0x1c10e000 0 0x1000>; 2826 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 2827 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 2828 clock-names = "merge", "merge_async"; 2829 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 2830 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2831 resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; 2832 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 2833 mediatek,merge-mute; 2834 }; 2835 2836 merge4: merge@1c10f000 { 2837 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2838 reg = <0 0x1c10f000 0 0x1000>; 2839 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 2840 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 2841 clock-names = "merge", "merge_async"; 2842 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 2843 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2844 resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; 2845 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 2846 mediatek,merge-mute; 2847 }; 2848 2849 merge5: merge@1c110000 { 2850 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 2851 reg = <0 0x1c110000 0 0x1000>; 2852 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 2853 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 2854 clock-names = "merge", "merge_async"; 2855 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 2856 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2857 resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; 2858 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 2859 mediatek,merge-fifo-en; 2860 }; 2861 2862 dp_intf1: dp-intf@1c113000 { 2863 compatible = "mediatek,mt8188-dp-intf"; 2864 reg = <0 0x1c113000 0 0x1000>; 2865 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 2866 <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, 2867 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2868 clock-names = "pixel", "engine", "pll"; 2869 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2870 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2871 status = "disabled"; 2872 }; 2873 2874 ethdr0: ethdr@1c114000 { 2875 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; 2876 reg = <0 0x1c114000 0 0x1000>, 2877 <0 0x1c115000 0 0x1000>, 2878 <0 0x1c117000 0 0x1000>, 2879 <0 0x1c119000 0 0x1000>, 2880 <0 0x1c11a000 0 0x1000>, 2881 <0 0x1c11b000 0 0x1000>, 2882 <0 0x1c11c000 0 0x1000>; 2883 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 2884 "vdo_be", "adl_ds"; 2885 2886 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 2887 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 2888 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 2889 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 2890 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 2891 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 2892 <&vdosys1 CLK_VDO1_26M_SLOW>, 2893 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 2894 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 2895 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 2896 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 2897 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 2898 <&topckgen CLK_TOP_ETHDR>; 2899 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 2900 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 2901 "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; 2902 2903 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; 2904 iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, 2905 <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; 2906 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2907 resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, 2908 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, 2909 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, 2910 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, 2911 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; 2912 2913 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 2914 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 2915 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 2916 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 2917 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 2918 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 2919 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 2920 }; 2921 2922 padding0: padding@1c11d000 { 2923 compatible = "mediatek,mt8188-disp-padding"; 2924 reg = <0 0x1c11d000 0 0x1000>; 2925 clocks = <&vdosys1 CLK_VDO1_PADDING0>; 2926 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2927 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; 2928 }; 2929 2930 padding1: padding@1c11e000 { 2931 compatible = "mediatek,mt8188-disp-padding"; 2932 reg = <0 0x1c11e000 0 0x1000>; 2933 clocks = <&vdosys1 CLK_VDO1_PADDING1>; 2934 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2935 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; 2936 }; 2937 2938 padding2: padding@1c11f000 { 2939 compatible = "mediatek,mt8188-disp-padding"; 2940 reg = <0 0x1c11f000 0 0x1000>; 2941 clocks = <&vdosys1 CLK_VDO1_PADDING2>; 2942 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2943 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; 2944 }; 2945 2946 padding3: padding@1c120000 { 2947 compatible = "mediatek,mt8188-disp-padding"; 2948 reg = <0 0x1c120000 0 0x1000>; 2949 clocks = <&vdosys1 CLK_VDO1_PADDING3>; 2950 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2951 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; 2952 }; 2953 2954 padding4: padding@1c121000 { 2955 compatible = "mediatek,mt8188-disp-padding"; 2956 reg = <0 0x1c121000 0 0x1000>; 2957 clocks = <&vdosys1 CLK_VDO1_PADDING4>; 2958 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; 2960 }; 2961 2962 padding5: padding@1c122000 { 2963 compatible = "mediatek,mt8188-disp-padding"; 2964 reg = <0 0x1c122000 0 0x1000>; 2965 clocks = <&vdosys1 CLK_VDO1_PADDING5>; 2966 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2967 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; 2968 }; 2969 2970 padding6: padding@1c123000 { 2971 compatible = "mediatek,mt8188-disp-padding"; 2972 reg = <0 0x1c123000 0 0x1000>; 2973 clocks = <&vdosys1 CLK_VDO1_PADDING6>; 2974 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2975 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; 2976 }; 2977 2978 padding7: padding@1c124000 { 2979 compatible = "mediatek,mt8188-disp-padding"; 2980 reg = <0 0x1c124000 0 0x1000>; 2981 clocks = <&vdosys1 CLK_VDO1_PADDING7>; 2982 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 2983 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; 2984 }; 2985 2986 edp_tx: edp-tx@1c500000 { 2987 compatible = "mediatek,mt8188-edp-tx"; 2988 reg = <0 0x1c500000 0 0x8000>; 2989 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2990 nvmem-cells = <&dp_calib_data>; 2991 nvmem-cell-names = "dp_calibration_data"; 2992 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; 2993 max-linkrate-mhz = <8100>; 2994 status = "disabled"; 2995 }; 2996 2997 dp_tx: dp-tx@1c600000 { 2998 compatible = "mediatek,mt8188-dp-tx"; 2999 reg = <0 0x1c600000 0 0x8000>; 3000 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3001 nvmem-cells = <&dp_calib_data>; 3002 nvmem-cell-names = "dp_calibration_data"; 3003 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; 3004 max-linkrate-mhz = <5400>; 3005 status = "disabled"; 3006 }; 3007 }; 3008}; 3009