1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include "mt8186.dtsi" 7#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/input/gpio-keys.h> 11#include <dt-bindings/regulator/mediatek,mt6397-regulator.h> 12 13/ { 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c5 = &i2c5; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 /* The size should be filled in by the bootloader. */ 32 reg = <0 0x40000000 0 0>; 33 }; 34 35 backlight_lcd0: backlight-lcd0 { 36 compatible = "pwm-backlight"; 37 pwms = <&pwm0 0 500000>; 38 power-supply = <&ppvar_sys>; 39 enable-gpios = <&pio 152 0>; 40 brightness-levels = <0 1023>; 41 num-interpolated-steps = <1023>; 42 default-brightness-level = <576>; 43 }; 44 45 bt-sco { 46 compatible = "linux,bt-sco"; 47 #sound-dai-cells = <0>; 48 }; 49 50 dmic-codec { 51 compatible = "dmic-codec"; 52 #sound-dai-cells = <0>; 53 num-channels = <2>; 54 wakeup-delay-ms = <50>; 55 }; 56 57 gpio_keys: gpio-keys { 58 compatible = "gpio-keys"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pen_eject>; 61 62 pen_insert: pen-insert-switch { 63 label = "Pen Insert"; 64 /* Insert = low, eject = high */ 65 gpios = <&pio 18 GPIO_ACTIVE_LOW>; 66 wakeup-event-action = <EV_ACT_DEASSERTED>; 67 wakeup-source; 68 linux,code = <SW_PEN_INSERTED>; 69 linux,input-type = <EV_SW>; 70 }; 71 }; 72 73 pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&en_pp1800_dpbrdg>; 77 gpios = <&pio 39 GPIO_ACTIVE_HIGH>; 78 regulator-name = "pp1800_dpbrdg_dx"; 79 enable-active-high; 80 vin-supply = <&mt6366_vio18_reg>; 81 }; 82 83 pp3300_disp_x: regulator-pp3300-disp-x { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&edp_panel_fixed_pins>; 87 gpios = <&pio 153 GPIO_ACTIVE_HIGH>; 88 regulator-name = "pp3300_disp_x"; 89 enable-active-high; 90 regulator-boot-on; 91 vin-supply = <&pp3300_z2>; 92 }; 93 94 /* system wide LDO 3.3V power rail */ 95 pp3300_z5: regulator-pp3300-ldo-z5 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_ldo_z5"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 /* separately switched 3.3V power rail */ 106 pp3300_s3: regulator-pp3300-s3 { 107 compatible = "regulator-fixed"; 108 regulator-name = "pp3300_s3"; 109 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 110 regulator-always-on; 111 regulator-boot-on; 112 vin-supply = <&pp3300_z2>; 113 }; 114 115 /* system wide 3.3V power rail */ 116 pp3300_z2: regulator-pp3300-z2 { 117 compatible = "regulator-fixed"; 118 regulator-name = "pp3300_z2"; 119 /* EN pin tied to pp4200_z2, which is controlled by EC */ 120 regulator-always-on; 121 regulator-boot-on; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&ppvar_sys>; 125 }; 126 127 /* system wide 4.2V power rail */ 128 pp4200_z2: regulator-pp4200-z2 { 129 compatible = "regulator-fixed"; 130 regulator-name = "pp4200_z2"; 131 /* controlled by EC */ 132 regulator-always-on; 133 regulator-boot-on; 134 regulator-min-microvolt = <4200000>; 135 regulator-max-microvolt = <4200000>; 136 vin-supply = <&ppvar_sys>; 137 }; 138 139 /* system wide switching 5.0V power rail */ 140 pp5000_z2: regulator-pp5000-z2 { 141 compatible = "regulator-fixed"; 142 regulator-name = "pp5000_z2"; 143 /* controlled by EC */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 vin-supply = <&ppvar_sys>; 149 }; 150 151 /* system wide semi-regulated power rail from battery or USB */ 152 ppvar_sys: regulator-ppvar-sys { 153 compatible = "regulator-fixed"; 154 regulator-name = "ppvar_sys"; 155 regulator-always-on; 156 regulator-boot-on; 157 }; 158 159 reserved_memory: reserved-memory { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 afe_dma_mem: audio-dma-pool { 165 compatible = "shared-dma-pool"; 166 size = <0 0x100000>; 167 alignment = <0 0x10>; 168 no-map; 169 }; 170 171 adsp_dma_mem: memory@61000000 { 172 compatible = "shared-dma-pool"; 173 reg = <0 0x61000000 0 0x100000>; 174 no-map; 175 }; 176 177 adsp_mem: memory@60000000 { 178 compatible = "shared-dma-pool"; 179 reg = <0 0x60000000 0 0x1000000>; 180 no-map; 181 }; 182 183 scp_mem: memory@50000000 { 184 compatible = "shared-dma-pool"; 185 reg = <0 0x50000000 0 0x10a0000>; 186 no-map; 187 }; 188 }; 189 190 sound: sound { 191 compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; 192 pinctrl-names = "aud_clk_mosi_off", 193 "aud_clk_mosi_on", 194 "aud_clk_miso_off", 195 "aud_clk_miso_on", 196 "aud_dat_miso_off", 197 "aud_dat_miso_on", 198 "aud_dat_mosi_off", 199 "aud_dat_mosi_on", 200 "aud_gpio_i2s0_off", 201 "aud_gpio_i2s0_on", 202 "aud_gpio_i2s1_off", 203 "aud_gpio_i2s1_on", 204 "aud_gpio_i2s2_off", 205 "aud_gpio_i2s2_on", 206 "aud_gpio_i2s3_off", 207 "aud_gpio_i2s3_on", 208 "aud_gpio_pcm_off", 209 "aud_gpio_pcm_on", 210 "aud_gpio_dmic_sec"; 211 pinctrl-0 = <&aud_clk_mosi_off>; 212 pinctrl-1 = <&aud_clk_mosi_on>; 213 pinctrl-2 = <&aud_clk_miso_off>; 214 pinctrl-3 = <&aud_clk_miso_on>; 215 pinctrl-4 = <&aud_dat_miso_off>; 216 pinctrl-5 = <&aud_dat_miso_on>; 217 pinctrl-6 = <&aud_dat_mosi_off>; 218 pinctrl-7 = <&aud_dat_mosi_on>; 219 pinctrl-8 = <&aud_gpio_i2s0_off>; 220 pinctrl-9 = <&aud_gpio_i2s0_on>; 221 pinctrl-10 = <&aud_gpio_i2s1_off>; 222 pinctrl-11 = <&aud_gpio_i2s1_on>; 223 pinctrl-12 = <&aud_gpio_i2s2_off>; 224 pinctrl-13 = <&aud_gpio_i2s2_on>; 225 pinctrl-14 = <&aud_gpio_i2s3_off>; 226 pinctrl-15 = <&aud_gpio_i2s3_on>; 227 pinctrl-16 = <&aud_gpio_pcm_off>; 228 pinctrl-17 = <&aud_gpio_pcm_on>; 229 pinctrl-18 = <&aud_gpio_dmic_sec>; 230 mediatek,adsp = <&adsp>; 231 mediatek,platform = <&afe>; 232 233 audio-routing = 234 "Headphone", "HPOL", 235 "Headphone", "HPOR", 236 "IN1P", "Headset Mic", 237 "Speakers", "Speaker", 238 "HDMI1", "TX"; 239 240 hs-playback-dai-link { 241 link-name = "I2S0"; 242 dai-format = "i2s"; 243 mediatek,clk-provider = "cpu"; 244 codec { 245 sound-dai = <&rt5682s 0>; 246 }; 247 }; 248 249 hs-capture-dai-link { 250 link-name = "I2S1"; 251 dai-format = "i2s"; 252 mediatek,clk-provider = "cpu"; 253 codec { 254 sound-dai = <&rt5682s 0>; 255 }; 256 }; 257 258 spk-share-dai-link { 259 link-name = "I2S2"; 260 mediatek,clk-provider = "cpu"; 261 }; 262 263 spk-hdmi-playback-dai-link { 264 link-name = "I2S3"; 265 dai-format = "i2s"; 266 mediatek,clk-provider = "cpu"; 267 /* RT1019P and IT6505 connected to the same I2S line */ 268 codec { 269 sound-dai = <&it6505dptx>, <&speaker_codec>; 270 }; 271 }; 272 }; 273 274 speaker_codec: speaker-codec { 275 compatible = "realtek,rt1019p"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&speaker_codec_pins_default>; 278 #sound-dai-cells = <0>; 279 sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; 280 }; 281 282 usb_p1_vbus: regulator-usb-p1-vbus { 283 compatible = "regulator-fixed"; 284 gpio = <&pio 148 GPIO_ACTIVE_HIGH>; 285 regulator-name = "vbus1"; 286 regulator-min-microvolt = <5000000>; 287 regulator-max-microvolt = <5000000>; 288 enable-active-high; 289 vin-supply = <&pp5000_z2>; 290 }; 291 292 wifi_pwrseq: wifi-pwrseq { 293 compatible = "mmc-pwrseq-simple"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&wifi_enable_pin>; 296 post-power-on-delay-ms = <50>; 297 reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 298 }; 299 300 wifi_wakeup: wifi-wakeup { 301 compatible = "gpio-keys"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&wifi_wakeup_pin>; 304 305 wowlan-event { 306 label = "Wake on WiFi"; 307 gpios = <&pio 7 GPIO_ACTIVE_LOW>; 308 linux,code = <KEY_WAKEUP>; 309 wakeup-source; 310 }; 311 }; 312}; 313 314&adsp { 315 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 316 status = "okay"; 317}; 318 319&afe { 320 memory-region = <&afe_dma_mem>; 321 status = "okay"; 322}; 323 324&cci { 325 proc-supply = <&mt6366_vproc12_reg>; 326}; 327 328&cpu0 { 329 proc-supply = <&mt6366_vproc12_reg>; 330}; 331 332&cpu1 { 333 proc-supply = <&mt6366_vproc12_reg>; 334}; 335 336&cpu2 { 337 proc-supply = <&mt6366_vproc12_reg>; 338}; 339 340&cpu3 { 341 proc-supply = <&mt6366_vproc12_reg>; 342}; 343 344&cpu4 { 345 proc-supply = <&mt6366_vproc12_reg>; 346}; 347 348&cpu5 { 349 proc-supply = <&mt6366_vproc12_reg>; 350}; 351 352&cpu6 { 353 proc-supply = <&mt6366_vproc11_reg>; 354}; 355 356&cpu7 { 357 proc-supply = <&mt6366_vproc11_reg>; 358}; 359 360&dpi { 361 pinctrl-names = "default", "sleep"; 362 pinctrl-0 = <&dpi_pins_default>; 363 pinctrl-1 = <&dpi_pins_sleep>; 364 /* TODO Re-enable after DP to Type-C port muxing can be described */ 365 status = "disabled"; 366}; 367 368&dpi_out { 369 remote-endpoint = <&it6505_in>; 370}; 371 372&dsi0 { 373 status = "okay"; 374}; 375 376&gic { 377 mediatek,broken-save-restore-fw; 378}; 379 380&gpu { 381 mali-supply = <&mt6366_vgpu_reg>; 382 status = "okay"; 383}; 384 385&i2c0 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c0_pins>; 388 status = "okay"; 389}; 390 391&i2c1 { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&i2c1_pins>; 394 clock-frequency = <400000>; 395 i2c-scl-internal-delay-ns = <8000>; 396 status = "okay"; 397}; 398 399&i2c2 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c2_pins>; 402 clock-frequency = <400000>; 403 i2c-scl-internal-delay-ns = <10000>; 404 status = "okay"; 405 406 trackpad: trackpad@15 { 407 compatible = "elan,ekth3000"; 408 reg = <0x15>; 409 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&trackpad_pin>; 412 vcc-supply = <&pp3300_s3>; 413 wakeup-source; 414 }; 415}; 416 417&i2c3 { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&i2c3_pins>; 420 clock-frequency = <100000>; 421 status = "okay"; 422 423 it6505dptx: dp-bridge@5c { 424 compatible = "ite,it6505"; 425 reg = <0x5c>; 426 interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&it6505_pins>; 429 #sound-dai-cells = <0>; 430 ovdd-supply = <&mt6366_vsim2_reg>; 431 pwr18-supply = <&pp1800_dpbrdg_dx>; 432 reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>; 433 extcon = <&usbc_extcon>; 434 435 ports { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 439 port@0 { 440 reg = <0>; 441 442 it6505_in: endpoint { 443 link-frequencies = /bits/ 64 <150000000>; 444 remote-endpoint = <&dpi_out>; 445 }; 446 }; 447 448 port@1 { 449 reg = <1>; 450 }; 451 }; 452 }; 453}; 454 455&i2c5 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c5_pins>; 458 status = "okay"; 459 460 rt5682s: codec@1a { 461 compatible = "realtek,rt5682s"; 462 reg = <0x1a>; 463 interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; 464 #sound-dai-cells = <1>; 465 AVDD-supply = <&mt6366_vio18_reg>; 466 DBVDD-supply = <&mt6366_vio18_reg>; 467 LDO1-IN-supply = <&mt6366_vio18_reg>; 468 MICVDD-supply = <&pp3300_z2>; 469 realtek,jd-src = <1>; 470 }; 471}; 472 473&mfg0 { 474 domain-supply = <&mt6366_vsram_gpu_reg>; 475}; 476 477&mfg1 { 478 domain-supply = <&mt6366_vgpu_reg>; 479}; 480 481&mipi_tx0 { 482 status = "okay"; 483}; 484 485&mmc0 { 486 pinctrl-names = "default", "state_uhs"; 487 pinctrl-0 = <&mmc0_pins_default>; 488 pinctrl-1 = <&mmc0_pins_uhs>; 489 bus-width = <8>; 490 max-frequency = <200000000>; 491 non-removable; 492 cap-mmc-highspeed; 493 mmc-hs200-1_8v; 494 mmc-hs400-1_8v; 495 supports-cqe; 496 no-sd; 497 no-sdio; 498 cap-mmc-hw-reset; 499 hs400-ds-delay = <0x11814>; 500 mediatek,hs400-ds-dly3 = <0x14>; 501 vmmc-supply = <&mt6366_vemc_reg>; 502 vqmmc-supply = <&mt6366_vio18_reg>; 503 status = "okay"; 504}; 505 506&mmc1 { 507 pinctrl-names = "default", "state_uhs", "state_eint"; 508 pinctrl-0 = <&mmc1_pins_default>; 509 pinctrl-1 = <&mmc1_pins_uhs>; 510 pinctrl-2 = <&mmc1_pins_eint>; 511 /delete-property/ interrupts; 512 interrupt-names = "msdc", "sdio_wakeup"; 513 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 514 <&pio 87 IRQ_TYPE_LEVEL_LOW>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 bus-width = <4>; 518 max-frequency = <200000000>; 519 cap-sd-highspeed; 520 sd-uhs-sdr104; 521 sd-uhs-sdr50; 522 keep-power-in-suspend; 523 wakeup-source; 524 cap-sdio-irq; 525 no-mmc; 526 no-sd; 527 vmmc-supply = <&pp3300_s3>; 528 vqmmc-supply = <&mt6366_vio18_reg>; 529 mmc-pwrseq = <&wifi_pwrseq>; 530 status = "okay"; 531 532 bluetooth@2 { 533 compatible = "mediatek,mt7921s-bluetooth"; 534 reg = <2>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&bt_pins_reset>; 537 reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; 538 }; 539}; 540 541&nor_flash { 542 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&nor_pins_default>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "okay"; 548 549 flash@0 { 550 compatible = "jedec,spi-nor"; 551 reg = <0>; 552 spi-max-frequency = <39000000>; 553 }; 554}; 555 556&pio { 557 /* 185 lines */ 558 gpio-line-names = "TP", 559 "TP", 560 "TP", 561 "I2S0_HP_DI", 562 "I2S3_DP_SPKR_DO", 563 "SAR_INT_ODL", 564 "BT_WAKE_AP_ODL", 565 "WIFI_INT_ODL", 566 "DPBRDG_INT_ODL", 567 "EDPBRDG_INT_ODL", 568 "EC_AP_HPD_OD", 569 "TCHPAD_INT_ODL", 570 "TCHSCR_INT_1V8_ODL", 571 "EC_AP_INT_ODL", 572 "EC_IN_RW_ODL", 573 "GSC_AP_INT_ODL", 574 /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 575 "AP_FLASH_WP_L", 576 "HP_INT_ODL", 577 "PEN_EJECT_OD", 578 "WCAM_PWDN_L", 579 "WCAM_RST_L", 580 "UCAM_SEN_EN", 581 "UCAM_RST_L", 582 "LTE_RESET_L", 583 "LTE_SAR_DETECT_L", 584 "I2S2_DP_SPK_MCK", 585 "I2S2_DP_SPKR_BCK", 586 "I2S2_DP_SPKR_LRCK", 587 "I2S2_DP_SPKR_DI (TP)", 588 "EN_PP1000_EDPBRDG", 589 "EN_PP1800_EDPBRDG", 590 "EN_PP3300_EDPBRDG", 591 "UART_GSC_TX_AP_RX", 592 "UART_AP_TX_GSC_RX", 593 "UART_DBGCON_TX_ADSP_RX", 594 "UART_ADSP_TX_DBGCON_RX", 595 "EN_PP1000_DPBRDG", 596 "TCHSCR_REPORT_DISABLE", 597 "EN_PP3300_DPBRDG", 598 "EN_PP1800_DPBRDG", 599 "SPI_AP_CLK_EC", 600 "SPI_AP_CS_EC_L", 601 "SPI_AP_DO_EC_DI", 602 "SPI_AP_DI_EC_DO", 603 "SPI_AP_CLK_GSC", 604 "SPI_AP_CS_GSC_L", 605 "SPI_AP_DO_GSC_DI", 606 "SPI_AP_DI_GSC_DO", 607 "UART_DBGCON_TX_SCP_RX", 608 "UART_SCP_TX_DBGCON_RX", 609 "EN_PP1200_CAM_X", 610 "EN_PP2800A_VCM_X", 611 "EN_PP2800A_UCAM_X", 612 "EN_PP2800A_WCAM_X", 613 "WLAN_MODULE_RST_L", 614 "EN_PP1200_UCAM_X", 615 "I2S1_HP_DO", 616 "I2S1_HP_BCK", 617 "I2S1_HP_LRCK", 618 "I2S1_HP_MCK", 619 "TCHSCR_RST_1V8_L", 620 "SPI_AP_CLK_ROM", 621 "SPI_AP_CS_ROM_L", 622 "SPI_AP_DO_ROM_DI", 623 "SPI_AP_DI_ROM_DO", 624 "NC", 625 "NC", 626 "EMMC_STRB", 627 "EMMC_CLK", 628 "EMMC_CMD", 629 "EMMC_RST_L", 630 "EMMC_DATA0", 631 "EMMC_DATA1", 632 "EMMC_DATA2", 633 "EMMC_DATA3", 634 "EMMC_DATA4", 635 "EMMC_DATA5", 636 "EMMC_DATA6", 637 "EMMC_DATA7", 638 "AP_KPCOL0", 639 "NC", 640 "NC", 641 "NC", 642 "TP", 643 "SDIO_CLK", 644 "SDIO_CMD", 645 "SDIO_DATA0", 646 "SDIO_DATA1", 647 "SDIO_DATA2", 648 "SDIO_DATA3", 649 "NC", 650 "NC", 651 "NC", 652 "NC", 653 "NC", 654 "NC", 655 "EDPBRDG_PWREN", 656 "BL_PWM_1V8", 657 "EDPBRDG_RST_L", 658 "MIPI_DPI_CLK", 659 "MIPI_DPI_VSYNC", 660 "MIPI_DPI_HSYNC", 661 "MIPI_DPI_DE", 662 "MIPI_DPI_D0", 663 "MIPI_DPI_D1", 664 "MIPI_DPI_D2", 665 "MIPI_DPI_D3", 666 "MIPI_DPI_D4", 667 "MIPI_DPI_D5", 668 "MIPI_DPI_D6", 669 "MIPI_DPI_DA7", 670 "MIPI_DPI_D8", 671 "MIPI_DPI_D9", 672 "MIPI_DPI_D10", 673 "MIPI_DPI_D11", 674 "PCM_BT_CLK", 675 "PCM_BT_SYNC", 676 "PCM_BT_DI", 677 "PCM_BT_DO", 678 "JTAG_TMS_TP", 679 "JTAG_TCK_TP", 680 "JTAG_TDI_TP", 681 "JTAG_TDO_TP", 682 "JTAG_TRSTN_TP", 683 "CLK_24M_WCAM", 684 "CLK_24M_UCAM", 685 "UCAM_DET_ODL", 686 "AP_I2C_EDPBRDG_SCL_1V8", 687 "AP_I2C_EDPBRDG_SDA_1V8", 688 "AP_I2C_TCHSCR_SCL_1V8", 689 "AP_I2C_TCHSCR_SDA_1V8", 690 "AP_I2C_TCHPAD_SCL_1V8", 691 "AP_I2C_TCHPAD_SDA_1V8", 692 "AP_I2C_DPBRDG_SCL_1V8", 693 "AP_I2C_DPBRDG_SDA_1V8", 694 "AP_I2C_WLAN_SCL_1V8", 695 "AP_I2C_WLAN_SDA_1V8", 696 "AP_I2C_AUD_SCL_1V8", 697 "AP_I2C_AUD_SDA_1V8", 698 "AP_I2C_TPM_SCL_1V8", 699 "AP_I2C_UCAM_SDA_1V8", 700 "AP_I2C_UCAM_SCL_1V8", 701 "AP_I2C_UCAM_SDA_1V8", 702 "AP_I2C_WCAM_SCL_1V8", 703 "AP_I2C_WCAM_SDA_1V8", 704 "SCP_I2C_SENSOR_SCL_1V8", 705 "SCP_I2C_SENSOR_SDA_1V8", 706 "AP_EC_WARM_RST_REQ", 707 "AP_XHCI_INIT_DONE", 708 "USB3_HUB_RST_L", 709 "EN_SPKR", 710 "BEEP_ON", 711 "AP_EDP_BKLTEN", 712 "EN_PP3300_DISP_X", 713 "EN_PP3300_SDBRDG_X", 714 "BT_KILL_1V8_L", 715 "WIFI_KILL_1V8_L", 716 "PWRAP_SPI0_CSN", 717 "PWRAP_SPI0_CK", 718 "PWRAP_SPI0_MO", 719 "PWRAP_SPI0_MI", 720 "SRCLKENA0", 721 "SRCLKENA1", 722 "SCP_VREQ_VAO", 723 "AP_RTC_CLK32K", 724 "AP_PMIC_WDTRST_L", 725 "AUD_CLK_MOSI", 726 "AUD_SYNC_MOSI", 727 "AUD_DAT_MOSI0", 728 "AUD_DAT_MOSI1", 729 "AUD_CLK_MISO", 730 "AUD_SYNC_MISO", 731 "AUD_DAT_MISO0", 732 "AUD_DAT_MISO1", 733 "NC", 734 "NC", 735 "DPBRDG_PWREN", 736 "DPBRDG_RST_L", 737 "LTE_W_DISABLE_L", 738 "LTE_SAR_DETECT_L", 739 "EN_PP3300_LTE_X", 740 "LTE_PWR_OFF_L", 741 "LTE_RESET_L", 742 "TP", 743 "TP"; 744 745 aud_clk_mosi_off: aud-clk-mosi-off-pins { 746 pins-clk-sync { 747 pinmux = <PINMUX_GPIO166__FUNC_GPIO166>, 748 <PINMUX_GPIO167__FUNC_GPIO167>; 749 input-enable; 750 bias-pull-down; 751 }; 752 }; 753 754 aud_clk_mosi_on: aud-clk-mosi-on-pins { 755 pins-clk-sync { 756 pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>, 757 <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>; 758 }; 759 }; 760 761 aud_clk_miso_off: aud-clk-miso-off-pins { 762 pins-clk-sync { 763 pinmux = <PINMUX_GPIO170__FUNC_GPIO170>, 764 <PINMUX_GPIO171__FUNC_GPIO171>; 765 input-enable; 766 bias-pull-down; 767 }; 768 }; 769 770 aud_clk_miso_on: aud-clk-miso-on-pins { 771 pins-clk-sync { 772 pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>, 773 <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>; 774 }; 775 }; 776 777 aud_dat_mosi_off: aud-dat-mosi-off-pins { 778 pins-dat { 779 pinmux = <PINMUX_GPIO168__FUNC_GPIO168>, 780 <PINMUX_GPIO169__FUNC_GPIO169>; 781 input-enable; 782 bias-pull-down; 783 }; 784 }; 785 786 aud_dat_mosi_on: aud-dat-mosi-on-pins { 787 pins-dat { 788 pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>, 789 <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>; 790 }; 791 }; 792 793 aud_dat_miso_off: aud-dat-miso-off-pins { 794 pins-dat { 795 pinmux = <PINMUX_GPIO172__FUNC_GPIO172>, 796 <PINMUX_GPIO173__FUNC_GPIO173>; 797 input-enable; 798 bias-pull-down; 799 }; 800 }; 801 802 aud_dat_miso_on: aud-dat-miso-on-pins { 803 pins-dat { 804 pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>, 805 <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>; 806 input-schmitt-enable; 807 bias-disable; 808 }; 809 }; 810 811 aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { 812 pins-sdata { 813 pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; 814 }; 815 }; 816 817 aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { 818 pins-sdata { 819 pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>; 820 }; 821 }; 822 823 aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { 824 pins-clk-sdata { 825 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>, 826 <PINMUX_GPIO57__FUNC_GPIO57>, 827 <PINMUX_GPIO58__FUNC_GPIO58>, 828 <PINMUX_GPIO59__FUNC_GPIO59>; 829 output-low; 830 }; 831 }; 832 833 aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { 834 pins-clk-sdata { 835 pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>, 836 <PINMUX_GPIO57__FUNC_I2S1_BCK>, 837 <PINMUX_GPIO58__FUNC_I2S1_LRCK>, 838 <PINMUX_GPIO59__FUNC_I2S1_MCK>; 839 }; 840 }; 841 842 aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { 843 pins-cmd-dat { 844 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>, 845 <PINMUX_GPIO27__FUNC_GPIO27>; 846 output-low; 847 }; 848 }; 849 850 aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { 851 pins-clk { 852 pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>, 853 <PINMUX_GPIO27__FUNC_I2S2_LRCK>; 854 drive-strength = <4>; 855 }; 856 }; 857 858 aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { 859 pins-sdata { 860 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 861 output-low; 862 }; 863 }; 864 865 aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { 866 pins-sdata { 867 pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>; 868 drive-strength = <4>; 869 }; 870 }; 871 872 aud_gpio_pcm_off: aud-gpio-pcm-off-pins { 873 pins-clk-sdata { 874 pinmux = <PINMUX_GPIO115__FUNC_GPIO115>, 875 <PINMUX_GPIO116__FUNC_GPIO116>, 876 <PINMUX_GPIO117__FUNC_GPIO117>, 877 <PINMUX_GPIO118__FUNC_GPIO118>; 878 output-low; 879 }; 880 }; 881 882 aud_gpio_pcm_on: aud-gpio-pcm-on-pins { 883 pins-clk-sdata { 884 pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>, 885 <PINMUX_GPIO116__FUNC_PCM_SYNC>, 886 <PINMUX_GPIO117__FUNC_PCM_DI>, 887 <PINMUX_GPIO118__FUNC_PCM_DO>; 888 }; 889 }; 890 891 aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { 892 pins { 893 pinmux = <PINMUX_GPIO23__FUNC_GPIO23>; 894 output-low; 895 }; 896 }; 897 898 bt_pins_reset: bt-reset-pins { 899 pins-bt-reset { 900 pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; 901 output-high; 902 }; 903 }; 904 905 dpi_pins_sleep: dpi-sleep-pins { 906 pins-cmd-dat { 907 pinmux = <PINMUX_GPIO103__FUNC_GPIO103>, 908 <PINMUX_GPIO104__FUNC_GPIO104>, 909 <PINMUX_GPIO105__FUNC_GPIO105>, 910 <PINMUX_GPIO106__FUNC_GPIO106>, 911 <PINMUX_GPIO107__FUNC_GPIO107>, 912 <PINMUX_GPIO108__FUNC_GPIO108>, 913 <PINMUX_GPIO109__FUNC_GPIO109>, 914 <PINMUX_GPIO110__FUNC_GPIO110>, 915 <PINMUX_GPIO111__FUNC_GPIO111>, 916 <PINMUX_GPIO112__FUNC_GPIO112>, 917 <PINMUX_GPIO113__FUNC_GPIO113>, 918 <PINMUX_GPIO114__FUNC_GPIO114>, 919 <PINMUX_GPIO101__FUNC_GPIO101>, 920 <PINMUX_GPIO100__FUNC_GPIO100>, 921 <PINMUX_GPIO102__FUNC_GPIO102>, 922 <PINMUX_GPIO99__FUNC_GPIO99>; 923 drive-strength = <10>; 924 output-low; 925 }; 926 }; 927 928 dpi_pins_default: dpi-default-pins { 929 pins-cmd-dat { 930 pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>, 931 <PINMUX_GPIO104__FUNC_DPI_DATA1>, 932 <PINMUX_GPIO105__FUNC_DPI_DATA2>, 933 <PINMUX_GPIO106__FUNC_DPI_DATA3>, 934 <PINMUX_GPIO107__FUNC_DPI_DATA4>, 935 <PINMUX_GPIO108__FUNC_DPI_DATA5>, 936 <PINMUX_GPIO109__FUNC_DPI_DATA6>, 937 <PINMUX_GPIO110__FUNC_DPI_DATA7>, 938 <PINMUX_GPIO111__FUNC_DPI_DATA8>, 939 <PINMUX_GPIO112__FUNC_DPI_DATA9>, 940 <PINMUX_GPIO113__FUNC_DPI_DATA10>, 941 <PINMUX_GPIO114__FUNC_DPI_DATA11>, 942 <PINMUX_GPIO101__FUNC_DPI_HSYNC>, 943 <PINMUX_GPIO100__FUNC_DPI_VSYNC>, 944 <PINMUX_GPIO102__FUNC_DPI_DE>, 945 <PINMUX_GPIO99__FUNC_DPI_PCLK>; 946 drive-strength = <10>; 947 }; 948 }; 949 950 ec_ap_int: cros-ec-int-pins { 951 pins-ec-ap-int-odl { 952 pinmux = <PINMUX_GPIO13__FUNC_GPIO13>; 953 input-enable; 954 }; 955 }; 956 957 edp_panel_fixed_pins: edp-panel-fixed-pins { 958 pins-vreg-en { 959 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 960 output-high; 961 }; 962 }; 963 964 en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { 965 pins-vreg-en { 966 pinmux = <PINMUX_GPIO39__FUNC_GPIO39>; 967 output-low; 968 }; 969 }; 970 971 gsc_int: gsc-int-pins { 972 pins-gsc-ap-int-odl { 973 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 974 input-enable; 975 }; 976 }; 977 978 i2c0_pins: i2c0-pins { 979 pins-bus { 980 pinmux = <PINMUX_GPIO128__FUNC_SDA0>, 981 <PINMUX_GPIO127__FUNC_SCL0>; 982 bias-disable; 983 drive-strength = <4>; 984 input-enable; 985 }; 986 }; 987 988 i2c1_pins: i2c1-pins { 989 pins-bus { 990 pinmux = <PINMUX_GPIO130__FUNC_SDA1>, 991 <PINMUX_GPIO129__FUNC_SCL1>; 992 bias-disable; 993 drive-strength = <4>; 994 input-enable; 995 }; 996 }; 997 998 i2c2_pins: i2c2-pins { 999 pins-bus { 1000 pinmux = <PINMUX_GPIO132__FUNC_SDA2>, 1001 <PINMUX_GPIO131__FUNC_SCL2>; 1002 bias-disable; 1003 drive-strength = <4>; 1004 input-enable; 1005 }; 1006 }; 1007 1008 i2c3_pins: i2c3-pins { 1009 pins-bus { 1010 pinmux = <PINMUX_GPIO134__FUNC_SDA3>, 1011 <PINMUX_GPIO133__FUNC_SCL3>; 1012 bias-disable; 1013 drive-strength = <4>; 1014 input-enable; 1015 }; 1016 }; 1017 1018 i2c5_pins: i2c5-pins { 1019 pins-bus { 1020 pinmux = <PINMUX_GPIO138__FUNC_SDA5>, 1021 <PINMUX_GPIO137__FUNC_SCL5>; 1022 bias-disable; 1023 drive-strength = <4>; 1024 input-enable; 1025 }; 1026 }; 1027 1028 it6505_pins: it6505-pins { 1029 pins-hpd { 1030 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>; 1031 input-enable; 1032 bias-pull-up; 1033 }; 1034 1035 pins-int { 1036 pinmux = <PINMUX_GPIO8__FUNC_GPIO8>; 1037 input-enable; 1038 bias-pull-up; 1039 }; 1040 1041 pins-reset { 1042 pinmux = <PINMUX_GPIO177__FUNC_GPIO177>; 1043 output-low; 1044 bias-pull-up; 1045 }; 1046 }; 1047 1048 mmc0_pins_default: mmc0-default-pins { 1049 pins-clk { 1050 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1051 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1052 }; 1053 1054 pins-cmd-dat { 1055 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1056 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1057 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1058 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1059 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1060 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1061 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1062 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1063 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1064 input-enable; 1065 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1066 }; 1067 1068 pins-rst { 1069 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1070 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1071 }; 1072 }; 1073 1074 mmc0_pins_uhs: mmc0-uhs-pins { 1075 pins-clk { 1076 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1077 drive-strength = <6>; 1078 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1079 }; 1080 1081 pins-cmd-dat { 1082 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1083 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1084 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1085 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1086 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1087 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1088 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1089 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1090 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1091 input-enable; 1092 drive-strength = <6>; 1093 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1094 }; 1095 1096 pins-ds { 1097 pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>; 1098 drive-strength = <6>; 1099 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1100 }; 1101 1102 pins-rst { 1103 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1104 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1105 }; 1106 }; 1107 1108 mmc1_pins_default: mmc1-default-pins { 1109 pins-clk { 1110 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1111 drive-strength = <6>; 1112 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1113 }; 1114 1115 pins-cmd-dat { 1116 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1117 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1118 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1119 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1120 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1121 input-enable; 1122 drive-strength = <6>; 1123 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1124 }; 1125 }; 1126 1127 mmc1_pins_uhs: mmc1-uhs-pins { 1128 pins-clk { 1129 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1130 drive-strength = <6>; 1131 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1132 }; 1133 1134 pins-cmd-dat { 1135 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1136 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1137 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1138 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1139 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1140 input-enable; 1141 drive-strength = <8>; 1142 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1143 }; 1144 }; 1145 1146 mmc1_pins_eint: mmc1-eint-pins { 1147 pins-dat1 { 1148 pinmux = <PINMUX_GPIO87__FUNC_GPIO87>; 1149 input-enable; 1150 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1151 }; 1152 }; 1153 1154 nor_pins_default: nor-default-pins { 1155 pins-clk-dat { 1156 pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>, 1157 <PINMUX_GPIO61__FUNC_SPINOR_CK>, 1158 <PINMUX_GPIO64__FUNC_SPINOR_IO1>; 1159 drive-strength = <6>; 1160 bias-pull-down; 1161 }; 1162 1163 pins-cs-dat { 1164 pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>, 1165 <PINMUX_GPIO65__FUNC_SPINOR_IO2>, 1166 <PINMUX_GPIO66__FUNC_SPINOR_IO3>; 1167 drive-strength = <6>; 1168 bias-pull-up; 1169 }; 1170 }; 1171 1172 pen_eject: pen-eject-pins { 1173 pins { 1174 pinmux = <PINMUX_GPIO18__FUNC_GPIO18>; 1175 input-enable; 1176 /* External pull-up. */ 1177 bias-disable; 1178 }; 1179 }; 1180 1181 pwm0_pin: disp-pwm-pins { 1182 pins { 1183 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>; 1184 output-high; 1185 }; 1186 }; 1187 1188 speaker_codec_pins_default: speaker-codec-default-pins { 1189 pins-sdb { 1190 pinmux = <PINMUX_GPIO150__FUNC_GPIO150>; 1191 output-low; 1192 }; 1193 }; 1194 1195 scp_pins: scp-default-pins { 1196 pins-scp-uart { 1197 pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>, 1198 <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>; 1199 }; 1200 }; 1201 1202 spi1_pins: spi1-pins { 1203 pins-bus { 1204 pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>, 1205 <PINMUX_GPIO41__FUNC_SPI1_CSB_A>, 1206 <PINMUX_GPIO42__FUNC_SPI1_MO_A>, 1207 <PINMUX_GPIO43__FUNC_SPI1_MI_A>; 1208 bias-disable; 1209 input-enable; 1210 }; 1211 }; 1212 1213 spi2_pins: spi2-pins { 1214 pins-bus { 1215 pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>, 1216 <PINMUX_GPIO45__FUNC_GPIO45>, 1217 <PINMUX_GPIO46__FUNC_SPI2_MO_A>, 1218 <PINMUX_GPIO47__FUNC_SPI2_MI_A>; 1219 bias-disable; 1220 input-enable; 1221 }; 1222 }; 1223 1224 spmi_pins: spmi-pins { 1225 pins-bus { 1226 pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>, 1227 <PINMUX_GPIO184__FUNC_SPMI_SDA>; 1228 }; 1229 }; 1230 1231 touchscreen_pins: touchscreen-pins { 1232 pins-irq { 1233 pinmux = <PINMUX_GPIO12__FUNC_GPIO12>; 1234 input-enable; 1235 bias-pull-up; 1236 }; 1237 1238 pins-reset { 1239 pinmux = <PINMUX_GPIO60__FUNC_GPIO60>; 1240 output-high; 1241 }; 1242 1243 pins-report-sw { 1244 pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; 1245 output-low; 1246 }; 1247 }; 1248 1249 trackpad_pin: trackpad-default-pins { 1250 pins-int-n { 1251 pinmux = <PINMUX_GPIO11__FUNC_GPIO11>; 1252 input-enable; 1253 bias-disable; /* pulled externally */ 1254 }; 1255 }; 1256 1257 wifi_enable_pin: wifi-enable-pins { 1258 pins-wifi-enable { 1259 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1260 }; 1261 }; 1262 1263 wifi_wakeup_pin: wifi-wakeup-pins { 1264 pins-wifi-wakeup { 1265 pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; 1266 input-enable; 1267 }; 1268 }; 1269}; 1270 1271&pwm0 { 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&pwm0_pin>; 1274 status = "okay"; 1275}; 1276 1277&pwrap { 1278 pmic { 1279 compatible = "mediatek,mt6366", "mediatek,mt6358"; 1280 interrupt-controller; 1281 interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; 1282 #interrupt-cells = <2>; 1283 1284 mt6366codec: audio-codec { 1285 compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; 1286 Avdd-supply = <&mt6366_vaud28_reg>; 1287 mediatek,dmic-mode = <1>; /* one-wire */ 1288 }; 1289 1290 mt6366_regulators: regulators { 1291 compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; 1292 vsys-ldo1-supply = <&pp4200_z2>; 1293 vsys-ldo2-supply = <&pp4200_z2>; 1294 vsys-ldo3-supply = <&pp4200_z2>; 1295 vsys-vcore-supply = <&pp4200_z2>; 1296 vsys-vdram1-supply = <&pp4200_z2>; 1297 vsys-vgpu-supply = <&pp4200_z2>; 1298 vsys-vmodem-supply = <&pp4200_z2>; 1299 vsys-vpa-supply = <&pp4200_z2>; 1300 vsys-vproc11-supply = <&pp4200_z2>; 1301 vsys-vproc12-supply = <&pp4200_z2>; 1302 vsys-vs1-supply = <&pp4200_z2>; 1303 vsys-vs2-supply = <&pp4200_z2>; 1304 vs1-ldo1-supply = <&mt6366_vs1_reg>; 1305 vs2-ldo1-supply = <&mt6366_vdram1_reg>; 1306 vs2-ldo2-supply = <&mt6366_vs2_reg>; 1307 vs2-ldo3-supply = <&mt6366_vs2_reg>; 1308 1309 vcore { 1310 regulator-name = "pp0750_dvdd_core"; 1311 regulator-min-microvolt = <550000>; 1312 regulator-max-microvolt = <800000>; 1313 regulator-ramp-delay = <6250>; 1314 regulator-enable-ramp-delay = <200>; 1315 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1316 MT6397_BUCK_MODE_FORCE_PWM>; 1317 regulator-always-on; 1318 }; 1319 1320 mt6366_vdram1_reg: vdram1 { 1321 regulator-name = "pp1125_emi_vdd2"; 1322 regulator-min-microvolt = <1125000>; 1323 regulator-max-microvolt = <1125000>; 1324 regulator-ramp-delay = <12500>; 1325 regulator-enable-ramp-delay = <0>; 1326 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1327 MT6397_BUCK_MODE_FORCE_PWM>; 1328 regulator-always-on; 1329 }; 1330 1331 mt6366_vgpu_reg: vgpu { 1332 /* 1333 * Called "ppvar_dvdd_gpu" in the schematic. 1334 * Called "ppvar_dvdd_vgpu" here to match 1335 * regulator coupling requirements. 1336 */ 1337 regulator-name = "ppvar_dvdd_vgpu"; 1338 regulator-min-microvolt = <500000>; 1339 regulator-max-microvolt = <950000>; 1340 regulator-ramp-delay = <6250>; 1341 regulator-enable-ramp-delay = <200>; 1342 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1343 MT6397_BUCK_MODE_FORCE_PWM>; 1344 regulator-coupled-with = <&mt6366_vsram_gpu_reg>; 1345 regulator-coupled-max-spread = <100000>; 1346 }; 1347 1348 mt6366_vproc11_reg: vproc11 { 1349 regulator-name = "ppvar_dvdd_proc_bc_mt6366"; 1350 regulator-min-microvolt = <600000>; 1351 regulator-max-microvolt = <1200000>; 1352 regulator-ramp-delay = <6250>; 1353 regulator-enable-ramp-delay = <200>; 1354 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1355 MT6397_BUCK_MODE_FORCE_PWM>; 1356 regulator-always-on; 1357 }; 1358 1359 mt6366_vproc12_reg: vproc12 { 1360 regulator-name = "ppvar_dvdd_proc_lc"; 1361 regulator-min-microvolt = <600000>; 1362 regulator-max-microvolt = <1200000>; 1363 regulator-ramp-delay = <6250>; 1364 regulator-enable-ramp-delay = <200>; 1365 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1366 MT6397_BUCK_MODE_FORCE_PWM>; 1367 regulator-always-on; 1368 }; 1369 1370 mt6366_vs1_reg: vs1 { 1371 regulator-name = "pp2000_vs1"; 1372 regulator-min-microvolt = <2000000>; 1373 regulator-max-microvolt = <2000000>; 1374 regulator-ramp-delay = <12500>; 1375 regulator-enable-ramp-delay = <0>; 1376 regulator-always-on; 1377 }; 1378 1379 mt6366_vs2_reg: vs2 { 1380 regulator-name = "pp1350_vs2"; 1381 regulator-min-microvolt = <1350000>; 1382 regulator-max-microvolt = <1350000>; 1383 regulator-ramp-delay = <12500>; 1384 regulator-enable-ramp-delay = <0>; 1385 regulator-always-on; 1386 }; 1387 1388 va12 { 1389 regulator-name = "pp1200_va12"; 1390 regulator-min-microvolt = <1200000>; 1391 regulator-max-microvolt = <1200000>; 1392 regulator-enable-ramp-delay = <270>; 1393 regulator-always-on; 1394 }; 1395 1396 mt6366_vaud28_reg: vaud28 { 1397 regulator-name = "pp2800_vaud28"; 1398 regulator-min-microvolt = <2800000>; 1399 regulator-max-microvolt = <2800000>; 1400 regulator-enable-ramp-delay = <270>; 1401 }; 1402 1403 mt6366_vaux18_reg: vaux18 { 1404 regulator-name = "pp1840_vaux18"; 1405 regulator-min-microvolt = <1800000>; 1406 regulator-max-microvolt = <1840000>; 1407 regulator-enable-ramp-delay = <270>; 1408 }; 1409 1410 mt6366_vbif28_reg: vbif28 { 1411 regulator-name = "pp2800_vbif28"; 1412 regulator-min-microvolt = <2800000>; 1413 regulator-max-microvolt = <2800000>; 1414 regulator-enable-ramp-delay = <270>; 1415 }; 1416 1417 mt6366_vcn18_reg: vcn18 { 1418 regulator-name = "pp1800_vcn18_x"; 1419 regulator-min-microvolt = <1800000>; 1420 regulator-max-microvolt = <1800000>; 1421 regulator-enable-ramp-delay = <270>; 1422 }; 1423 1424 mt6366_vcn28_reg: vcn28 { 1425 regulator-name = "pp2800_vcn28_x"; 1426 regulator-min-microvolt = <2800000>; 1427 regulator-max-microvolt = <2800000>; 1428 regulator-enable-ramp-delay = <270>; 1429 }; 1430 1431 mt6366_vefuse_reg: vefuse { 1432 regulator-name = "pp1800_vefuse"; 1433 regulator-min-microvolt = <1800000>; 1434 regulator-max-microvolt = <1800000>; 1435 regulator-enable-ramp-delay = <270>; 1436 }; 1437 1438 mt6366_vfe28_reg: vfe28 { 1439 regulator-name = "pp2800_vfe28_x"; 1440 regulator-min-microvolt = <2800000>; 1441 regulator-max-microvolt = <2800000>; 1442 regulator-enable-ramp-delay = <270>; 1443 }; 1444 1445 mt6366_vemc_reg: vemc { 1446 regulator-name = "pp3000_vemc"; 1447 regulator-min-microvolt = <3000000>; 1448 regulator-max-microvolt = <3000000>; 1449 regulator-enable-ramp-delay = <60>; 1450 }; 1451 1452 mt6366_vibr_reg: vibr { 1453 regulator-name = "pp2800_vibr_x"; 1454 regulator-min-microvolt = <2800000>; 1455 regulator-max-microvolt = <2800000>; 1456 regulator-enable-ramp-delay = <60>; 1457 }; 1458 1459 mt6366_vio18_reg: vio18 { 1460 regulator-name = "pp1800_vio18_s3"; 1461 regulator-min-microvolt = <1800000>; 1462 regulator-max-microvolt = <1800000>; 1463 regulator-enable-ramp-delay = <2700>; 1464 regulator-always-on; 1465 }; 1466 1467 mt6366_vio28_reg: vio28 { 1468 regulator-name = "pp2800_vio28_x"; 1469 regulator-min-microvolt = <2800000>; 1470 regulator-max-microvolt = <2800000>; 1471 regulator-enable-ramp-delay = <270>; 1472 }; 1473 1474 mt6366_vm18_reg: vm18 { 1475 regulator-name = "pp1800_emi_vdd1"; 1476 regulator-min-microvolt = <1800000>; 1477 regulator-max-microvolt = <1840000>; 1478 regulator-enable-ramp-delay = <325>; 1479 regulator-always-on; 1480 }; 1481 1482 mt6366_vmc_reg: vmc { 1483 regulator-name = "pp3000_vmc"; 1484 regulator-min-microvolt = <3000000>; 1485 regulator-max-microvolt = <3000000>; 1486 regulator-enable-ramp-delay = <60>; 1487 }; 1488 1489 mt6366_vmddr_reg: vmddr { 1490 regulator-name = "pm0750_emi_vmddr"; 1491 regulator-min-microvolt = <700000>; 1492 regulator-max-microvolt = <750000>; 1493 regulator-enable-ramp-delay = <325>; 1494 regulator-always-on; 1495 }; 1496 1497 mt6366_vmch_reg: vmch { 1498 regulator-name = "pp3000_vmch"; 1499 regulator-min-microvolt = <3000000>; 1500 regulator-max-microvolt = <3000000>; 1501 regulator-enable-ramp-delay = <60>; 1502 }; 1503 1504 mt6366_vcn33_reg: vcn33 { 1505 regulator-name = "pp3300_vcn33_x"; 1506 regulator-min-microvolt = <3300000>; 1507 regulator-max-microvolt = <3300000>; 1508 regulator-enable-ramp-delay = <270>; 1509 }; 1510 1511 vdram2 { 1512 regulator-name = "pp0600_emi_vddq"; 1513 regulator-min-microvolt = <600000>; 1514 regulator-max-microvolt = <600000>; 1515 regulator-enable-ramp-delay = <3300>; 1516 regulator-always-on; 1517 }; 1518 1519 mt6366_vrf12_reg: vrf12 { 1520 regulator-name = "pp1200_vrf12_x"; 1521 regulator-min-microvolt = <1200000>; 1522 regulator-max-microvolt = <1200000>; 1523 regulator-enable-ramp-delay = <120>; 1524 }; 1525 1526 mt6366_vrf18_reg: vrf18 { 1527 regulator-name = "pp1800_vrf18_x"; 1528 regulator-min-microvolt = <1800000>; 1529 regulator-max-microvolt = <1800000>; 1530 regulator-enable-ramp-delay = <120>; 1531 }; 1532 1533 vsim1 { 1534 regulator-name = "pp1860_vsim1_x"; 1535 regulator-min-microvolt = <1800000>; 1536 regulator-max-microvolt = <1860000>; 1537 regulator-enable-ramp-delay = <540>; 1538 }; 1539 1540 mt6366_vsim2_reg: vsim2 { 1541 regulator-name = "pp2760_vsim2_x"; 1542 regulator-min-microvolt = <2700000>; 1543 regulator-max-microvolt = <2760000>; 1544 regulator-enable-ramp-delay = <540>; 1545 }; 1546 1547 mt6366_vsram_gpu_reg: vsram-gpu { 1548 regulator-name = "pp0900_dvdd_sram_gpu"; 1549 regulator-min-microvolt = <850000>; 1550 regulator-max-microvolt = <1050000>; 1551 regulator-ramp-delay = <6250>; 1552 regulator-enable-ramp-delay = <240>; 1553 regulator-coupled-with = <&mt6366_vgpu_reg>; 1554 regulator-coupled-max-spread = <100000>; 1555 }; 1556 1557 mt6366_vsram_others_reg: vsram-others { 1558 regulator-name = "pp0900_dvdd_sram_core"; 1559 regulator-min-microvolt = <900000>; 1560 regulator-max-microvolt = <900000>; 1561 regulator-ramp-delay = <6250>; 1562 regulator-enable-ramp-delay = <240>; 1563 regulator-always-on; 1564 }; 1565 1566 mt6366_vsram_proc11_reg: vsram-proc11 { 1567 regulator-name = "pp0900_dvdd_sram_bc"; 1568 regulator-min-microvolt = <850000>; 1569 regulator-max-microvolt = <1120000>; 1570 regulator-ramp-delay = <6250>; 1571 regulator-enable-ramp-delay = <240>; 1572 regulator-always-on; 1573 }; 1574 1575 mt6366_vsram_proc12_reg: vsram-proc12 { 1576 regulator-name = "pp0900_dvdd_sram_lc"; 1577 regulator-min-microvolt = <850000>; 1578 regulator-max-microvolt = <1120000>; 1579 regulator-ramp-delay = <6250>; 1580 regulator-enable-ramp-delay = <240>; 1581 regulator-always-on; 1582 }; 1583 1584 vusb { 1585 regulator-name = "pp3070_vusb"; 1586 regulator-min-microvolt = <3000000>; 1587 regulator-max-microvolt = <3070000>; 1588 regulator-enable-ramp-delay = <270>; 1589 regulator-always-on; 1590 }; 1591 1592 vxo22 { 1593 regulator-name = "pp2240_vxo22"; 1594 regulator-min-microvolt = <2200000>; 1595 regulator-max-microvolt = <2240000>; 1596 regulator-enable-ramp-delay = <120>; 1597 /* Feeds DCXO internally */ 1598 regulator-always-on; 1599 }; 1600 }; 1601 1602 rtc { 1603 compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; 1604 }; 1605 }; 1606}; 1607 1608&scp { 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&scp_pins>; 1611 firmware-name = "mediatek/mt8186/scp.img"; 1612 memory-region = <&scp_mem>; 1613 status = "okay"; 1614 1615 cros-ec-rpmsg { 1616 compatible = "google,cros-ec-rpmsg"; 1617 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1618 }; 1619}; 1620 1621&spi1 { 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&spi1_pins>; 1624 mediatek,pad-select = <0>; 1625 status = "okay"; 1626 1627 cros_ec: ec@0 { 1628 compatible = "google,cros-ec-spi"; 1629 reg = <0>; 1630 interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&ec_ap_int>; 1633 spi-max-frequency = <1000000>; 1634 1635 i2c_tunnel: i2c-tunnel { 1636 compatible = "google,cros-ec-i2c-tunnel"; 1637 google,remote-bus = <1>; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 }; 1641 1642 typec { 1643 compatible = "google,cros-ec-typec"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 1647 usb_c0: connector@0 { 1648 compatible = "usb-c-connector"; 1649 reg = <0>; 1650 label = "left"; 1651 power-role = "dual"; 1652 data-role = "host"; 1653 try-power-role = "source"; 1654 }; 1655 1656 usb_c1: connector@1 { 1657 compatible = "usb-c-connector"; 1658 reg = <1>; 1659 label = "right"; 1660 power-role = "dual"; 1661 data-role = "host"; 1662 try-power-role = "source"; 1663 }; 1664 }; 1665 1666 usbc_extcon: extcon0 { 1667 compatible = "google,extcon-usbc-cros-ec"; 1668 google,usb-port-id = <0>; 1669 }; 1670 }; 1671}; 1672 1673&spi2 { 1674 pinctrl-names = "default"; 1675 pinctrl-0 = <&spi2_pins>; 1676 cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; 1677 mediatek,pad-select = <0>; 1678 status = "okay"; 1679 1680 tpm@0 { 1681 compatible = "google,cr50"; 1682 reg = <0>; 1683 interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&gsc_int>; 1686 spi-max-frequency = <1000000>; 1687 }; 1688}; 1689 1690&ssusb0 { 1691 status = "okay"; 1692}; 1693 1694&ssusb1 { 1695 status = "okay"; 1696}; 1697 1698&u3phy0 { 1699 status = "okay"; 1700}; 1701 1702&u3phy1 { 1703 status = "okay"; 1704}; 1705 1706&uart0 { 1707 status = "okay"; 1708}; 1709 1710&usb_host0 { 1711 vbus-supply = <&pp3300_s3>; 1712 status = "okay"; 1713}; 1714 1715&usb_host1 { 1716 vbus-supply = <&usb_p1_vbus>; 1717 status = "okay"; 1718}; 1719 1720&watchdog { 1721 mediatek,reset-by-toprgu; 1722}; 1723 1724#include <arm/cros-ec-keyboard.dtsi> 1725#include <arm/cros-ec-sbs.dtsi> 1726