1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Author: Sam.Shih <sam.shih@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mt7986-clk.h> 10#include <dt-bindings/reset/mt7986-resets.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt7986a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a53"; 24 reg = <0x0>; 25 device_type = "cpu"; 26 enable-method = "psci"; 27 #cooling-cells = <2>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a53"; 32 reg = <0x1>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 #cooling-cells = <2>; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 reg = <0x2>; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 #cooling-cells = <2>; 44 }; 45 46 cpu3: cpu@3 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x3>; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 #cooling-cells = <2>; 52 }; 53 }; 54 55 clk40m: oscillator-40m { 56 compatible = "fixed-clock"; 57 clock-frequency = <40000000>; 58 #clock-cells = <0>; 59 clock-output-names = "clkxtal"; 60 }; 61 62 psci { 63 compatible = "arm,psci-0.2"; 64 method = "smc"; 65 }; 66 67 reserved-memory { 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 72 secmon_reserved: secmon@43000000 { 73 reg = <0 0x43000000 0 0x30000>; 74 no-map; 75 }; 76 77 wmcpu_emi: wmcpu-reserved@4fc00000 { 78 no-map; 79 reg = <0 0x4fc00000 0 0x00100000>; 80 }; 81 82 wo_emi0: wo-emi@4fd00000 { 83 reg = <0 0x4fd00000 0 0x40000>; 84 no-map; 85 }; 86 87 wo_emi1: wo-emi@4fd40000 { 88 reg = <0 0x4fd40000 0 0x40000>; 89 no-map; 90 }; 91 92 wo_ilm0: wo-ilm@151e0000 { 93 reg = <0 0x151e0000 0 0x8000>; 94 no-map; 95 }; 96 97 wo_ilm1: wo-ilm@151f0000 { 98 reg = <0 0x151f0000 0 0x8000>; 99 no-map; 100 }; 101 102 wo_data: wo-data@4fd80000 { 103 reg = <0 0x4fd80000 0 0x240000>; 104 no-map; 105 }; 106 107 wo_dlm0: wo-dlm@151e8000 { 108 reg = <0 0x151e8000 0 0x2000>; 109 no-map; 110 }; 111 112 wo_dlm1: wo-dlm@151f8000 { 113 reg = <0 0x151f8000 0 0x2000>; 114 no-map; 115 }; 116 117 wo_boot: wo-boot@15194000 { 118 reg = <0 0x15194000 0 0x1000>; 119 no-map; 120 }; 121 122 }; 123 124 soc { 125 compatible = "simple-bus"; 126 ranges; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 130 gic: interrupt-controller@c000000 { 131 compatible = "arm,gic-v3"; 132 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 133 <0 0x0c080000 0 0x80000>, /* GICR */ 134 <0 0x0c400000 0 0x2000>, /* GICC */ 135 <0 0x0c410000 0 0x1000>, /* GICH */ 136 <0 0x0c420000 0 0x2000>; /* GICV */ 137 interrupt-parent = <&gic>; 138 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-controller; 140 #interrupt-cells = <3>; 141 }; 142 143 infracfg: infracfg@10001000 { 144 compatible = "mediatek,mt7986-infracfg", "syscon"; 145 reg = <0 0x10001000 0 0x1000>; 146 #clock-cells = <1>; 147 #reset-cells = <1>; 148 }; 149 150 wed_pcie: wed-pcie@10003000 { 151 compatible = "mediatek,mt7986-wed-pcie", 152 "syscon"; 153 reg = <0 0x10003000 0 0x10>; 154 }; 155 156 topckgen: topckgen@1001b000 { 157 compatible = "mediatek,mt7986-topckgen", "syscon"; 158 reg = <0 0x1001B000 0 0x1000>; 159 #clock-cells = <1>; 160 }; 161 162 watchdog: watchdog@1001c000 { 163 compatible = "mediatek,mt7986-wdt"; 164 reg = <0 0x1001c000 0 0x1000>; 165 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 166 #reset-cells = <1>; 167 status = "disabled"; 168 }; 169 170 apmixedsys: apmixedsys@1001e000 { 171 compatible = "mediatek,mt7986-apmixedsys"; 172 reg = <0 0x1001E000 0 0x1000>; 173 #clock-cells = <1>; 174 }; 175 176 pio: pinctrl@1001f000 { 177 compatible = "mediatek,mt7986a-pinctrl"; 178 reg = <0 0x1001f000 0 0x1000>, 179 <0 0x11c30000 0 0x1000>, 180 <0 0x11c40000 0 0x1000>, 181 <0 0x11e20000 0 0x1000>, 182 <0 0x11e30000 0 0x1000>, 183 <0 0x11f00000 0 0x1000>, 184 <0 0x11f10000 0 0x1000>, 185 <0 0x1000b000 0 0x1000>; 186 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", 187 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 gpio-ranges = <&pio 0 0 100>; 191 interrupt-controller; 192 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-parent = <&gic>; 194 #interrupt-cells = <2>; 195 }; 196 197 pwm: pwm@10048000 { 198 compatible = "mediatek,mt7986-pwm"; 199 reg = <0 0x10048000 0 0x1000>; 200 #pwm-cells = <2>; 201 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&topckgen CLK_TOP_PWM_SEL>, 203 <&infracfg CLK_INFRA_PWM_STA>, 204 <&infracfg CLK_INFRA_PWM1_CK>, 205 <&infracfg CLK_INFRA_PWM2_CK>; 206 clock-names = "top", "main", "pwm1", "pwm2"; 207 status = "disabled"; 208 }; 209 210 sgmiisys0: syscon@10060000 { 211 compatible = "mediatek,mt7986-sgmiisys_0", 212 "syscon"; 213 reg = <0 0x10060000 0 0x1000>; 214 #clock-cells = <1>; 215 }; 216 217 sgmiisys1: syscon@10070000 { 218 compatible = "mediatek,mt7986-sgmiisys_1", 219 "syscon"; 220 reg = <0 0x10070000 0 0x1000>; 221 #clock-cells = <1>; 222 }; 223 224 trng: rng@1020f000 { 225 compatible = "mediatek,mt7986-rng", 226 "mediatek,mt7623-rng"; 227 reg = <0 0x1020f000 0 0x100>; 228 clocks = <&infracfg CLK_INFRA_TRNG_CK>; 229 clock-names = "rng"; 230 status = "disabled"; 231 }; 232 233 crypto: crypto@10320000 { 234 compatible = "inside-secure,safexcel-eip97"; 235 reg = <0 0x10320000 0 0x40000>; 236 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 240 interrupt-names = "ring0", "ring1", "ring2", "ring3"; 241 clocks = <&infracfg CLK_INFRA_EIP97_CK>; 242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; 243 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; 244 status = "disabled"; 245 }; 246 247 uart0: serial@11002000 { 248 compatible = "mediatek,mt7986-uart", 249 "mediatek,mt6577-uart"; 250 reg = <0 0x11002000 0 0x400>; 251 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&infracfg CLK_INFRA_UART0_SEL>, 253 <&infracfg CLK_INFRA_UART0_CK>; 254 clock-names = "baud", "bus"; 255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, 256 <&infracfg CLK_INFRA_UART0_SEL>; 257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, 258 <&topckgen CLK_TOP_UART_SEL>; 259 status = "disabled"; 260 }; 261 262 uart1: serial@11003000 { 263 compatible = "mediatek,mt7986-uart", 264 "mediatek,mt6577-uart"; 265 reg = <0 0x11003000 0 0x400>; 266 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&infracfg CLK_INFRA_UART1_SEL>, 268 <&infracfg CLK_INFRA_UART1_CK>; 269 clock-names = "baud", "bus"; 270 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; 271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 272 status = "disabled"; 273 }; 274 275 uart2: serial@11004000 { 276 compatible = "mediatek,mt7986-uart", 277 "mediatek,mt6577-uart"; 278 reg = <0 0x11004000 0 0x400>; 279 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&infracfg CLK_INFRA_UART2_SEL>, 281 <&infracfg CLK_INFRA_UART2_CK>; 282 clock-names = "baud", "bus"; 283 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; 284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 285 status = "disabled"; 286 }; 287 288 i2c0: i2c@11008000 { 289 compatible = "mediatek,mt7986-i2c"; 290 reg = <0 0x11008000 0 0x90>, 291 <0 0x10217080 0 0x80>; 292 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 293 clock-div = <5>; 294 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 295 <&infracfg CLK_INFRA_AP_DMA_CK>; 296 clock-names = "main", "dma"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 spi0: spi@1100a000 { 303 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 304 reg = <0 0x1100a000 0 0x100>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&topckgen CLK_TOP_MPLL_D2>, 309 <&topckgen CLK_TOP_SPI_SEL>, 310 <&infracfg CLK_INFRA_SPI0_CK>, 311 <&infracfg CLK_INFRA_SPI0_HCK_CK>; 312 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 313 status = "disabled"; 314 }; 315 316 spi1: spi@1100b000 { 317 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 318 reg = <0 0x1100b000 0 0x100>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&topckgen CLK_TOP_MPLL_D2>, 323 <&topckgen CLK_TOP_SPIM_MST_SEL>, 324 <&infracfg CLK_INFRA_SPI1_CK>, 325 <&infracfg CLK_INFRA_SPI1_HCK_CK>; 326 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 327 status = "disabled"; 328 }; 329 330 thermal: thermal@1100c800 { 331 compatible = "mediatek,mt7986-thermal"; 332 reg = <0 0x1100c800 0 0x800>; 333 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&infracfg CLK_INFRA_THERM_CK>, 335 <&infracfg CLK_INFRA_ADC_26M_CK>; 336 clock-names = "therm", "auxadc"; 337 nvmem-cells = <&thermal_calibration>; 338 nvmem-cell-names = "calibration-data"; 339 #thermal-sensor-cells = <1>; 340 mediatek,auxadc = <&auxadc>; 341 mediatek,apmixedsys = <&apmixedsys>; 342 }; 343 344 auxadc: adc@1100d000 { 345 compatible = "mediatek,mt7986-auxadc"; 346 reg = <0 0x1100d000 0 0x1000>; 347 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; 348 clock-names = "main"; 349 #io-channel-cells = <1>; 350 status = "disabled"; 351 }; 352 353 ssusb: usb@11200000 { 354 compatible = "mediatek,mt7986-xhci", 355 "mediatek,mtk-xhci"; 356 reg = <0 0x11200000 0 0x2e00>, 357 <0 0x11203e00 0 0x0100>; 358 reg-names = "mac", "ippc"; 359 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, 361 <&infracfg CLK_INFRA_IUSB_CK>, 362 <&infracfg CLK_INFRA_IUSB_133_CK>, 363 <&infracfg CLK_INFRA_IUSB_66M_CK>, 364 <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 365 clock-names = "sys_ck", 366 "ref_ck", 367 "mcu_ck", 368 "dma_ck", 369 "xhci_ck"; 370 phys = <&u2port0 PHY_TYPE_USB2>, 371 <&u3port0 PHY_TYPE_USB3>, 372 <&u2port1 PHY_TYPE_USB2>; 373 status = "disabled"; 374 }; 375 376 mmc0: mmc@11230000 { 377 compatible = "mediatek,mt7986-mmc"; 378 reg = <0 0x11230000 0 0x1000>, 379 <0 0x11c20000 0 0x1000>; 380 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 381 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, 382 <&topckgen CLK_TOP_EMMC_250M_SEL>; 383 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>, 384 <&topckgen CLK_TOP_NET1PLL_D5_D2>; 385 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, 386 <&infracfg CLK_INFRA_MSDC_HCK_CK>, 387 <&infracfg CLK_INFRA_MSDC_CK>, 388 <&infracfg CLK_INFRA_MSDC_133M_CK>, 389 <&infracfg CLK_INFRA_MSDC_66M_CK>; 390 clock-names = "source", "hclk", "source_cg", "bus_clk", 391 "sys_cg"; 392 status = "disabled"; 393 }; 394 395 pcie: pcie@11280000 { 396 compatible = "mediatek,mt7986-pcie", 397 "mediatek,mt8192-pcie"; 398 reg = <0x00 0x11280000 0x00 0x4000>; 399 reg-names = "pcie-mac"; 400 ranges = <0x82000000 0x00 0x20000000 0x00 401 0x20000000 0x00 0x10000000>; 402 device_type = "pci"; 403 #address-cells = <3>; 404 #size-cells = <2>; 405 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 406 bus-range = <0x00 0xff>; 407 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, 408 <&infracfg CLK_INFRA_IPCIE_CK>, 409 <&infracfg CLK_INFRA_IPCIER_CK>, 410 <&infracfg CLK_INFRA_IPCIEB_CK>; 411 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; 412 413 phys = <&pcie_port PHY_TYPE_PCIE>; 414 phy-names = "pcie-phy"; 415 416 #interrupt-cells = <1>; 417 interrupt-map-mask = <0 0 0 0x7>; 418 interrupt-map = <0 0 0 1 &pcie_intc 0>, 419 <0 0 0 2 &pcie_intc 1>, 420 <0 0 0 3 &pcie_intc 2>, 421 <0 0 0 4 &pcie_intc 3>; 422 status = "disabled"; 423 424 pcie_intc: interrupt-controller { 425 #address-cells = <0>; 426 #interrupt-cells = <1>; 427 interrupt-controller; 428 }; 429 }; 430 431 pcie_phy: t-phy@11c00000 { 432 compatible = "mediatek,mt7986-tphy", 433 "mediatek,generic-tphy-v2"; 434 ranges = <0 0 0x11c00000 0x20000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 status = "disabled"; 438 439 pcie_port: pcie-phy@0 { 440 reg = <0 0x20000>; 441 clocks = <&clk40m>; 442 clock-names = "ref"; 443 #phy-cells = <1>; 444 }; 445 }; 446 447 efuse: efuse@11d00000 { 448 compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; 449 reg = <0 0x11d00000 0 0x1000>; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 453 soc-uuid@140 { 454 reg = <0x140 0x8>; 455 }; 456 457 thermal_calibration: calib@274 { 458 reg = <0x274 0xc>; 459 }; 460 }; 461 462 usb_phy: t-phy@11e10000 { 463 compatible = "mediatek,mt7986-tphy", 464 "mediatek,generic-tphy-v2"; 465 ranges = <0 0 0x11e10000 0x1700>; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 status = "disabled"; 469 470 u2port0: usb-phy@0 { 471 reg = <0x0 0x700>; 472 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 473 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 474 clock-names = "ref", "da_ref"; 475 #phy-cells = <1>; 476 }; 477 478 u3port0: usb-phy@700 { 479 reg = <0x700 0x900>; 480 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; 481 clock-names = "ref"; 482 #phy-cells = <1>; 483 }; 484 485 u2port1: usb-phy@1000 { 486 reg = <0x1000 0x700>; 487 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 488 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 489 clock-names = "ref", "da_ref"; 490 #phy-cells = <1>; 491 }; 492 }; 493 494 ethsys: syscon@15000000 { 495 compatible = "mediatek,mt7986-ethsys", 496 "syscon"; 497 reg = <0 0x15000000 0 0x1000>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 }; 501 502 wed0: wed@15010000 { 503 compatible = "mediatek,mt7986-wed", 504 "syscon"; 505 reg = <0 0x15010000 0 0x1000>; 506 interrupt-parent = <&gic>; 507 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 508 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, 509 <&wo_data>, <&wo_boot>; 510 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 511 "wo-data", "wo-boot"; 512 mediatek,wo-ccif = <&wo_ccif0>; 513 }; 514 515 wed1: wed@15011000 { 516 compatible = "mediatek,mt7986-wed", 517 "syscon"; 518 reg = <0 0x15011000 0 0x1000>; 519 interrupt-parent = <&gic>; 520 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 521 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, 522 <&wo_data>, <&wo_boot>; 523 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 524 "wo-data", "wo-boot"; 525 mediatek,wo-ccif = <&wo_ccif1>; 526 }; 527 528 eth: ethernet@15100000 { 529 compatible = "mediatek,mt7986-eth"; 530 reg = <0 0x15100000 0 0x40000>; 531 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", 540 "pdma1", "pdma2", "pdma3"; 541 clocks = <ðsys CLK_ETH_FE_EN>, 542 <ðsys CLK_ETH_GP2_EN>, 543 <ðsys CLK_ETH_GP1_EN>, 544 <ðsys CLK_ETH_WOCPU1_EN>, 545 <ðsys CLK_ETH_WOCPU0_EN>, 546 <&sgmiisys0 CLK_SGMII0_TX250M_EN>, 547 <&sgmiisys0 CLK_SGMII0_RX250M_EN>, 548 <&sgmiisys0 CLK_SGMII0_CDR_REF>, 549 <&sgmiisys0 CLK_SGMII0_CDR_FB>, 550 <&sgmiisys1 CLK_SGMII1_TX250M_EN>, 551 <&sgmiisys1 CLK_SGMII1_RX250M_EN>, 552 <&sgmiisys1 CLK_SGMII1_CDR_REF>, 553 <&sgmiisys1 CLK_SGMII1_CDR_FB>, 554 <&topckgen CLK_TOP_NETSYS_SEL>, 555 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 556 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", 557 "sgmii_tx250m", "sgmii_rx250m", 558 "sgmii_cdr_ref", "sgmii_cdr_fb", 559 "sgmii2_tx250m", "sgmii2_rx250m", 560 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 561 "netsys0", "netsys1"; 562 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 563 <&topckgen CLK_TOP_SGM_325M_SEL>; 564 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 565 <&apmixedsys CLK_APMIXED_SGMPLL>; 566 sram = <ð_sram>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 mediatek,ethsys = <ðsys>; 570 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 571 mediatek,wed-pcie = <&wed_pcie>; 572 mediatek,wed = <&wed0>, <&wed1>; 573 status = "disabled"; 574 }; 575 576 /*15100000+0x40000*/ 577 eth_sram: sram@15140000 { 578 compatible = "mmio-sram"; 579 reg = <0 0x15140000 0 0x40000>; 580 #address-cells = <1>; 581 #size-cells = <1>; 582 ranges = <0 0x15140000 0 0x40000>; 583 }; 584 585 wo_ccif0: syscon@151a5000 { 586 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 587 reg = <0 0x151a5000 0 0x1000>; 588 interrupt-parent = <&gic>; 589 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 590 }; 591 592 wo_ccif1: syscon@151ad000 { 593 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 594 reg = <0 0x151ad000 0 0x1000>; 595 interrupt-parent = <&gic>; 596 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 wifi: wifi@18000000 { 600 compatible = "mediatek,mt7986-wmac"; 601 reg = <0 0x18000000 0 0x1000000>, 602 <0 0x10003000 0 0x1000>, 603 <0 0x11d10000 0 0x1000>; 604 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 605 reset-names = "consys"; 606 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, 607 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 608 clock-names = "mcu", "ap2conn"; 609 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 613 memory-region = <&wmcpu_emi>; 614 }; 615 }; 616 617 thermal-zones { 618 cpu_thermal: cpu-thermal { 619 polling-delay-passive = <1000>; 620 polling-delay = <1000>; 621 thermal-sensors = <&thermal 0>; 622 623 trips { 624 cpu_trip_crit: crit { 625 temperature = <125000>; 626 hysteresis = <2000>; 627 type = "critical"; 628 }; 629 630 cpu_trip_hot: hot { 631 temperature = <120000>; 632 hysteresis = <2000>; 633 type = "hot"; 634 }; 635 636 cpu_trip_active_high: active-high { 637 temperature = <115000>; 638 hysteresis = <2000>; 639 type = "active"; 640 }; 641 642 cpu_trip_active_med: active-med { 643 temperature = <85000>; 644 hysteresis = <2000>; 645 type = "active"; 646 }; 647 648 cpu_trip_active_low: active-low { 649 temperature = <60000>; 650 hysteresis = <2000>; 651 type = "active"; 652 }; 653 }; 654 }; 655 }; 656 657 timer { 658 compatible = "arm,armv8-timer"; 659 interrupt-parent = <&gic>; 660 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 661 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 662 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 663 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 664 }; 665}; 666