1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2025 Max Shevchenko <wctrl@proton.me> 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&sysirq>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 enable-method = "mediatek,mt6589-smp"; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a7"; 22 reg = <0x0>; 23 }; 24 cpu@1 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a7"; 27 reg = <0x1>; 28 }; 29 }; 30 31 uart_clk: dummy26m { 32 compatible = "fixed-clock"; 33 clock-frequency = <26000000>; 34 #clock-cells = <0>; 35 }; 36 37 system_clk: dummy13m { 38 compatible = "fixed-clock"; 39 clock-frequency = <13000000>; 40 #clock-cells = <0>; 41 }; 42 43 rtc_clk: dummy32k { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 49 soc { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 ranges; 54 55 watchdog: watchdog@10007000 { 56 compatible = "mediatek,mt6572-wdt", "mediatek,mt6589-wdt"; 57 reg = <0x10007000 0x100>; 58 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 59 timeout-sec = <15>; 60 #reset-cells = <1>; 61 }; 62 63 timer: timer@10008000 { 64 compatible = "mediatek,mt6572-timer", "mediatek,mt6577-timer"; 65 reg = <0x10008000 0x80>; 66 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 67 clocks = <&system_clk>, <&rtc_clk>; 68 clock-names = "system-clk", "rtc-clk"; 69 }; 70 71 sysirq: interrupt-controller@10200100 { 72 compatible = "mediatek,mt6572-sysirq", "mediatek,mt6577-sysirq"; 73 reg = <0x10200100 0x1c>; 74 interrupt-controller; 75 #interrupt-cells = <3>; 76 interrupt-parent = <&gic>; 77 }; 78 79 gic: interrupt-controller@10211000 { 80 compatible = "arm,cortex-a7-gic"; 81 reg = <0x10211000 0x1000>, 82 <0x10212000 0x2000>, 83 <0x10214000 0x2000>, 84 <0x10216000 0x2000>; 85 interrupt-controller; 86 #interrupt-cells = <3>; 87 interrupt-parent = <&gic>; 88 }; 89 90 uart0: serial@11005000 { 91 compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart"; 92 reg = <0x11005000 0x400>; 93 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 94 clocks = <&uart_clk>; 95 clock-names = "baud"; 96 status = "disabled"; 97 }; 98 99 uart1: serial@11006000 { 100 compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart"; 101 reg = <0x11006000 0x400>; 102 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; 103 clocks = <&uart_clk>; 104 clock-names = "baud"; 105 status = "disabled"; 106 }; 107 }; 108}; 109