xref: /linux/arch/arm64/boot/dts/qcom/msm8939.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8#include <dt-bindings/clock/qcom,gcc-msm8939.h>
9#include <dt-bindings/clock/qcom,rpmcc.h>
10#include <dt-bindings/interconnect/qcom,msm8939.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/reset/qcom,gcc-msm8939.h>
14#include <dt-bindings/soc/qcom,apr.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&intc>;
19
20	/*
21	 * Stock LK wants address-cells/size-cells = 2
22	 * A number of our drivers want address/size cells = 1
23	 * hence the disparity between top-level and /soc below.
24	 */
25	#address-cells = <2>;
26	#size-cells = <2>;
27
28	clocks {
29		xo_board: xo-board {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <19200000>;
33		};
34
35		sleep_clk: sleep-clk {
36			compatible = "fixed-clock";
37			#clock-cells = <0>;
38			clock-frequency = <32764>;
39		};
40	};
41
42	cpus {
43		#address-cells = <1>;
44		#size-cells = <0>;
45
46		cpu0: cpu@100 {
47			compatible = "arm,cortex-a53";
48			device_type = "cpu";
49			enable-method = "spin-table";
50			cpu-release-addr = /bits/ 64 <0>;
51			reg = <0x100>;
52			next-level-cache = <&l2_1>;
53			qcom,acc = <&acc0>;
54			qcom,saw = <&saw0>;
55			cpu-idle-states = <&cpu_sleep_0>;
56			clocks = <&apcs1_mbox>;
57			#cooling-cells = <2>;
58			l2_1: l2-cache {
59				compatible = "cache";
60				cache-level = <2>;
61				cache-unified;
62			};
63		};
64
65		cpu1: cpu@101 {
66			compatible = "arm,cortex-a53";
67			device_type = "cpu";
68			enable-method = "spin-table";
69			cpu-release-addr = /bits/ 64 <0>;
70			reg = <0x101>;
71			next-level-cache = <&l2_1>;
72			qcom,acc = <&acc1>;
73			qcom,saw = <&saw1>;
74			cpu-idle-states = <&cpu_sleep_0>;
75			clocks = <&apcs1_mbox>;
76			#cooling-cells = <2>;
77		};
78
79		cpu2: cpu@102 {
80			compatible = "arm,cortex-a53";
81			device_type = "cpu";
82			enable-method = "spin-table";
83			cpu-release-addr = /bits/ 64 <0>;
84			reg = <0x102>;
85			next-level-cache = <&l2_1>;
86			qcom,acc = <&acc2>;
87			qcom,saw = <&saw2>;
88			cpu-idle-states = <&cpu_sleep_0>;
89			clocks = <&apcs1_mbox>;
90			#cooling-cells = <2>;
91		};
92
93		cpu3: cpu@103 {
94			compatible = "arm,cortex-a53";
95			device_type = "cpu";
96			enable-method = "spin-table";
97			cpu-release-addr = /bits/ 64 <0>;
98			reg = <0x103>;
99			next-level-cache = <&l2_1>;
100			qcom,acc = <&acc3>;
101			qcom,saw = <&saw3>;
102			cpu-idle-states = <&cpu_sleep_0>;
103			clocks = <&apcs1_mbox>;
104			#cooling-cells = <2>;
105		};
106
107		cpu4: cpu@0 {
108			compatible = "arm,cortex-a53";
109			device_type = "cpu";
110			enable-method = "spin-table";
111			cpu-release-addr = /bits/ 64 <0>;
112			reg = <0x0>;
113			qcom,acc = <&acc4>;
114			qcom,saw = <&saw4>;
115			cpu-idle-states = <&cpu_sleep_0>;
116			clocks = <&apcs0_mbox>;
117			#cooling-cells = <2>;
118			next-level-cache = <&l2_0>;
119			l2_0: l2-cache {
120				compatible = "cache";
121				cache-level = <2>;
122				cache-unified;
123			};
124		};
125
126		cpu5: cpu@1 {
127			compatible = "arm,cortex-a53";
128			device_type = "cpu";
129			enable-method = "spin-table";
130			cpu-release-addr = /bits/ 64 <0>;
131			reg = <0x1>;
132			next-level-cache = <&l2_0>;
133			qcom,acc = <&acc5>;
134			qcom,saw = <&saw5>;
135			cpu-idle-states = <&cpu_sleep_0>;
136			clocks = <&apcs0_mbox>;
137			#cooling-cells = <2>;
138		};
139
140		cpu6: cpu@2 {
141			compatible = "arm,cortex-a53";
142			device_type = "cpu";
143			enable-method = "spin-table";
144			cpu-release-addr = /bits/ 64 <0>;
145			reg = <0x2>;
146			next-level-cache = <&l2_0>;
147			qcom,acc = <&acc6>;
148			qcom,saw = <&saw6>;
149			cpu-idle-states = <&cpu_sleep_0>;
150			clocks = <&apcs0_mbox>;
151			#cooling-cells = <2>;
152		};
153
154		cpu7: cpu@3 {
155			compatible = "arm,cortex-a53";
156			device_type = "cpu";
157			enable-method = "spin-table";
158			cpu-release-addr = /bits/ 64 <0>;
159			reg = <0x3>;
160			next-level-cache = <&l2_0>;
161			qcom,acc = <&acc7>;
162			qcom,saw = <&saw7>;
163			cpu-idle-states = <&cpu_sleep_0>;
164			clocks = <&apcs0_mbox>;
165			#cooling-cells = <2>;
166		};
167
168		idle-states {
169			cpu_sleep_0: cpu-sleep-0 {
170				compatible = "arm,idle-state";
171				entry-latency-us = <130>;
172				exit-latency-us = <150>;
173				min-residency-us = <2000>;
174				local-timer-stop;
175			};
176		};
177	};
178
179	/*
180	 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
181	 * consisting of two clusters of four ARM Cortex-A53s each. The
182	 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
183	 * at 1.5-1.7GHz.
184	 *
185	 * The enable method used here is spin-table which presupposes use
186	 * of a 2nd stage boot shim such as lk2nd to have installed a
187	 * spin-table, the downstream non-psci/non-spin-table method that
188	 * default msm8916/msm8936/msm8939 will not be supported upstream.
189	 */
190	cpu-map {
191		/* LITTLE (efficiency) cluster */
192		cluster0 {
193			core0 {
194				cpu = <&cpu4>;
195			};
196
197			core1 {
198				cpu = <&cpu5>;
199			};
200
201			core2 {
202				cpu = <&cpu6>;
203			};
204
205			core3 {
206				cpu = <&cpu7>;
207			};
208		};
209
210		/* big (performance) cluster */
211		/* Boot CPU is cluster 1 core 0 */
212		cluster1 {
213			core0 {
214				cpu = <&cpu0>;
215			};
216
217			core1 {
218				cpu = <&cpu1>;
219			};
220
221			core2 {
222				cpu = <&cpu2>;
223			};
224
225			core3 {
226				cpu = <&cpu3>;
227			};
228		};
229	};
230
231	firmware {
232		scm: scm {
233			compatible = "qcom,scm-msm8916", "qcom,scm";
234			clocks = <&gcc GCC_CRYPTO_CLK>,
235				 <&gcc GCC_CRYPTO_AXI_CLK>,
236				 <&gcc GCC_CRYPTO_AHB_CLK>;
237			clock-names = "core", "bus", "iface";
238			#reset-cells = <1>;
239
240			qcom,dload-mode = <&tcsr 0x6100>;
241		};
242	};
243
244	memory@80000000 {
245		device_type = "memory";
246		/* We expect the bootloader to fill in the reg */
247		reg = <0x0 0x80000000 0x0 0x0>;
248	};
249
250	pmu {
251		compatible = "arm,cortex-a53-pmu";
252		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
253	};
254
255	rpm: remoteproc {
256		compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
257
258		smd-edge {
259			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
260			qcom,ipc = <&apcs1_mbox 8 0>;
261			qcom,smd-edge = <15>;
262
263			rpm_requests: rpm-requests {
264				compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
265				qcom,smd-channels = "rpm_requests";
266
267				rpmcc: clock-controller {
268					compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
269					#clock-cells = <1>;
270					clock-names = "xo";
271					clocks = <&xo_board>;
272				};
273
274				rpmpd: power-controller {
275					compatible = "qcom,msm8939-rpmpd";
276					#power-domain-cells = <1>;
277					operating-points-v2 = <&rpmpd_opp_table>;
278
279					rpmpd_opp_table: opp-table {
280						compatible = "operating-points-v2";
281
282						rpmpd_opp_ret: opp1 {
283							opp-level = <1>;
284						};
285
286						rpmpd_opp_svs_krait: opp2 {
287							opp-level = <2>;
288						};
289
290						rpmpd_opp_svs_soc: opp3 {
291							opp-level = <3>;
292						};
293
294						rpmpd_opp_nom: opp4 {
295							opp-level = <4>;
296						};
297
298						rpmpd_opp_turbo: opp5 {
299							opp-level = <5>;
300						};
301
302						rpmpd_opp_super_turbo: opp6 {
303							opp-level = <6>;
304						};
305					};
306				};
307			};
308		};
309	};
310
311	reserved-memory {
312		#address-cells = <2>;
313		#size-cells = <2>;
314		ranges;
315
316		tz-apps@86000000 {
317			reg = <0x0 0x86000000 0x0 0x300000>;
318			no-map;
319		};
320
321		smem@86300000 {
322			compatible = "qcom,smem";
323			reg = <0x0 0x86300000 0x0 0x100000>;
324			no-map;
325
326			hwlocks = <&tcsr_mutex 3>;
327			qcom,rpm-msg-ram = <&rpm_msg_ram>;
328		};
329
330		hypervisor@86400000 {
331			reg = <0x0 0x86400000 0x0 0x100000>;
332			no-map;
333		};
334
335		tz@86500000 {
336			reg = <0x0 0x86500000 0x0 0x180000>;
337			no-map;
338		};
339
340		reserved@86680000 {
341			reg = <0x0 0x86680000 0x0 0x80000>;
342			no-map;
343		};
344
345		rmtfs@86700000 {
346			compatible = "qcom,rmtfs-mem";
347			reg = <0x0 0x86700000 0x0 0xe0000>;
348			no-map;
349
350			qcom,client-id = <1>;
351		};
352
353		rfsa@867e0000 {
354			reg = <0x0 0x867e0000 0x0 0x20000>;
355			no-map;
356		};
357
358		mpss_mem: mpss@86800000 {
359			/*
360			 * The memory region for the mpss firmware is generally
361			 * relocatable and could be allocated dynamically.
362			 * However, many firmware versions tend to fail when
363			 * loaded to some special addresses, so it is hard to
364			 * define reliable alloc-ranges.
365			 *
366			 * alignment = <0x0 0x400000>;
367			 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
368			 */
369			reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
370			no-map;
371			status = "disabled";
372		};
373
374		wcnss_mem: wcnss {
375			size = <0x0 0x600000>;
376			alignment = <0x0 0x100000>;
377			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
378			no-map;
379			status = "disabled";
380		};
381
382		venus_mem: venus {
383			size = <0x0 0x500000>;
384			alignment = <0x0 0x100000>;
385			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
386			no-map;
387			status = "disabled";
388		};
389
390		mba_mem: mba {
391			size = <0x0 0x100000>;
392			alignment = <0x0 0x100000>;
393			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
394			no-map;
395			status = "disabled";
396		};
397	};
398
399	smp2p-hexagon {
400		compatible = "qcom,smp2p";
401		qcom,smem = <435>, <428>;
402
403		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
404
405		mboxes = <&apcs1_mbox 14>;
406
407		qcom,local-pid = <0>;
408		qcom,remote-pid = <1>;
409
410		hexagon_smp2p_out: master-kernel {
411			qcom,entry-name = "master-kernel";
412
413			#qcom,smem-state-cells = <1>;
414		};
415
416		hexagon_smp2p_in: slave-kernel {
417			qcom,entry-name = "slave-kernel";
418
419			interrupt-controller;
420			#interrupt-cells = <2>;
421		};
422	};
423
424	smp2p-wcnss {
425		compatible = "qcom,smp2p";
426		qcom,smem = <451>, <431>;
427
428		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
429
430		mboxes = <&apcs1_mbox 18>;
431
432		qcom,local-pid = <0>;
433		qcom,remote-pid = <4>;
434
435		wcnss_smp2p_in: slave-kernel {
436			qcom,entry-name = "slave-kernel";
437
438			interrupt-controller;
439			#interrupt-cells = <2>;
440		};
441
442		wcnss_smp2p_out: master-kernel {
443			qcom,entry-name = "master-kernel";
444
445			#qcom,smem-state-cells = <1>;
446		};
447	};
448
449	smsm {
450		compatible = "qcom,smsm";
451
452		#address-cells = <1>;
453		#size-cells = <0>;
454
455		mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>;
456
457		apps_smsm: apps@0 {
458			reg = <0>;
459
460			#qcom,smem-state-cells = <1>;
461		};
462
463		hexagon_smsm: hexagon@1 {
464			reg = <1>;
465			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
466
467			interrupt-controller;
468			#interrupt-cells = <2>;
469		};
470
471		wcnss_smsm: wcnss@6 {
472			reg = <6>;
473			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
474
475			interrupt-controller;
476			#interrupt-cells = <2>;
477		};
478	};
479
480	soc: soc@0 {
481		compatible = "simple-bus";
482		#address-cells = <1>;
483		#size-cells = <1>;
484		ranges = <0 0 0 0xffffffff>;
485
486		rng@22000 {
487			compatible = "qcom,prng";
488			reg = <0x00022000 0x200>;
489			clocks = <&gcc GCC_PRNG_AHB_CLK>;
490			clock-names = "core";
491		};
492
493		qfprom: qfprom@5c000 {
494			compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
495			reg = <0x0005c000 0x1000>;
496			#address-cells = <1>;
497			#size-cells = <1>;
498
499			tsens_base1: base1@a0 {
500				reg = <0xa0 0x1>;
501				bits = <0 8>;
502			};
503
504			tsens_s6_p1: s6-p1@a1 {
505				reg = <0xa1 0x1>;
506				bits = <0 6>;
507			};
508
509			tsens_s6_p2: s6-p2@a1 {
510				reg = <0xa1 0x2>;
511				bits = <6 6>;
512			};
513
514			tsens_s7_p1: s7-p1@a2 {
515				reg = <0xa2 0x2>;
516				bits = <4 6>;
517			};
518
519			tsens_s7_p2: s7-p2@a3 {
520				reg = <0xa3 0x1>;
521				bits = <2 6>;
522			};
523
524			tsens_s8_p1: s8-p1@a4 {
525				reg = <0xa4 0x1>;
526				bits = <0 6>;
527			};
528
529			tsens_s8_p2: s8-p2@a4 {
530				reg = <0xa4 0x2>;
531				bits = <6 6>;
532			};
533
534			tsens_s9_p1: s9-p1@a5 {
535				reg = <0xa5 0x2>;
536				bits = <4 6>;
537			};
538
539			tsens_s9_p2: s9-p2@a6 {
540				reg = <0xa6 0x1>;
541				bits = <2 6>;
542			};
543
544			tsens_base2: base2@a7 {
545				reg = <0xa7 0x1>;
546				bits = <0 8>;
547			};
548
549			tsens_mode: mode@d0 {
550				reg = <0xd0 0x1>;
551				bits = <0 3>;
552			};
553
554			tsens_s0_p1: s0-p1@d0 {
555				reg = <0xd0 0x2>;
556				bits = <3 6>;
557			};
558
559			tsens_s0_p2: s0-p1@d1 {
560				reg = <0xd1 0x1>;
561				bits = <1 6>;
562			};
563
564			tsens_s1_p1: s1-p1@d1 {
565				reg = <0xd1 0x2>;
566				bits = <7 6>;
567			};
568
569			tsens_s1_p2: s1-p2@d2 {
570				reg = <0xd2 0x2>;
571				bits = <5 6>;
572			};
573
574			tsens_s2_p1: s2-p1@d3 {
575				reg = <0xd3 0x2>;
576				bits = <3 6>;
577			};
578
579			tsens_s2_p2: s2-p2@d4 {
580				reg = <0xd4 0x1>;
581				bits = <1 6>;
582			};
583
584			tsens_s3_p1: s3-p1@d4 {
585				reg = <0xd4 0x2>;
586				bits = <7 6>;
587			};
588
589			tsens_s3_p2: s3-p2@d5 {
590				reg = <0xd5 0x2>;
591				bits = <5 6>;
592			};
593
594			tsens_s5_p1: s5-p1@d6 {
595				reg = <0xd6 0x2>;
596				bits = <3 6>;
597			};
598
599			tsens_s5_p2: s5-p2@d7 {
600				reg = <0xd7 0x1>;
601				bits = <1 6>;
602			};
603		};
604
605		rpm_msg_ram: sram@60000 {
606			compatible = "qcom,rpm-msg-ram";
607			reg = <0x00060000 0x8000>;
608		};
609
610		bimc: interconnect@400000 {
611			compatible = "qcom,msm8939-bimc";
612			reg = <0x00400000 0x62000>;
613			#interconnect-cells = <1>;
614		};
615
616		tsens: thermal-sensor@4a9000 {
617			compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
618			reg = <0x004a9000 0x1000>, /* TM */
619			      <0x004a8000 0x1000>; /* SROT */
620			nvmem-cells = <&tsens_mode>,
621				      <&tsens_base1>, <&tsens_base2>,
622				      <&tsens_s0_p1>, <&tsens_s0_p2>,
623				      <&tsens_s1_p1>, <&tsens_s1_p2>,
624				      <&tsens_s2_p1>, <&tsens_s2_p2>,
625				      <&tsens_s3_p1>, <&tsens_s3_p2>,
626				      <&tsens_s5_p1>, <&tsens_s5_p2>,
627				      <&tsens_s6_p1>, <&tsens_s6_p2>,
628				      <&tsens_s7_p1>, <&tsens_s7_p2>,
629				      <&tsens_s8_p1>, <&tsens_s8_p2>,
630				      <&tsens_s9_p1>, <&tsens_s9_p2>;
631			nvmem-cell-names = "mode",
632					   "base1", "base2",
633					   "s0_p1", "s0_p2",
634					   "s1_p1", "s1_p2",
635					   "s2_p1", "s2_p2",
636					   "s3_p1", "s3_p2",
637					   "s5_p1", "s5_p2",
638					   "s6_p1", "s6_p2",
639					   "s7_p1", "s7_p2",
640					   "s8_p1", "s8_p2",
641					   "s9_p1", "s9_p2";
642			#qcom,sensors = <9>;
643			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
644			interrupt-names = "uplow";
645			#thermal-sensor-cells = <1>;
646		};
647
648		restart@4ab000 {
649			compatible = "qcom,pshold";
650			reg = <0x004ab000 0x4>;
651		};
652
653		pcnoc: interconnect@500000 {
654			compatible = "qcom,msm8939-pcnoc";
655			reg = <0x00500000 0x11000>;
656			#interconnect-cells = <1>;
657		};
658
659		snoc: interconnect@580000 {
660			compatible = "qcom,msm8939-snoc";
661			reg = <0x00580000 0x14080>;
662			#interconnect-cells = <1>;
663
664			snoc_mm: interconnect-snoc {
665				compatible = "qcom,msm8939-snoc-mm";
666				#interconnect-cells = <1>;
667			};
668		};
669
670		tlmm: pinctrl@1000000 {
671			compatible = "qcom,msm8916-pinctrl";
672			reg = <0x01000000 0x300000>;
673			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
674			gpio-controller;
675			gpio-ranges = <&tlmm 0 0 122>;
676			#gpio-cells = <2>;
677			interrupt-controller;
678			#interrupt-cells = <2>;
679
680			blsp_i2c1_default: blsp-i2c1-default-state {
681				pins = "gpio2", "gpio3";
682				function = "blsp_i2c1";
683				drive-strength = <2>;
684				bias-disable;
685			};
686
687			blsp_i2c1_sleep: blsp-i2c1-sleep-state {
688				pins = "gpio2", "gpio3";
689				function = "gpio";
690				drive-strength = <2>;
691				bias-disable;
692			};
693
694			blsp_i2c2_default: blsp-i2c2-default-state {
695				pins = "gpio6", "gpio7";
696				function = "blsp_i2c2";
697				drive-strength = <2>;
698				bias-disable;
699			};
700
701			blsp_i2c2_sleep: blsp-i2c2-sleep-state {
702				pins = "gpio6", "gpio7";
703				function = "gpio";
704				drive-strength = <2>;
705				bias-disable;
706			};
707
708			blsp_i2c3_default: blsp-i2c3-default-state {
709				pins = "gpio10", "gpio11";
710				function = "blsp_i2c3";
711				drive-strength = <2>;
712				bias-disable;
713			};
714
715			blsp_i2c3_sleep: blsp-i2c3-sleep-state {
716				pins = "gpio10", "gpio11";
717				function = "gpio";
718				drive-strength = <2>;
719				bias-disable;
720			};
721
722			blsp_i2c4_default: blsp-i2c4-default-state {
723				pins = "gpio14", "gpio15";
724				function = "blsp_i2c4";
725				drive-strength = <2>;
726				bias-disable;
727			};
728
729			blsp_i2c4_sleep: blsp-i2c4-sleep-state {
730				pins = "gpio14", "gpio15";
731				function = "gpio";
732				drive-strength = <2>;
733				bias-disable;
734			};
735
736			blsp_i2c5_default: blsp-i2c5-default-state {
737				pins = "gpio18", "gpio19";
738				function = "blsp_i2c5";
739				drive-strength = <2>;
740				bias-disable;
741			};
742
743			blsp_i2c5_sleep: blsp-i2c5-sleep-state {
744				pins = "gpio18", "gpio19";
745				function = "gpio";
746				drive-strength = <2>;
747				bias-disable;
748			};
749
750			blsp_i2c6_default: blsp-i2c6-default-state {
751				pins = "gpio22", "gpio23";
752				function = "blsp_i2c6";
753				drive-strength = <2>;
754				bias-disable;
755			};
756
757			blsp_i2c6_sleep: blsp-i2c6-sleep-state {
758				pins = "gpio22", "gpio23";
759				function = "gpio";
760				drive-strength = <2>;
761				bias-disable;
762			};
763
764			blsp_spi1_default: blsp-spi1-default-state {
765				spi-pins {
766					pins = "gpio0", "gpio1", "gpio3";
767					function = "blsp_spi1";
768					drive-strength = <12>;
769					bias-disable;
770				};
771
772				cs-pins {
773					pins = "gpio2";
774					function = "gpio";
775					drive-strength = <16>;
776					bias-disable;
777					output-high;
778				};
779			};
780
781			blsp_spi1_sleep: blsp-spi1-sleep-state {
782				pins = "gpio0", "gpio1", "gpio2", "gpio3";
783				function = "gpio";
784				drive-strength = <2>;
785				bias-pull-down;
786			};
787
788			blsp_spi2_default: blsp-spi2-default-state {
789				spi-pins {
790					pins = "gpio4", "gpio5", "gpio7";
791					function = "blsp_spi2";
792					drive-strength = <12>;
793					bias-disable;
794				};
795
796				cs-pins {
797					pins = "gpio6";
798					function = "gpio";
799					drive-strength = <16>;
800					bias-disable;
801					output-high;
802				};
803			};
804
805			blsp_spi2_sleep: blsp-spi2-sleep-state {
806				pins = "gpio4", "gpio5", "gpio6", "gpio7";
807				function = "gpio";
808				drive-strength = <2>;
809				bias-pull-down;
810			};
811
812			blsp_spi3_default: blsp-spi3-default-state {
813				spi-pins {
814					pins = "gpio8", "gpio9", "gpio11";
815					function = "blsp_spi3";
816					drive-strength = <12>;
817					bias-disable;
818				};
819
820				cs-pins {
821					pins = "gpio10";
822					function = "gpio";
823					drive-strength = <16>;
824					bias-disable;
825					output-high;
826				};
827			};
828
829			blsp_spi3_sleep: blsp-spi3-sleep-state {
830				pins = "gpio8", "gpio9", "gpio10", "gpio11";
831				function = "gpio";
832				drive-strength = <2>;
833				bias-pull-down;
834			};
835
836			blsp_spi4_default: blsp-spi4-default-state {
837				spi-pins {
838					pins = "gpio12", "gpio13", "gpio15";
839					function = "blsp_spi4";
840					drive-strength = <12>;
841					bias-disable;
842				};
843
844				cs-pins {
845					pins = "gpio14";
846					function = "gpio";
847					drive-strength = <16>;
848					bias-disable;
849					output-high;
850				};
851			};
852
853			blsp_spi4_sleep: blsp-spi4-sleep-state {
854				pins = "gpio12", "gpio13", "gpio14", "gpio15";
855				function = "gpio";
856				drive-strength = <2>;
857				bias-pull-down;
858			};
859
860			blsp_spi5_default: blsp-spi5-default-state {
861				spi-pins {
862					pins = "gpio16", "gpio17", "gpio19";
863					function = "blsp_spi5";
864					drive-strength = <12>;
865					bias-disable;
866				};
867
868				cs-pins {
869					pins = "gpio18";
870					function = "gpio";
871					drive-strength = <16>;
872					bias-disable;
873					output-high;
874				};
875			};
876
877			blsp_spi5_sleep: blsp-spi5-sleep-state {
878				pins = "gpio16", "gpio17", "gpio18", "gpio19";
879				function = "gpio";
880				drive-strength = <2>;
881				bias-pull-down;
882			};
883
884			blsp_spi6_default: blsp-spi6-default-state {
885				spi-pins {
886					pins = "gpio20", "gpio21", "gpio23";
887					function = "blsp_spi6";
888					drive-strength = <12>;
889					bias-disable;
890				};
891
892				cs-pins {
893					pins = "gpio22";
894					function = "gpio";
895					drive-strength = <16>;
896					bias-disable;
897					output-high;
898				};
899			};
900
901			blsp_spi6_sleep: blsp-spi6-sleep-state {
902				pins = "gpio20", "gpio21", "gpio22", "gpio23";
903				function = "gpio";
904				drive-strength = <2>;
905				bias-pull-down;
906			};
907
908			blsp_uart1_console_default: blsp-uart1-console-default-state {
909				tx-pins {
910					pins = "gpio0";
911					function = "blsp_uart1";
912					drive-strength = <16>;
913					bias-disable;
914					bootph-all;
915				};
916
917				rx-pins {
918					pins = "gpio1";
919					function = "blsp_uart1";
920					drive-strength = <16>;
921					bias-pull-up;
922					bootph-all;
923				};
924			};
925
926			blsp_uart1_console_sleep: blsp-uart1-console-sleep-state {
927				pins = "gpio0", "gpio1";
928				function = "gpio";
929				drive-strength = <2>;
930				bias-pull-down;
931			};
932
933			blsp_uart2_console_default: blsp-uart2-console-default-state {
934				tx-pins {
935					pins = "gpio4";
936					function = "blsp_uart2";
937					drive-strength = <16>;
938					bias-disable;
939					bootph-all;
940				};
941
942				rx-pins {
943					pins = "gpio5";
944					function = "blsp_uart2";
945					drive-strength = <16>;
946					bias-pull-up;
947					bootph-all;
948				};
949			};
950
951			blsp_uart2_console_sleep: blsp-uart2-console-sleep-state {
952				pins = "gpio4", "gpio5";
953				function = "gpio";
954				drive-strength = <2>;
955				bias-pull-down;
956			};
957
958			camera_front_default: camera-front-default-state {
959				pwdn-pins {
960					pins = "gpio33";
961					function = "gpio";
962					drive-strength = <16>;
963					bias-disable;
964				};
965
966				rst-pins {
967					pins = "gpio28";
968					function = "gpio";
969					drive-strength = <16>;
970					bias-disable;
971				};
972
973				mclk1-pins {
974					pins = "gpio27";
975					function = "cam_mclk1";
976					drive-strength = <16>;
977					bias-disable;
978				};
979			};
980
981			camera_rear_default: camera-rear-default-state {
982				pwdn-pins {
983					pins = "gpio34";
984					function = "gpio";
985					drive-strength = <16>;
986					bias-disable;
987				};
988
989				rst-pins {
990					pins = "gpio35";
991					function = "gpio";
992					drive-strength = <16>;
993					bias-disable;
994				};
995
996				mclk0-pins {
997					pins = "gpio26";
998					function = "cam_mclk0";
999					drive-strength = <16>;
1000					bias-disable;
1001				};
1002			};
1003
1004			cci0_default: cci0-default-state {
1005				pins = "gpio29", "gpio30";
1006				function = "cci_i2c";
1007				drive-strength = <16>;
1008				bias-disable;
1009			};
1010
1011			cdc_dmic_default: cdc-dmic-default-state {
1012				clk-pins {
1013					pins = "gpio0";
1014					function = "dmic0_clk";
1015					drive-strength = <8>;
1016				};
1017
1018				data-pins {
1019					pins = "gpio1";
1020					function = "dmic0_data";
1021					drive-strength = <8>;
1022				};
1023			};
1024
1025			cdc_dmic_sleep: cdc-dmic-sleep-state {
1026				clk-pins {
1027					pins = "gpio0";
1028					function = "dmic0_clk";
1029					drive-strength = <2>;
1030					bias-disable;
1031				};
1032
1033				data-pins {
1034					pins = "gpio1";
1035					function = "dmic0_data";
1036					drive-strength = <2>;
1037					bias-disable;
1038				};
1039			};
1040
1041			cdc_pdm_default: cdc-pdm-default-state {
1042				pins = "gpio63", "gpio64", "gpio65", "gpio66",
1043				       "gpio67", "gpio68";
1044				function = "cdc_pdm0";
1045				drive-strength = <8>;
1046				bias-disable;
1047			};
1048
1049			cdc_pdm_sleep: cdc-pdm-sleep-state {
1050				pins = "gpio63", "gpio64", "gpio65", "gpio66",
1051				       "gpio67", "gpio68";
1052				function = "cdc_pdm0";
1053				drive-strength = <2>;
1054				bias-pull-down;
1055			};
1056
1057			pri_mi2s_default: mi2s-pri-default-state {
1058				pins = "gpio113", "gpio114", "gpio115", "gpio116";
1059				function = "pri_mi2s";
1060				drive-strength = <8>;
1061				bias-disable;
1062			};
1063
1064			pri_mi2s_sleep: mi2s-pri-sleep-state {
1065				pins = "gpio113", "gpio114", "gpio115", "gpio116";
1066				function = "pri_mi2s";
1067				drive-strength = <2>;
1068				bias-disable;
1069			};
1070
1071			pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1072				pins = "gpio116";
1073				function = "pri_mi2s";
1074				drive-strength = <8>;
1075				bias-disable;
1076			};
1077
1078			pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1079				pins = "gpio116";
1080				function = "pri_mi2s";
1081				drive-strength = <2>;
1082				bias-disable;
1083			};
1084
1085			pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1086				pins = "gpio110";
1087				function = "pri_mi2s_ws";
1088				drive-strength = <8>;
1089				bias-disable;
1090			};
1091
1092			pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1093				pins = "gpio110";
1094				function = "pri_mi2s_ws";
1095				drive-strength = <2>;
1096				bias-disable;
1097			};
1098
1099			sec_mi2s_default: mi2s-sec-default-state {
1100				pins = "gpio112", "gpio117", "gpio118", "gpio119";
1101				function = "sec_mi2s";
1102				drive-strength = <8>;
1103				bias-disable;
1104			};
1105
1106			sec_mi2s_sleep: mi2s-sec-sleep-state {
1107				pins = "gpio112", "gpio117", "gpio118", "gpio119";
1108				function = "sec_mi2s";
1109				drive-strength = <2>;
1110				bias-disable;
1111			};
1112
1113			sdc1_default: sdc1-default-state {
1114				clk-pins {
1115					pins = "sdc1_clk";
1116					bias-disable;
1117					drive-strength = <16>;
1118				};
1119
1120				cmd-pins {
1121					pins = "sdc1_cmd";
1122					bias-pull-up;
1123					drive-strength = <10>;
1124				};
1125
1126				data-pins {
1127					pins = "sdc1_data";
1128					bias-pull-up;
1129					drive-strength = <10>;
1130				};
1131			};
1132
1133			sdc1_sleep: sdc1-sleep-state {
1134				clk-pins {
1135					pins = "sdc1_clk";
1136					bias-disable;
1137					drive-strength = <2>;
1138				};
1139
1140				cmd-pins {
1141					pins = "sdc1_cmd";
1142					bias-pull-up;
1143					drive-strength = <2>;
1144				};
1145
1146				data-pins {
1147					pins = "sdc1_data";
1148					bias-pull-up;
1149					drive-strength = <2>;
1150				};
1151			};
1152
1153			sdc2_default: sdc2-default-state {
1154				clk-pins {
1155					pins = "sdc2_clk";
1156					bias-disable;
1157					drive-strength = <16>;
1158				};
1159
1160				cmd-pins {
1161					pins = "sdc2_cmd";
1162					bias-pull-up;
1163					drive-strength = <10>;
1164				};
1165
1166				data-pins {
1167					pins = "sdc2_data";
1168					bias-pull-up;
1169					drive-strength = <10>;
1170				};
1171			};
1172
1173			sdc2_sleep: sdc2-sleep-state {
1174				clk-pins {
1175					pins = "sdc2_clk";
1176					bias-disable;
1177					drive-strength = <2>;
1178				};
1179
1180				cmd-pins {
1181					pins = "sdc2_cmd";
1182					bias-pull-up;
1183					drive-strength = <2>;
1184				};
1185
1186				data-pins {
1187					pins = "sdc2_data";
1188					bias-pull-up;
1189					drive-strength = <2>;
1190				};
1191			};
1192
1193			wcss_wlan_default: wcss-wlan-default-state {
1194				pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1195				function = "wcss_wlan";
1196				drive-strength = <6>;
1197				bias-pull-up;
1198			};
1199		};
1200
1201		gcc: clock-controller@1800000 {
1202			compatible = "qcom,gcc-msm8939";
1203			reg = <0x01800000 0x80000>;
1204			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1205				 <&sleep_clk>,
1206				 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
1207				 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1208				 <0>,
1209				 <0>,
1210				 <0>;
1211			clock-names = "xo",
1212				      "sleep_clk",
1213				      "dsi0pll",
1214				      "dsi0pllbyte",
1215				      "ext_mclk",
1216				      "ext_pri_i2s",
1217				      "ext_sec_i2s";
1218			#clock-cells = <1>;
1219			#reset-cells = <1>;
1220			#power-domain-cells = <1>;
1221		};
1222
1223		tcsr_mutex: hwlock@1905000 {
1224			compatible = "qcom,tcsr-mutex";
1225			reg = <0x01905000 0x20000>;
1226			#hwlock-cells = <1>;
1227		};
1228
1229		tcsr: syscon@1937000 {
1230			compatible = "qcom,tcsr-msm8916", "syscon";
1231			reg = <0x01937000 0x30000>;
1232		};
1233
1234		mdss: display-subsystem@1a00000 {
1235			compatible = "qcom,mdss";
1236			reg = <0x01a00000 0x1000>,
1237			      <0x01ac8000 0x3000>;
1238			reg-names = "mdss_phys", "vbif_phys";
1239
1240			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1241			interrupt-controller;
1242
1243			clocks = <&gcc GCC_MDSS_AHB_CLK>,
1244				 <&gcc GCC_MDSS_AXI_CLK>,
1245				 <&gcc GCC_MDSS_VSYNC_CLK>;
1246			clock-names = "iface",
1247				      "bus",
1248				      "vsync";
1249
1250			power-domains = <&gcc MDSS_GDSC>;
1251
1252			#address-cells = <1>;
1253			#size-cells = <1>;
1254			#interrupt-cells = <1>;
1255			ranges;
1256
1257			status = "disabled";
1258
1259			mdss_mdp: display-controller@1a01000 {
1260				compatible = "qcom,mdp5";
1261				reg = <0x01a01000 0x89000>;
1262				reg-names = "mdp_phys";
1263
1264				interrupt-parent = <&mdss>;
1265				interrupts = <0>;
1266
1267				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1268					 <&gcc GCC_MDSS_AXI_CLK>,
1269					 <&gcc GCC_MDSS_MDP_CLK>,
1270					 <&gcc GCC_MDSS_VSYNC_CLK>;
1271				clock-names = "iface",
1272					      "bus",
1273					      "core",
1274					      "vsync";
1275
1276				iommus = <&apps_iommu 4>;
1277
1278				interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1279						<&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1280				interconnect-names = "mdp0-mem", "mdp1-mem";
1281
1282				ports {
1283					#address-cells = <1>;
1284					#size-cells = <0>;
1285
1286					port@0 {
1287						reg = <0>;
1288						mdss_mdp_intf1_out: endpoint {
1289							remote-endpoint = <&mdss_dsi0_in>;
1290						};
1291					};
1292
1293					port@1 {
1294						reg = <1>;
1295						mdss_mdp_intf2_out: endpoint {
1296							remote-endpoint = <&mdss_dsi1_in>;
1297						};
1298					};
1299				};
1300			};
1301
1302			mdss_dsi0: dsi@1a98000 {
1303				compatible = "qcom,msm8916-dsi-ctrl",
1304					     "qcom,mdss-dsi-ctrl";
1305				reg = <0x01a98000 0x25c>;
1306				reg-names = "dsi_ctrl";
1307
1308				interrupt-parent = <&mdss>;
1309				interrupts = <4>;
1310
1311				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1312					 <&gcc GCC_MDSS_AHB_CLK>,
1313					 <&gcc GCC_MDSS_AXI_CLK>,
1314					 <&gcc GCC_MDSS_BYTE0_CLK>,
1315					 <&gcc GCC_MDSS_PCLK0_CLK>,
1316					 <&gcc GCC_MDSS_ESC0_CLK>;
1317				clock-names = "mdp_core",
1318					      "iface",
1319					      "bus",
1320					      "byte",
1321					      "pixel",
1322					      "core";
1323				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1324						  <&gcc PCLK0_CLK_SRC>;
1325				assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1326							 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
1327
1328				phys = <&mdss_dsi0_phy>;
1329				status = "disabled";
1330
1331				#address-cells = <1>;
1332				#size-cells = <0>;
1333
1334				ports {
1335					#address-cells = <1>;
1336					#size-cells = <0>;
1337
1338					port@0 {
1339						reg = <0>;
1340						mdss_dsi0_in: endpoint {
1341							remote-endpoint = <&mdss_mdp_intf1_out>;
1342						};
1343					};
1344
1345					port@1 {
1346						reg = <1>;
1347						mdss_dsi0_out: endpoint {
1348						};
1349					};
1350				};
1351			};
1352
1353			mdss_dsi0_phy: phy@1a98300 {
1354				compatible = "qcom,dsi-phy-28nm-lp";
1355				reg = <0x01a98300 0xd4>,
1356				      <0x01a98500 0x280>,
1357				      <0x01a98780 0x30>;
1358				reg-names = "dsi_pll",
1359					    "dsi_phy",
1360					    "dsi_phy_regulator";
1361
1362				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1363					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1364				clock-names = "iface", "ref";
1365
1366				#clock-cells = <1>;
1367				#phy-cells = <0>;
1368				status = "disabled";
1369			};
1370
1371			mdss_dsi1: dsi@1aa0000 {
1372				compatible = "qcom,msm8916-dsi-ctrl",
1373					     "qcom,mdss-dsi-ctrl";
1374				reg = <0x01aa0000 0x25c>;
1375				reg-names = "dsi_ctrl";
1376
1377				interrupt-parent = <&mdss>;
1378				interrupts = <5>;
1379
1380				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1381					 <&gcc GCC_MDSS_AHB_CLK>,
1382					 <&gcc GCC_MDSS_AXI_CLK>,
1383					 <&gcc GCC_MDSS_BYTE1_CLK>,
1384					 <&gcc GCC_MDSS_PCLK1_CLK>,
1385					 <&gcc GCC_MDSS_ESC1_CLK>;
1386				clock-names = "mdp_core",
1387					      "iface",
1388					      "bus",
1389					      "byte",
1390					      "pixel",
1391					      "core";
1392				assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1393						  <&gcc PCLK1_CLK_SRC>;
1394				assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1395							 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
1396				phys = <&mdss_dsi1_phy>;
1397				status = "disabled";
1398
1399				ports {
1400					#address-cells = <1>;
1401					#size-cells = <0>;
1402
1403					port@0 {
1404						reg = <0>;
1405						mdss_dsi1_in: endpoint {
1406							remote-endpoint = <&mdss_mdp_intf2_out>;
1407						};
1408					};
1409
1410					port@1 {
1411						reg = <1>;
1412						mdss_dsi1_out: endpoint {
1413						};
1414					};
1415				};
1416			};
1417
1418			mdss_dsi1_phy: phy@1aa0300 {
1419				compatible = "qcom,dsi-phy-28nm-lp";
1420				reg = <0x01aa0300 0xd4>,
1421				      <0x01aa0500 0x280>,
1422				      <0x01aa0780 0x30>;
1423				reg-names = "dsi_pll",
1424					    "dsi_phy",
1425					    "dsi_phy_regulator";
1426
1427				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1428					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1429				clock-names = "iface", "ref";
1430
1431				#clock-cells = <1>;
1432				#phy-cells = <0>;
1433				status = "disabled";
1434			};
1435		};
1436
1437		gpu: gpu@1c00000 {
1438			compatible = "qcom,adreno-405.0", "qcom,adreno";
1439			reg = <0x01c00000 0x10000>;
1440			reg-names = "kgsl_3d0_reg_memory";
1441			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1442			interrupt-names = "kgsl_3d0_irq";
1443			clock-names = "core",
1444				      "iface",
1445				      "mem",
1446				      "mem_iface",
1447				      "alt_mem_iface",
1448				      "gfx3d",
1449				      "rbbmtimer";
1450			clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1451				 <&gcc GCC_OXILI_AHB_CLK>,
1452				 <&gcc GCC_OXILI_GMEM_CLK>,
1453				 <&gcc GCC_BIMC_GFX_CLK>,
1454				 <&gcc GCC_BIMC_GPU_CLK>,
1455				 <&gcc GFX3D_CLK_SRC>,
1456				 <&gcc GCC_OXILI_TIMER_CLK>;
1457			power-domains = <&gcc OXILI_GDSC>;
1458			operating-points-v2 = <&opp_table>;
1459			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1460			#cooling-cells = <2>;
1461
1462			status = "disabled";
1463
1464			opp_table: opp-table {
1465				compatible = "operating-points-v2";
1466
1467				opp-550000000 {
1468					opp-hz = /bits/ 64 <550000000>;
1469				};
1470
1471				opp-465000000 {
1472					opp-hz = /bits/ 64 <465000000>;
1473				};
1474
1475				opp-400000000 {
1476					opp-hz = /bits/ 64 <400000000>;
1477				};
1478
1479				opp-220000000 {
1480					opp-hz = /bits/ 64 <220000000>;
1481				};
1482
1483				opp-19200000 {
1484					opp-hz = /bits/ 64 <19200000>;
1485				};
1486			};
1487		};
1488
1489		apps_iommu: iommu@1ef0000 {
1490			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1491			reg = <0x01ef0000 0x3000>;
1492			ranges = <0 0x01e20000 0x20000>;
1493			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1494				 <&gcc GCC_APSS_TCU_CLK>;
1495			clock-names = "iface", "bus";
1496			#address-cells = <1>;
1497			#size-cells = <1>;
1498			#iommu-cells = <1>;
1499			qcom,iommu-secure-id = <17>;
1500
1501			/* mdp_0: */
1502			iommu-ctx@4000 {
1503				compatible = "qcom,msm-iommu-v1-ns";
1504				reg = <0x4000 0x1000>;
1505				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1506			};
1507
1508			/* venus_ns: */
1509			iommu-ctx@5000 {
1510				compatible = "qcom,msm-iommu-v1-sec";
1511				reg = <0x5000 0x1000>;
1512				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1513			};
1514		};
1515
1516		gpu_iommu: iommu@1f08000 {
1517			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1518			ranges = <0 0x1f08000 0x10000>;
1519			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1520				 <&gcc GCC_GFX_TCU_CLK>,
1521				 <&gcc GCC_GFX_TBU_CLK>;
1522			clock-names = "iface", "bus", "tbu";
1523			#address-cells = <1>;
1524			#size-cells = <1>;
1525			#iommu-cells = <1>;
1526			qcom,iommu-secure-id = <18>;
1527
1528			/* gfx3d_user: */
1529			iommu-ctx@1000 {
1530				compatible = "qcom,msm-iommu-v1-ns";
1531				reg = <0x1000 0x1000>;
1532				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1533			};
1534
1535			/* gfx3d_priv: */
1536			iommu-ctx@2000 {
1537				compatible = "qcom,msm-iommu-v1-ns";
1538				reg = <0x2000 0x1000>;
1539				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1540			};
1541		};
1542
1543		spmi_bus: spmi@200f000 {
1544			compatible = "qcom,spmi-pmic-arb";
1545			reg = <0x0200f000 0x001000>,
1546			      <0x02400000 0x400000>,
1547			      <0x02c00000 0x400000>,
1548			      <0x03800000 0x200000>,
1549			      <0x0200a000 0x002100>;
1550			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1551			interrupt-names = "periph_irq";
1552			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1553			qcom,ee = <0>;
1554			qcom,channel = <0>;
1555			#address-cells = <2>;
1556			#size-cells = <0>;
1557			interrupt-controller;
1558			#interrupt-cells = <4>;
1559		};
1560
1561		bam_dmux_dma: dma-controller@4044000 {
1562			compatible = "qcom,bam-v1.7.0";
1563			reg = <0x04044000 0x19000>;
1564			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1565			#dma-cells = <1>;
1566			qcom,ee = <0>;
1567
1568			num-channels = <6>;
1569			qcom,num-ees = <1>;
1570			qcom,powered-remotely;
1571
1572			status = "disabled";
1573		};
1574
1575		mpss: remoteproc@4080000 {
1576			compatible = "qcom,msm8916-mss-pil";
1577			reg = <0x04080000 0x100>, <0x04020000 0x040>;
1578			reg-names = "qdsp6", "rmb";
1579			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1580					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1581					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1582					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1583					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1584			interrupt-names = "wdog",
1585					  "fatal",
1586					  "ready",
1587					  "handover",
1588					  "stop-ack";
1589			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1590				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1591				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1592				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1593			clock-names = "iface",
1594				      "bus",
1595				      "mem",
1596				      "xo";
1597			power-domains = <&rpmpd MSM8939_VDDMDCX>,
1598					<&rpmpd MSM8939_VDDMX>;
1599			power-domain-names = "cx", "mx";
1600			qcom,smem-states = <&hexagon_smp2p_out 0>;
1601			qcom,smem-state-names = "stop";
1602			resets = <&scm 0>;
1603			reset-names = "mss_restart";
1604			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1605			status = "disabled";
1606
1607			bam_dmux: bam-dmux {
1608				compatible = "qcom,bam-dmux";
1609
1610				interrupt-parent = <&hexagon_smsm>;
1611				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1612				interrupt-names = "pc", "pc-ack";
1613
1614				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1615				qcom,smem-state-names = "pc", "pc-ack";
1616
1617				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1618				dma-names = "tx", "rx";
1619
1620				status = "disabled";
1621			};
1622
1623			mba {
1624				memory-region = <&mba_mem>;
1625			};
1626
1627			mpss {
1628				memory-region = <&mpss_mem>;
1629			};
1630
1631			smd-edge {
1632				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1633
1634				qcom,smd-edge = <0>;
1635				mboxes = <&apcs1_mbox 12>;
1636				qcom,remote-pid = <1>;
1637
1638				label = "hexagon";
1639
1640				apr: apr {
1641					compatible = "qcom,apr-v2";
1642					qcom,smd-channels = "apr_audio_svc";
1643					qcom,domain = <APR_DOMAIN_ADSP>;
1644					#address-cells = <1>;
1645					#size-cells = <0>;
1646					status = "disabled";
1647
1648					q6core: service@3 {
1649						compatible = "qcom,q6core";
1650						reg = <APR_SVC_ADSP_CORE>;
1651					};
1652
1653					q6afe: service@4 {
1654						compatible = "qcom,q6afe";
1655						reg = <APR_SVC_AFE>;
1656
1657						q6afedai: dais {
1658							compatible = "qcom,q6afe-dais";
1659							#address-cells = <1>;
1660							#size-cells = <0>;
1661							#sound-dai-cells = <1>;
1662						};
1663					};
1664
1665					q6asm: service@7 {
1666						compatible = "qcom,q6asm";
1667						reg = <APR_SVC_ASM>;
1668
1669						q6asmdai: dais {
1670							compatible = "qcom,q6asm-dais";
1671							#address-cells = <1>;
1672							#size-cells = <0>;
1673							#sound-dai-cells = <1>;
1674						};
1675					};
1676
1677					q6adm: service@8 {
1678						compatible = "qcom,q6adm";
1679						reg = <APR_SVC_ADM>;
1680
1681						q6routing: routing {
1682							compatible = "qcom,q6adm-routing";
1683							#sound-dai-cells = <0>;
1684						};
1685					};
1686				};
1687			};
1688		};
1689
1690		sound: sound@7702000 {
1691			compatible = "qcom,apq8016-sbc-sndcard";
1692			reg = <0x07702000 0x4>,
1693			      <0x07702004 0x4>;
1694			reg-names = "mic-iomux", "spkr-iomux";
1695			status = "disabled";
1696		};
1697
1698		lpass: audio-controller@7708000 {
1699			compatible = "qcom,apq8016-lpass-cpu";
1700			reg = <0x07708000 0x10000>;
1701			reg-names = "lpass-lpaif";
1702			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1703			interrupt-names = "lpass-irq-lpaif";
1704			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1705				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1706				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1707				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1708				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1709				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1710				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1711			clock-names = "ahbix-clk",
1712				      "mi2s-bit-clk0",
1713				      "mi2s-bit-clk1",
1714				      "mi2s-bit-clk2",
1715				      "mi2s-bit-clk3",
1716				      "pcnoc-mport-clk",
1717				      "pcnoc-sway-clk";
1718			#sound-dai-cells = <1>;
1719			#address-cells = <1>;
1720			#size-cells = <0>;
1721			status = "disabled";
1722		};
1723
1724		lpass_codec: audio-codec@771c000 {
1725			compatible = "qcom,msm8916-wcd-digital-codec";
1726			reg = <0x0771c000 0x400>;
1727			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1728				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1729			clock-names = "ahbix-clk", "mclk";
1730			#sound-dai-cells = <1>;
1731			status = "disabled";
1732		};
1733
1734		sdhc_1: mmc@7824900 {
1735			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1736			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1737			reg-names = "hc", "core";
1738
1739			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1740				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1741			interrupt-names = "hc_irq", "pwr_irq";
1742			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1743				 <&gcc GCC_SDCC1_APPS_CLK>,
1744				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1745			clock-names = "iface", "core", "xo";
1746			resets = <&gcc GCC_SDCC1_BCR>;
1747			pinctrl-0 = <&sdc1_default>;
1748			pinctrl-1 = <&sdc1_sleep>;
1749			pinctrl-names = "default", "sleep";
1750			mmc-ddr-1_8v;
1751			bus-width = <8>;
1752			non-removable;
1753			status = "disabled";
1754		};
1755
1756		sdhc_2: mmc@7864900 {
1757			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1758			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1759			reg-names = "hc", "core";
1760
1761			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1762				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1763			interrupt-names = "hc_irq", "pwr_irq";
1764			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1765				 <&gcc GCC_SDCC2_APPS_CLK>,
1766				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1767			clock-names = "iface", "core", "xo";
1768			resets = <&gcc GCC_SDCC2_BCR>;
1769			pinctrl-0 = <&sdc2_default>;
1770			pinctrl-1 = <&sdc2_sleep>;
1771			pinctrl-names = "default", "sleep";
1772			bus-width = <4>;
1773			status = "disabled";
1774		};
1775
1776		blsp_dma: dma-controller@7884000 {
1777			compatible = "qcom,bam-v1.7.0";
1778			reg = <0x07884000 0x23000>;
1779			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1780			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1781			clock-names = "bam_clk";
1782			#dma-cells = <1>;
1783			qcom,ee = <0>;
1784			qcom,controlled-remotely;
1785		};
1786
1787		blsp_uart1: serial@78af000 {
1788			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1789			reg = <0x078af000 0x200>;
1790			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1791			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1792			clock-names = "core", "iface";
1793			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1794			dma-names = "tx", "rx";
1795			status = "disabled";
1796		};
1797
1798		blsp_uart2: serial@78b0000 {
1799			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1800			reg = <0x078b0000 0x200>;
1801			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1802			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1803			clock-names = "core", "iface";
1804			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1805			dma-names = "tx", "rx";
1806			status = "disabled";
1807		};
1808
1809		blsp_i2c1: i2c@78b5000 {
1810			compatible = "qcom,i2c-qup-v2.2.1";
1811			reg = <0x078b5000 0x500>;
1812			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1813			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1814				 <&gcc GCC_BLSP1_AHB_CLK>;
1815			clock-names = "core", "iface";
1816			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1817			dma-names = "tx", "rx";
1818			pinctrl-0 = <&blsp_i2c1_default>;
1819			pinctrl-1 = <&blsp_i2c1_sleep>;
1820			pinctrl-names = "default", "sleep";
1821			#address-cells = <1>;
1822			#size-cells = <0>;
1823			status = "disabled";
1824		};
1825
1826		blsp_spi1: spi@78b5000 {
1827			compatible = "qcom,spi-qup-v2.2.1";
1828			reg = <0x078b5000 0x500>;
1829			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1830			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1831				 <&gcc GCC_BLSP1_AHB_CLK>;
1832			clock-names = "core", "iface";
1833			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1834			dma-names = "tx", "rx";
1835			pinctrl-0 = <&blsp_spi1_default>;
1836			pinctrl-1 = <&blsp_spi1_sleep>;
1837			pinctrl-names = "default", "sleep";
1838			#address-cells = <1>;
1839			#size-cells = <0>;
1840			status = "disabled";
1841		};
1842
1843		blsp_i2c2: i2c@78b6000 {
1844			compatible = "qcom,i2c-qup-v2.2.1";
1845			reg = <0x078b6000 0x500>;
1846			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1847			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1848				 <&gcc GCC_BLSP1_AHB_CLK>;
1849			clock-names = "core", "iface";
1850			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1851			dma-names = "tx", "rx";
1852			pinctrl-0 = <&blsp_i2c2_default>;
1853			pinctrl-1 = <&blsp_i2c2_sleep>;
1854			pinctrl-names = "default", "sleep";
1855			#address-cells = <1>;
1856			#size-cells = <0>;
1857			status = "disabled";
1858		};
1859
1860		blsp_spi2: spi@78b6000 {
1861			compatible = "qcom,spi-qup-v2.2.1";
1862			reg = <0x078b6000 0x500>;
1863			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1864			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1865				 <&gcc GCC_BLSP1_AHB_CLK>;
1866			clock-names = "core", "iface";
1867			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1868			dma-names = "tx", "rx";
1869			pinctrl-0 = <&blsp_spi2_default>;
1870			pinctrl-1 = <&blsp_spi2_sleep>;
1871			pinctrl-names = "default", "sleep";
1872			#address-cells = <1>;
1873			#size-cells = <0>;
1874			status = "disabled";
1875		};
1876
1877		blsp_i2c3: i2c@78b7000 {
1878			compatible = "qcom,i2c-qup-v2.2.1";
1879			reg = <0x078b7000 0x500>;
1880			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1881			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1882				 <&gcc GCC_BLSP1_AHB_CLK>;
1883			clock-names = "core", "iface";
1884			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1885			dma-names = "tx", "rx";
1886			pinctrl-0 = <&blsp_i2c3_default>;
1887			pinctrl-1 = <&blsp_i2c3_sleep>;
1888			pinctrl-names = "default", "sleep";
1889			#address-cells = <1>;
1890			#size-cells = <0>;
1891			status = "disabled";
1892		};
1893
1894		blsp_spi3: spi@78b7000 {
1895			compatible = "qcom,spi-qup-v2.2.1";
1896			reg = <0x078b7000 0x500>;
1897			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1898			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1899				 <&gcc GCC_BLSP1_AHB_CLK>;
1900			clock-names = "core", "iface";
1901			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1902			dma-names = "tx", "rx";
1903			pinctrl-0 = <&blsp_spi3_default>;
1904			pinctrl-1 = <&blsp_spi3_sleep>;
1905			pinctrl-names = "default", "sleep";
1906			#address-cells = <1>;
1907			#size-cells = <0>;
1908			status = "disabled";
1909		};
1910
1911		blsp_i2c4: i2c@78b8000 {
1912			compatible = "qcom,i2c-qup-v2.2.1";
1913			reg = <0x078b8000 0x500>;
1914			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1915			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1916				 <&gcc GCC_BLSP1_AHB_CLK>;
1917			clock-names = "core", "iface";
1918			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1919			dma-names = "tx", "rx";
1920			pinctrl-0 = <&blsp_i2c4_default>;
1921			pinctrl-1 = <&blsp_i2c4_sleep>;
1922			pinctrl-names = "default", "sleep";
1923			#address-cells = <1>;
1924			#size-cells = <0>;
1925			status = "disabled";
1926		};
1927
1928		blsp_spi4: spi@78b8000 {
1929			compatible = "qcom,spi-qup-v2.2.1";
1930			reg = <0x078b8000 0x500>;
1931			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1932			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1933				 <&gcc GCC_BLSP1_AHB_CLK>;
1934			clock-names = "core", "iface";
1935			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1936			dma-names = "tx", "rx";
1937			pinctrl-0 = <&blsp_spi4_default>;
1938			pinctrl-1 = <&blsp_spi4_sleep>;
1939			pinctrl-names = "default", "sleep";
1940			#address-cells = <1>;
1941			#size-cells = <0>;
1942			status = "disabled";
1943		};
1944
1945		blsp_i2c5: i2c@78b9000 {
1946			compatible = "qcom,i2c-qup-v2.2.1";
1947			reg = <0x078b9000 0x500>;
1948			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1949			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1950				 <&gcc GCC_BLSP1_AHB_CLK>;
1951			clock-names = "core", "iface";
1952			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1953			dma-names = "tx", "rx";
1954			pinctrl-0 = <&blsp_i2c5_default>;
1955			pinctrl-1 = <&blsp_i2c5_sleep>;
1956			pinctrl-names = "default", "sleep";
1957			#address-cells = <1>;
1958			#size-cells = <0>;
1959			status = "disabled";
1960		};
1961
1962		blsp_spi5: spi@78b9000 {
1963			compatible = "qcom,spi-qup-v2.2.1";
1964			reg = <0x078b9000 0x500>;
1965			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1966			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1967				 <&gcc GCC_BLSP1_AHB_CLK>;
1968			clock-names = "core", "iface";
1969			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1970			dma-names = "tx", "rx";
1971			pinctrl-0 = <&blsp_spi5_default>;
1972			pinctrl-1 = <&blsp_spi5_sleep>;
1973			pinctrl-names = "default", "sleep";
1974			#address-cells = <1>;
1975			#size-cells = <0>;
1976			status = "disabled";
1977		};
1978
1979		blsp_i2c6: i2c@78ba000 {
1980			compatible = "qcom,i2c-qup-v2.2.1";
1981			reg = <0x078ba000 0x500>;
1982			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1983			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1984				 <&gcc GCC_BLSP1_AHB_CLK>;
1985			clock-names = "core", "iface";
1986			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1987			dma-names = "tx", "rx";
1988			pinctrl-0 = <&blsp_i2c6_default>;
1989			pinctrl-1 = <&blsp_i2c6_sleep>;
1990			pinctrl-names = "default", "sleep";
1991			#address-cells = <1>;
1992			#size-cells = <0>;
1993			status = "disabled";
1994		};
1995
1996		blsp_spi6: spi@78ba000 {
1997			compatible = "qcom,spi-qup-v2.2.1";
1998			reg = <0x078ba000 0x500>;
1999			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2000			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2001				 <&gcc GCC_BLSP1_AHB_CLK>;
2002			clock-names = "core", "iface";
2003			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2004			dma-names = "tx", "rx";
2005			pinctrl-0 = <&blsp_spi6_default>;
2006			pinctrl-1 = <&blsp_spi6_sleep>;
2007			pinctrl-names = "default", "sleep";
2008			#address-cells = <1>;
2009			#size-cells = <0>;
2010			status = "disabled";
2011		};
2012
2013		usb: usb@78d9000 {
2014			compatible = "qcom,ci-hdrc";
2015			reg = <0x078d9000 0x200>,
2016			      <0x078d9200 0x200>;
2017			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2018				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2019			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2020				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
2021			clock-names = "iface", "core";
2022			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2023			assigned-clock-rates = <80000000>;
2024			resets = <&gcc GCC_USB_HS_BCR>;
2025			reset-names = "core";
2026			#reset-cells = <1>;
2027			phy_type = "ulpi";
2028			dr_mode = "otg";
2029			adp-disable;
2030			hnp-disable;
2031			srp-disable;
2032			ahb-burst-config = <0>;
2033			phy-names = "usb-phy";
2034			phys = <&usb_hs_phy>;
2035			status = "disabled";
2036
2037			ulpi {
2038				usb_hs_phy: phy {
2039					compatible = "qcom,usb-hs-phy-msm8916",
2040						     "qcom,usb-hs-phy";
2041					clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2042						 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2043					clock-names = "ref", "sleep";
2044					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2045					reset-names = "phy", "por";
2046					#phy-cells = <0>;
2047					qcom,init-seq = /bits/ 8 <0x0 0x44>,
2048								 <0x1 0x6b>,
2049								 <0x2 0x24>,
2050								 <0x3 0x13>;
2051				};
2052			};
2053		};
2054
2055		wcnss: remoteproc@a204000 {
2056			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2057			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2058					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2059					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2060					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2061					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2062			interrupt-names = "wdog",
2063					  "fatal",
2064					  "ready",
2065					  "handover",
2066					  "stop-ack";
2067			reg = <0x0a204000 0x2000>,
2068			      <0x0a202000 0x1000>,
2069			      <0x0a21b000 0x3000>;
2070			reg-names = "ccu", "dxe", "pmu";
2071
2072			memory-region = <&wcnss_mem>;
2073
2074			power-domains = <&rpmpd MSM8939_VDDCX>,
2075					<&rpmpd MSM8939_VDDMX>;
2076			power-domain-names = "cx", "mx";
2077
2078			qcom,smem-states = <&wcnss_smp2p_out 0>;
2079			qcom,smem-state-names = "stop";
2080
2081			pinctrl-names = "default";
2082			pinctrl-0 = <&wcss_wlan_default>;
2083
2084			status = "disabled";
2085
2086			wcnss_iris: iris {
2087				/* Separate chip, compatible is board-specific */
2088				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2089				clock-names = "xo";
2090			};
2091
2092			smd-edge {
2093				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2094				mboxes = <&apcs1_mbox 17>;
2095				qcom,smd-edge = <6>;
2096				qcom,remote-pid = <4>;
2097
2098				label = "pronto";
2099
2100				wcnss {
2101					compatible = "qcom,wcnss";
2102					qcom,smd-channels = "WCNSS_CTRL";
2103
2104					qcom,mmio = <&wcnss>;
2105
2106					wcnss_bt: bluetooth {
2107						compatible = "qcom,wcnss-bt";
2108					};
2109
2110					wcnss_wifi: wifi {
2111						compatible = "qcom,wcnss-wlan";
2112
2113						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2114							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2115						interrupt-names = "tx", "rx";
2116
2117						qcom,smem-states = <&apps_smsm 10>,
2118								   <&apps_smsm 9>;
2119						qcom,smem-state-names = "tx-enable",
2120									"tx-rings-empty";
2121					};
2122				};
2123			};
2124		};
2125
2126		intc: interrupt-controller@b000000 {
2127			compatible = "qcom,msm-qgic2";
2128			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2129			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2130			interrupt-controller;
2131			#interrupt-cells = <3>;
2132			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2133		};
2134
2135		apcs1_mbox: mailbox@b011000 {
2136			compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2137			reg = <0x0b011000 0x1000>;
2138			clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2139			clock-names = "pll", "aux", "ref";
2140			#clock-cells = <0>;
2141			assigned-clocks = <&apcs2>;
2142			assigned-clock-rates = <297600000>;
2143			#mbox-cells = <1>;
2144		};
2145
2146		a53pll_c1: clock@b016000 {
2147			compatible = "qcom,msm8939-a53pll";
2148			reg = <0x0b016000 0x40>;
2149			#clock-cells = <0>;
2150		};
2151
2152		acc0: clock-controller@b088000 {
2153			compatible = "qcom,kpss-acc-v2";
2154			reg = <0x0b088000 0x1000>;
2155		};
2156
2157		saw0: power-manager@b089000 {
2158			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2159			reg = <0x0b089000 0x1000>;
2160		};
2161
2162		acc1: clock-controller@b098000 {
2163			compatible = "qcom,kpss-acc-v2";
2164			reg = <0x0b098000 0x1000>;
2165		};
2166
2167		saw1: power-manager@b099000 {
2168			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2169			reg = <0x0b099000 0x1000>;
2170		};
2171
2172		acc2: clock-controller@b0a8000 {
2173			compatible = "qcom,kpss-acc-v2";
2174			reg = <0x0b0a8000 0x1000>;
2175		};
2176
2177		saw2: power-manager@b0a9000 {
2178			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2179			reg = <0x0b0a9000 0x1000>;
2180		};
2181
2182		acc3: clock-controller@b0b8000 {
2183			compatible = "qcom,kpss-acc-v2";
2184			reg = <0x0b0b8000 0x1000>;
2185		};
2186
2187		saw3: power-manager@b0b9000 {
2188			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2189			reg = <0x0b0b9000 0x1000>;
2190		};
2191
2192		apcs0_mbox: mailbox@b111000 {
2193			compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2194			reg = <0x0b111000 0x1000>;
2195			clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2196			clock-names = "pll", "aux", "ref";
2197			#clock-cells = <0>;
2198			#mbox-cells = <1>;
2199		};
2200
2201		a53pll_c0: clock@b116000 {
2202			compatible = "qcom,msm8939-a53pll";
2203			reg = <0x0b116000 0x40>;
2204			#clock-cells = <0>;
2205		};
2206
2207		timer@b120000 {
2208			compatible = "arm,armv7-timer-mem";
2209			reg = <0x0b120000 0x1000>;
2210			#address-cells = <1>;
2211			#size-cells = <1>;
2212			ranges;
2213			/* Necessary because firmware does not configure this correctly */
2214			clock-frequency = <19200000>;
2215
2216			frame@b121000 {
2217				reg = <0x0b121000 0x1000>,
2218				      <0x0b122000 0x1000>;
2219				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2220					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2221				frame-number = <0>;
2222			};
2223
2224			frame@b123000 {
2225				reg = <0x0b123000 0x1000>;
2226				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2227				frame-number = <1>;
2228				status = "disabled";
2229			};
2230
2231			frame@b124000 {
2232				reg = <0x0b124000 0x1000>;
2233				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2234				frame-number = <2>;
2235				status = "disabled";
2236			};
2237
2238			frame@b125000 {
2239				reg = <0x0b125000 0x1000>;
2240				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2241				frame-number = <3>;
2242				status = "disabled";
2243			};
2244
2245			frame@b126000 {
2246				reg = <0x0b126000 0x1000>;
2247				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2248				frame-number = <4>;
2249				status = "disabled";
2250			};
2251
2252			frame@b127000 {
2253				reg = <0x0b127000 0x1000>;
2254				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2255				frame-number = <5>;
2256				status = "disabled";
2257			};
2258
2259			frame@b128000 {
2260				reg = <0x0b128000 0x1000>;
2261				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2262				frame-number = <6>;
2263				status = "disabled";
2264			};
2265		};
2266
2267		acc4: clock-controller@b188000 {
2268			compatible = "qcom,kpss-acc-v2";
2269			reg = <0x0b188000 0x1000>;
2270		};
2271
2272		saw4: power-manager@b189000 {
2273			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2274			reg = <0x0b189000 0x1000>;
2275		};
2276
2277		acc5: clock-controller@b198000 {
2278			compatible = "qcom,kpss-acc-v2";
2279			reg = <0x0b198000 0x1000>;
2280		};
2281
2282		saw5: power-manager@b199000 {
2283			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2284			reg = <0x0b199000 0x1000>;
2285		};
2286
2287		acc6: clock-controller@b1a8000 {
2288			compatible = "qcom,kpss-acc-v2";
2289			reg = <0x0b1a8000 0x1000>;
2290		};
2291
2292		saw6: power-manager@b1a9000 {
2293			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2294			reg = <0x0b1a9000 0x1000>;
2295		};
2296
2297		acc7: clock-controller@b1b8000 {
2298			compatible = "qcom,kpss-acc-v2";
2299			reg = <0x0b1b8000 0x1000>;
2300		};
2301
2302		saw7: power-manager@b1b9000 {
2303			compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2304			reg = <0x0b1b9000 0x1000>;
2305		};
2306
2307		a53pll_cci: clock@b1d0000 {
2308			compatible = "qcom,msm8939-a53pll";
2309			reg = <0x0b1d0000 0x40>;
2310			#clock-cells = <0>;
2311		};
2312
2313		apcs2: mailbox@b1d1000 {
2314			compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2315			reg = <0x0b1d1000 0x1000>;
2316			clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2317			clock-names = "pll", "aux", "ref";
2318			#clock-cells = <0>;
2319			#mbox-cells = <1>;
2320		};
2321	};
2322
2323	thermal_zones: thermal-zones {
2324		cpu0-thermal {
2325			polling-delay-passive = <250>;
2326
2327			thermal-sensors = <&tsens 5>;
2328
2329			trips {
2330				cpu0_alert: trip0 {
2331					temperature = <75000>;
2332					hysteresis = <2000>;
2333					type = "passive";
2334				};
2335
2336				cpu0_crit: trip1 {
2337					temperature = <115000>;
2338					hysteresis = <0>;
2339					type = "critical";
2340				};
2341			};
2342
2343			cooling-maps {
2344				map0 {
2345					trip = <&cpu0_alert>;
2346					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2347							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2348							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2349							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2350				};
2351			};
2352		};
2353
2354		cpu1-thermal {
2355			polling-delay-passive = <250>;
2356
2357			thermal-sensors = <&tsens 6>;
2358
2359			trips {
2360				cpu1_alert: trip0 {
2361					temperature = <75000>;
2362					hysteresis = <2000>;
2363					type = "passive";
2364				};
2365
2366				cpu1_crit: trip1 {
2367					temperature = <110000>;
2368					hysteresis = <2000>;
2369					type = "critical";
2370				};
2371			};
2372
2373			cooling-maps {
2374				map0 {
2375					trip = <&cpu1_alert>;
2376					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2377							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2378							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2379							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2380				};
2381			};
2382		};
2383
2384		cpu2-thermal {
2385			polling-delay-passive = <250>;
2386
2387			thermal-sensors = <&tsens 7>;
2388
2389			trips {
2390				cpu2_alert: trip0 {
2391					temperature = <75000>;
2392					hysteresis = <2000>;
2393					type = "passive";
2394				};
2395
2396				cpu2_crit: trip1 {
2397					temperature = <110000>;
2398					hysteresis = <2000>;
2399					type = "critical";
2400				};
2401			};
2402
2403			cooling-maps {
2404				map0 {
2405					trip = <&cpu2_alert>;
2406					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2407							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2408							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2409							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2410				};
2411			};
2412		};
2413
2414		cpu3-thermal {
2415			polling-delay-passive = <250>;
2416
2417			thermal-sensors = <&tsens 8>;
2418
2419			trips {
2420				cpu3_alert: trip0 {
2421					temperature = <75000>;
2422					hysteresis = <2000>;
2423					type = "passive";
2424				};
2425
2426				cpu3_crit: trip1 {
2427					temperature = <110000>;
2428					hysteresis = <2000>;
2429					type = "critical";
2430				};
2431			};
2432
2433			cooling-maps {
2434				map0 {
2435					trip = <&cpu3_alert>;
2436					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2437							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2438							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2439							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2440				};
2441			};
2442		};
2443
2444		cpu4567-thermal {
2445			polling-delay-passive = <250>;
2446
2447			thermal-sensors = <&tsens 9>;
2448
2449			trips {
2450				cpu4567_alert: trip0 {
2451					temperature = <75000>;
2452					hysteresis = <2000>;
2453					type = "passive";
2454				};
2455
2456				cpu4567_crit: trip1 {
2457					temperature = <110000>;
2458					hysteresis = <2000>;
2459					type = "critical";
2460				};
2461			};
2462
2463			cooling-maps {
2464				map0 {
2465					trip = <&cpu4567_alert>;
2466					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2467							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2468							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2469							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2470				};
2471			};
2472		};
2473
2474		gpu-thermal {
2475			polling-delay-passive = <250>;
2476
2477			thermal-sensors = <&tsens 3>;
2478
2479			cooling-maps {
2480				map0 {
2481					trip = <&gpu_alert0>;
2482					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2483				};
2484			};
2485
2486			trips {
2487				gpu_alert0: trip-point0 {
2488					temperature = <75000>;
2489					hysteresis = <2000>;
2490					type = "passive";
2491				};
2492
2493				gpu_crit: gpu-crit {
2494					temperature = <95000>;
2495					hysteresis = <2000>;
2496					type = "critical";
2497				};
2498			};
2499		};
2500
2501		modem1-thermal {
2502			polling-delay-passive = <250>;
2503
2504			thermal-sensors = <&tsens 0>;
2505
2506			trips {
2507				modem1_alert0: trip-point0 {
2508					temperature = <85000>;
2509					hysteresis = <2000>;
2510					type = "hot";
2511				};
2512			};
2513		};
2514
2515		modem2-thermal {
2516			polling-delay-passive = <250>;
2517
2518			thermal-sensors = <&tsens 2>;
2519
2520			trips {
2521				modem2_alert0: trip-point0 {
2522					temperature = <85000>;
2523					hysteresis = <2000>;
2524					type = "hot";
2525				};
2526			};
2527		};
2528
2529		camera-thermal {
2530			polling-delay-passive = <250>;
2531
2532			thermal-sensors = <&tsens 1>;
2533
2534			trips {
2535				cam_alert0: trip-point0 {
2536					temperature = <75000>;
2537					hysteresis = <2000>;
2538					type = "hot";
2539				};
2540			};
2541		};
2542	};
2543
2544	timer {
2545		compatible = "arm,armv8-timer";
2546		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2547			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2548			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2549			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2550	};
2551};
2552