1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_4_1_0_SH_MASK_HEADER 24 #define _mmhub_4_1_0_SH_MASK_HEADER 25 26 27 // addressBlock: mmhub_dagb_dagbdec 28 //DAGB0_RDCLI0 29 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 //DAGB0_RDCLI1 50 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 //DAGB0_RDCLI2 71 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 //DAGB0_RDCLI3 92 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 //DAGB0_RDCLI4 113 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 //DAGB0_RDCLI5 134 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 //DAGB0_RDCLI6 155 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 //DAGB0_RDCLI7 176 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 //DAGB0_RDCLI8 197 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 //DAGB0_RDCLI9 218 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 //DAGB0_RDCLI10 239 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 //DAGB0_RDCLI11 260 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 //DAGB0_RDCLI12 281 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 //DAGB0_RDCLI13 302 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 //DAGB0_RDCLI14 323 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 //DAGB0_RDCLI15 344 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 //DAGB0_RDCLI16 365 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367 #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368 #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369 #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370 #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371 #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372 #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374 #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375 #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377 #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378 #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379 #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380 #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381 #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382 #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384 #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385 //DAGB0_RDCLI17 386 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388 #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389 #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390 #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391 #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392 #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393 #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395 #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396 #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398 #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399 #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400 #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401 #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402 #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403 #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405 #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406 //DAGB0_RDCLI18 407 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409 #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410 #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411 #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412 #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413 #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414 #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416 #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417 #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419 #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420 #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421 #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422 #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423 #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424 #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426 #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427 //DAGB0_RDCLI19 428 #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430 #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431 #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432 #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433 #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434 #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435 #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437 #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438 #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440 #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441 #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442 #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443 #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444 #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445 #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447 #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448 //DAGB0_RDCLI20 449 #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451 #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452 #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453 #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454 #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455 #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456 #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458 #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459 #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461 #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462 #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463 #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464 #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465 #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466 #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468 #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469 //DAGB0_RDCLI21 470 #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472 #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473 #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474 #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475 #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476 #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477 #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479 #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480 #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482 #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483 #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484 #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485 #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486 #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487 #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489 #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490 //DAGB0_RDCLI22 491 #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493 #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494 #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495 #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496 #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497 #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498 #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500 #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501 #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503 #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504 #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505 #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506 #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507 #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508 #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510 #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511 //DAGB0_RDCLI23 512 #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514 #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515 #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516 #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517 #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518 #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519 #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521 #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522 #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524 #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525 #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526 #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527 #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528 #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529 #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531 #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532 //DAGB0_RD_CNTL 533 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 534 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 535 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 536 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 537 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 538 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 539 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 540 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 541 //DAGB0_RD_IO_CNTL 542 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 543 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 544 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 545 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 546 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 547 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 548 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 549 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 550 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 551 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 552 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 553 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 554 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 555 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 556 //DAGB0_RD_GMI_CNTL 557 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 558 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 559 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 560 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 561 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 562 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 563 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 564 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 565 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 566 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 567 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 568 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 569 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 570 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 571 //DAGB0_RD_ADDR_DAGB 572 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 573 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 574 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 575 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x9 576 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xf 577 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL 578 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L 579 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L 580 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00007E00L 581 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L 582 //DAGB0_RD_CGTT_CLK_CTRL 583 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 584 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 585 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 586 #define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 587 #define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 588 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 589 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 590 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 591 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 592 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 593 #define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 594 #define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 595 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 596 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 597 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 598 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 599 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 600 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 601 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 602 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 603 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 604 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 605 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 606 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 607 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 608 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 609 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 610 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 611 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 612 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 613 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 614 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 615 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 616 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 617 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 618 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 619 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 620 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 621 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 622 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 623 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 624 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 625 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 626 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 627 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 628 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 629 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 630 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 631 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 632 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 633 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 634 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 635 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 636 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 637 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 638 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 639 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 640 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 641 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 642 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 643 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 644 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 645 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 646 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 647 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 648 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 649 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 650 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 651 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 652 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 653 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 654 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 655 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 656 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 657 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 658 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 659 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 660 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 661 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 662 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 663 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 664 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 665 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 666 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 667 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 668 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 669 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 670 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 671 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 672 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 673 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 674 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 675 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 676 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 677 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 678 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 679 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 680 //DAGB0_RD_ADDR_DAGB_MAX_BURST2 681 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 682 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 683 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 684 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 685 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 686 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 687 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 688 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 689 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 690 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 691 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 692 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 693 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 694 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 695 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 696 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 697 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 698 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 699 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 700 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 701 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 702 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 703 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 704 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 705 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 706 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 707 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 708 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 709 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 710 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 711 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 712 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 713 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 714 //DAGB0_RD_VC0_CNTL 715 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 716 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 717 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 718 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 719 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 720 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 721 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 722 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 723 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 724 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 725 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 726 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 727 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 728 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 729 //DAGB0_RD_VC1_CNTL 730 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 731 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 732 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 733 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 734 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 735 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 736 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 737 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 738 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 739 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 740 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 741 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 742 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 743 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 744 //DAGB0_RD_VC2_CNTL 745 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 746 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 747 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 748 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 749 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 750 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 751 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 752 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 753 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 754 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 755 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 756 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 757 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 758 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 759 //DAGB0_RD_VC3_CNTL 760 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 761 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 762 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 763 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 764 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 765 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 766 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 767 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 768 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 769 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 770 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 771 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 772 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 773 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 774 //DAGB0_RD_VC4_CNTL 775 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 776 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 777 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 778 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 779 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 780 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 781 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 782 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 783 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 784 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 785 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 786 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 787 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 788 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 789 //DAGB0_RD_VC5_CNTL 790 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 791 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 792 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 793 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 794 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 795 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 796 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 797 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 798 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 799 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 800 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 801 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 802 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 803 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 804 //DAGB0_RD_IO_VC_CNTL 805 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 806 #define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 807 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 808 #define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 809 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 810 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 811 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 812 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 813 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 814 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 815 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 816 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 817 //DAGB0_RD_GMI_VC_CNTL 818 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 819 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 820 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 821 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 822 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 823 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 824 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 825 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 826 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 827 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 828 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 829 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 830 //DAGB0_RD_CNTL_MISC 831 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 832 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 833 #define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 834 #define DAGB0_RD_CNTL_MISC__IO_BYPASS_COMPRESSION__SHIFT 0xa 835 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 836 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 837 #define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 838 //DAGB0_RD_TLB_CREDIT 839 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 840 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 841 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 842 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 843 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 844 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 845 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 846 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 847 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 848 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 849 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 850 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 851 //DAGB0_RDCLI_ASK_PENDING 852 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 853 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL 854 //DAGB0_RDCLI_GO_PENDING 855 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 856 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL 857 //DAGB0_RDCLI_GBLSEND_PENDING 858 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 859 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL 860 //DAGB0_RDCLI_TLB_PENDING 861 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 862 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL 863 //DAGB0_RDCLI_OARB_PENDING 864 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 865 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL 866 //DAGB0_RDCLI_ASK2ARB_PENDING 867 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 868 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0x00FFFFFFL 869 //DAGB0_RDCLI_ASK2DF_PENDING 870 #define DAGB0_RDCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 871 //DAGB0_RDCLI_OSD_PENDING 872 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 873 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 874 //DAGB0_RDCLI_ASK_OSD_PENDING 875 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 876 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 877 //DAGB0_WRCLI0 878 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 879 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 880 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 881 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 882 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 883 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 884 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 885 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 886 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 887 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 888 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 889 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 890 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 891 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 892 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 893 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 894 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 895 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 896 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 897 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 898 //DAGB0_WRCLI1 899 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 900 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 901 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 902 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 903 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 904 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 905 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 906 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 907 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 908 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 909 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 910 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 911 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 912 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 913 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 914 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 915 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 916 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 917 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 918 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 919 //DAGB0_WRCLI2 920 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 921 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 922 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 923 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 924 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 925 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 926 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 927 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 928 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 929 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 930 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 931 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 932 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 933 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 934 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 935 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 936 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 937 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 938 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 939 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 940 //DAGB0_WRCLI3 941 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 942 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 943 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 944 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 945 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 946 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 947 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 948 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 949 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 950 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 951 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 952 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 953 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 954 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 955 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 956 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 957 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 958 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 959 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 960 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 961 //DAGB0_WRCLI4 962 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 963 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 964 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 965 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 966 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 967 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 968 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 969 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 970 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 971 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 972 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 973 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 974 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 975 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 976 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 977 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 978 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 979 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 980 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 981 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 982 //DAGB0_WRCLI5 983 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 984 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 985 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 986 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 987 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 988 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 989 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 990 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 991 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 992 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 993 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 994 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 995 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 996 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 997 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 998 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 999 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1000 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1001 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1002 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1003 //DAGB0_WRCLI6 1004 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1005 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1006 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1007 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1008 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1009 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1010 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1011 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1012 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1013 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1014 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1015 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1016 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1017 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1018 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1019 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1020 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1021 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1022 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1023 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1024 //DAGB0_WRCLI7 1025 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1026 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1027 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1028 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1029 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1030 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1031 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1032 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1033 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1034 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1035 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1036 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1037 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1038 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1039 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1040 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1041 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1042 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1043 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1044 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1045 //DAGB0_WRCLI8 1046 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1047 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1048 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1049 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1050 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1051 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1052 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1053 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1054 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1055 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1056 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1057 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1058 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1059 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1060 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1061 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1062 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1063 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1064 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1065 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1066 //DAGB0_WRCLI9 1067 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1068 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1069 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1070 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1071 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1072 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1073 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1074 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1075 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1076 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1077 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1078 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1079 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1080 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1081 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1082 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1083 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1084 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1085 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1086 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1087 //DAGB0_WRCLI10 1088 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1089 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1090 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1091 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1092 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1093 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1094 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1095 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1096 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1097 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1098 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1099 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1100 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1101 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1102 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1103 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1104 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1105 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1106 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1107 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1108 //DAGB0_WRCLI11 1109 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1110 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1111 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1112 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1113 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1114 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1115 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1116 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1117 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1118 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1119 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1120 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1121 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1122 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1123 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1124 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1125 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1126 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1127 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1128 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1129 //DAGB0_WRCLI12 1130 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1131 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1132 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1133 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1134 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1135 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1136 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1137 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1138 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1139 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1140 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1141 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1142 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1143 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1144 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1145 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1146 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1147 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1148 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1149 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1150 //DAGB0_WRCLI13 1151 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1152 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1153 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1154 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1155 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1156 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1157 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1158 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1159 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1160 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1161 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1162 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1163 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1164 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1165 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1166 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1167 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1168 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1169 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1170 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1171 //DAGB0_WRCLI14 1172 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1173 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1174 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1175 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1176 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1177 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1178 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1179 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1180 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1181 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1182 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1183 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1184 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1185 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1186 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1187 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1188 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1189 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1190 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1191 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1192 //DAGB0_WRCLI15 1193 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1194 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1195 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1196 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1197 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1198 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1199 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1200 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1201 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1202 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1203 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1204 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1205 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1206 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1207 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1208 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1209 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1210 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1211 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1212 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1213 //DAGB0_WRCLI16 1214 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1215 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1216 #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1217 #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1218 #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1219 #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1220 #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1221 #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1222 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1223 #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1224 #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1225 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1226 #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1227 #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1228 #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1229 #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1230 #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1231 #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1232 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1233 #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1234 //DAGB0_WRCLI17 1235 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1236 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1237 #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1238 #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1239 #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1240 #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1241 #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1242 #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1243 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1244 #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1245 #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1246 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1247 #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1248 #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1249 #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1250 #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1251 #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1252 #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1253 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1254 #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1255 //DAGB0_WRCLI18 1256 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1257 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1258 #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1259 #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1260 #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1261 #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1262 #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1263 #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1264 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1265 #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1266 #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1267 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1268 #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1269 #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1270 #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1271 #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1272 #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1273 #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1274 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1275 #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1276 //DAGB0_WRCLI19 1277 #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1278 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1279 #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1280 #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1281 #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1282 #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1283 #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1284 #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1285 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1286 #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1287 #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1288 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1289 #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1290 #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1291 #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1292 #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1293 #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1294 #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1295 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1296 #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1297 //DAGB0_WRCLI20 1298 #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1299 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1300 #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1301 #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1302 #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1303 #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1304 #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1305 #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1306 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1307 #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1308 #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1309 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1310 #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1311 #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1312 #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1313 #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1314 #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1315 #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1316 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1317 #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1318 //DAGB0_WRCLI21 1319 #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1320 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1321 #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1322 #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1323 #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1324 #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1325 #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1326 #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1327 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1328 #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1329 #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1330 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1331 #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1332 #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1333 #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1334 #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1335 #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1336 #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1337 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1338 #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1339 //DAGB0_WRCLI22 1340 #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1341 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1342 #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1343 #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1344 #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1345 #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1346 #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1347 #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1348 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1349 #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1350 #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1351 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1352 #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1353 #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1354 #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1355 #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1356 #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1357 #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1358 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1359 #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1360 //DAGB0_WRCLI23 1361 #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1362 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1363 #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1364 #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1365 #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1366 #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1367 #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1368 #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1369 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1370 #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1371 #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1372 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1373 #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1374 #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1375 #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1376 #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1377 #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1378 #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1379 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1380 #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1381 //DAGB0_WR_CNTL 1382 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 1383 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 1384 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc 1385 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 1386 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 1387 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L 1388 //DAGB0_WR_IO_CNTL 1389 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1390 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1391 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1392 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1393 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1394 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1395 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 1396 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1397 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1398 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1399 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1400 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1401 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1402 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1403 //DAGB0_WR_GMI_CNTL 1404 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1405 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1406 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1407 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1408 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1409 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1410 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 1411 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1412 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1413 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1414 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1415 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1416 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1417 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1418 //DAGB0_WR_ADDR_DAGB 1419 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1420 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 1421 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 1422 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x9 1423 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xf 1424 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL 1425 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L 1426 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L 1427 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00007E00L 1428 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L 1429 //DAGB0_WR_CGTT_CLK_CTRL 1430 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1431 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1432 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1433 #define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 1434 #define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 1435 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1436 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1437 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1438 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1439 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 1440 #define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 1441 #define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 1442 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1443 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1444 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1445 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1446 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1447 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1448 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 1449 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 1450 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1451 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1452 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1453 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1454 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 1455 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 1456 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 1457 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1458 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1459 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1460 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1461 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1462 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1463 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1464 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1465 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1466 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1467 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1468 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1469 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1470 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1471 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1472 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1473 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1474 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1475 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1476 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1477 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1478 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1479 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1480 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1481 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1482 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1483 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1484 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1485 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1486 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1487 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1488 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1489 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1490 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1491 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1492 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1493 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1494 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1495 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1496 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1497 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1498 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1499 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1500 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1501 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1502 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1503 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1504 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1505 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1506 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1507 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1508 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1509 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1510 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1511 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1512 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1513 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1514 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1515 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1516 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1517 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1518 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1519 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1520 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1521 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1522 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1523 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1524 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1525 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1526 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1527 //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1528 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1529 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1530 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1531 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1532 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1533 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1534 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1535 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1536 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1537 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1538 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1539 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1540 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1541 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1542 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1543 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1544 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1545 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1546 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1547 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1548 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1549 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1550 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1551 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1552 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1553 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1554 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1555 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1556 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1557 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1558 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1559 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1560 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1561 //DAGB0_WR_DATA_DAGB 1562 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1563 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 1564 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 1565 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x9 1566 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x0000000FL 1567 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L 1568 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L 1569 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00007E00L 1570 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1571 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1572 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1573 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1574 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1575 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1576 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1577 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1578 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1579 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1580 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1581 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1582 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1583 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1584 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1585 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1586 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1587 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1588 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1589 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1590 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1591 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1592 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1593 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1594 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1595 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1596 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1597 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1598 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1599 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1600 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1601 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1602 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1603 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1604 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1605 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1606 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1607 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1608 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1609 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1610 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1611 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1612 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1613 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1614 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1615 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1616 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1617 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1618 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1619 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1620 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1621 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1622 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1623 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1624 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1625 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1626 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1627 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1628 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1629 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1630 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1631 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1632 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1633 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1634 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1635 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1636 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1637 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1638 //DAGB0_WR_DATA_DAGB_MAX_BURST2 1639 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1640 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1641 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1642 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1643 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1644 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1645 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1646 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1647 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1648 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1649 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1650 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1651 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1652 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1653 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1654 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1655 //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1656 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1657 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1658 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1659 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1660 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1661 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1662 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1663 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1664 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1665 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1666 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1667 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1668 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1669 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1670 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1671 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1672 //DAGB0_WR_VC0_CNTL 1673 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1674 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1675 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1676 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1677 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1678 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1679 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1680 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1681 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1682 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1683 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1684 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1685 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1686 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1687 //DAGB0_WR_VC1_CNTL 1688 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1689 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1690 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1691 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1692 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1693 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1694 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1695 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1696 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1697 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1698 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1699 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1700 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1701 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1702 //DAGB0_WR_VC2_CNTL 1703 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1704 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1705 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1706 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1707 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1708 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1709 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1710 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1711 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1712 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1713 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1714 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1715 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1716 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1717 //DAGB0_WR_VC3_CNTL 1718 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1719 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1720 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1721 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1722 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1723 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1724 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1725 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1726 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1727 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1728 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1729 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1730 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1731 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1732 //DAGB0_WR_VC4_CNTL 1733 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1734 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1735 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1736 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1737 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1738 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1739 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1740 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1741 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1742 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1743 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1744 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1745 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1746 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1747 //DAGB0_WR_VC5_CNTL 1748 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1749 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1750 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1751 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1752 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1753 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1754 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1755 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1756 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1757 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1758 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1759 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1760 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1761 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1762 //DAGB0_WR_IO_VC_CNTL 1763 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1764 #define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc 1765 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1766 #define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 1767 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1768 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 1769 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1770 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 1771 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1772 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 1773 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1774 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1775 //DAGB0_WR_GMI_VC_CNTL 1776 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1777 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 1778 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1779 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 1780 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1781 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 1782 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1783 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 1784 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1785 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 1786 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1787 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1788 //DAGB0_WR_CNTL_MISC 1789 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1790 #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 1791 #define DAGB0_WR_CNTL_MISC__FORCE_BYPASS_DCC__SHIFT 0xb 1792 #define DAGB0_WR_CNTL_MISC__DCC_FORCE_BYPASS_128B__SHIFT 0xc 1793 #define DAGB0_WR_CNTL_MISC__MAP_COMP_MODE0__SHIFT 0xd 1794 #define DAGB0_WR_CNTL_MISC__IO_BYPASS_COMPRESSION__SHIFT 0xe 1795 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1796 #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L 1797 //DAGB0_WR_TLB_CREDIT 1798 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1799 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1800 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1801 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1802 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1803 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1804 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1805 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1806 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1807 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1808 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1809 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1810 //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 1811 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1812 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1813 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1814 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1815 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1816 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 1817 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 1818 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 1819 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1820 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1821 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1822 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1823 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 1824 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 1825 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 1826 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 1827 //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 1828 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1829 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1830 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1831 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1832 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1833 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a 1834 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_STORE__SHIFT 0x1b 1835 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_ATOMIC__SHIFT 0x1c 1836 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1837 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1838 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1839 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1840 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L 1841 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L 1842 //DAGB0_WRCLI_ASK_PENDING 1843 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1844 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL 1845 //DAGB0_WRCLI_GO_PENDING 1846 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1847 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL 1848 //DAGB0_WRCLI_GBLSEND_PENDING 1849 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1850 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL 1851 //DAGB0_WRCLI_TLB_PENDING 1852 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1853 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL 1854 //DAGB0_WRCLI_OARB_PENDING 1855 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1856 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL 1857 //DAGB0_WRCLI_ASK2ARB_PENDING 1858 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 1859 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0x00FFFFFFL 1860 //DAGB0_WRCLI_ASK2DF_PENDING 1861 #define DAGB0_WRCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 1862 //DAGB0_WRCLI_OSD_PENDING 1863 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1864 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 1865 //DAGB0_WRCLI_ASK_OSD_PENDING 1866 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 1867 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 1868 //DAGB0_WRCLI_DBUS_ASK_PENDING 1869 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1870 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0x00FFFFFFL 1871 //DAGB0_WRCLI_DBUS_GO_PENDING 1872 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1873 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0x00FFFFFFL 1874 //DAGB0_SDP_ERR_STATUS 1875 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 1876 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 1877 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 1878 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR__SHIFT 0xa 1879 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xb 1880 #define DAGB0_SDP_ERR_STATUS__WR_DATAPARITY_ERROR__SHIFT 0xc 1881 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd 1882 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe 1883 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xf 1884 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x10 1885 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 1886 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 1887 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 1888 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000800L 1889 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L 1890 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L 1891 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00008000L 1892 //DAGB0_DAGB_DLY 1893 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1894 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1895 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1896 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1897 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1898 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1899 //DAGB0_CNTL_MISC 1900 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 1901 #define DAGB0_CNTL_MISC__CLI_FATAL_EDGE_MODE__SHIFT 0x6 1902 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 1903 //DAGB0_CNTL_MISC2 1904 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 1905 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 1906 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 1907 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 1908 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 1909 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 1910 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x6 1911 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x7 1912 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x8 1913 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 1914 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 1915 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 1916 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 1917 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 1918 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 1919 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000040L 1920 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000080L 1921 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000100L 1922 //DAGB0_FIFO_EMPTY 1923 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1924 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 1925 //DAGB0_FIFO_FULL 1926 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1927 #define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL 1928 //DAGB0_RD_CREDITS_FULL 1929 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1930 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 1931 //DAGB0_WR_CREDITS_FULL 1932 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1933 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL 1934 //DAGB0_PERFCOUNTER_LO 1935 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1936 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1937 //DAGB0_PERFCOUNTER_HI 1938 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1939 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1940 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1941 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1942 //DAGB0_PERFCOUNTER0_CFG 1943 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1944 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1945 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1946 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1947 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1948 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1949 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1950 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1951 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1952 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1953 //DAGB0_PERFCOUNTER1_CFG 1954 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1955 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1956 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1957 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1958 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1959 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1960 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1961 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1962 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1963 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1964 //DAGB0_PERFCOUNTER2_CFG 1965 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1966 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1967 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1968 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1969 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1970 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1971 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1972 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1973 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1974 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1975 //DAGB0_PERFCOUNTER_RSLT_CNTL 1976 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1977 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1978 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1979 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1980 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1981 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1982 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1983 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1984 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1985 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1986 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1987 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1988 //DAGB0_L1TLB_REG_RW 1989 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 1990 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 1991 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 1992 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 1993 //DAGB0_RESERVE0 1994 #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1995 #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1996 //DAGB0_RESERVE1 1997 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1998 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1999 //DAGB0_RESERVE2 2000 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2001 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2002 //DAGB0_RESERVE3 2003 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2004 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2005 //DAGB0_SDP_RD_BW_CNTL 2006 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2007 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 2008 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0xb 2009 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xc 2010 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0x12 2011 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2012 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000007FEL 2013 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000800L 2014 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x0003F000L 2015 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x07FC0000L 2016 //DAGB0_SDP_PRIORITY_OVERRIDE 2017 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 2018 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2019 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 2020 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 2021 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 2022 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 2023 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 2024 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 2025 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 2026 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 2027 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 2028 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 2029 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 2030 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 2031 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 2032 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 2033 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 2034 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2035 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 2036 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 2037 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 2038 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 2039 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 2040 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 2041 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 2042 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 2043 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 2044 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 2045 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 2046 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 2047 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 2048 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 2049 //DAGB0_SDP_RD_PRIORITY 2050 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 2051 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 2052 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 2053 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 2054 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 2055 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 2056 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 2057 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 2058 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 2059 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 2060 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 2061 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 2062 //DAGB0_SDP_WR_PRIORITY 2063 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 2064 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 2065 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 2066 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc 2067 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 2068 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 2069 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL 2070 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L 2071 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L 2072 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L 2073 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L 2074 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L 2075 //DAGB0_SDP_RD_CLI2SDP_VC_MAP 2076 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2077 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2078 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2079 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2080 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2081 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2082 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2083 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2084 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2085 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2086 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2087 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2088 //DAGB0_SDP_WR_CLI2SDP_VC_MAP 2089 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2090 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2091 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2092 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2093 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2094 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2095 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2096 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2097 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2098 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2099 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2100 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2101 //DAGB0_SDP_ENABLE 2102 #define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 2103 #define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L 2104 //DAGB0_SDP_CREDITS 2105 #define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 2106 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 2107 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 2108 #define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 2109 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 2110 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 2111 //DAGB0_SDP_TAG_RESERVE0 2112 #define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 2113 #define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 2114 #define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 2115 #define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 2116 #define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 2117 #define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 2118 #define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 2119 #define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 2120 //DAGB0_SDP_TAG_RESERVE1 2121 #define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 2122 #define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 2123 #define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 2124 #define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 2125 #define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 2126 #define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 2127 #define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 2128 #define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 2129 //DAGB0_SDP_VCC_RESERVE0 2130 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 2131 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 2132 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 2133 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 2134 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 2135 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2136 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2137 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2138 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2139 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2140 //DAGB0_SDP_VCC_RESERVE1 2141 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 2142 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 2143 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 2144 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2145 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2146 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2147 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2148 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2149 //DAGB0_SDP_REQ_CNTL 2150 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 2151 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 2152 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 2153 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 2154 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 2155 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 2156 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 2157 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 2158 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 2159 #define DAGB0_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN__SHIFT 0xc 2160 #define DAGB0_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE__SHIFT 0xd 2161 #define DAGB0_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE__SHIFT 0xe 2162 #define DAGB0_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN__SHIFT 0x10 2163 #define DAGB0_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE__SHIFT 0x11 2164 #define DAGB0_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE__SHIFT 0x12 2165 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 2166 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 2167 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 2168 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 2169 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 2170 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 2171 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 2172 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 2173 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 2174 //DAGB0_SDP_MISC_AON 2175 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 2176 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 2177 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 2178 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 2179 //DAGB0_SDP_MISC 2180 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 2181 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 2182 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 2183 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 2184 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 2185 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 2186 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 2187 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 2188 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 2189 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 2190 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 2191 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 2192 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 2193 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 2194 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 2195 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 2196 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 2197 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 2198 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 2199 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 2200 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 2201 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 2202 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 2203 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 2204 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 2205 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 2206 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 2207 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 2208 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 2209 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 2210 //DAGB0_SDP_MISC2 2211 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 2212 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 2213 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 2214 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 2215 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 2216 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 2217 //DAGB0_SDP_VCD_RESERVE0 2218 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 2219 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 2220 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 2221 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 2222 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 2223 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2224 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2225 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2226 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2227 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2228 //DAGB0_SDP_VCD_RESERVE1 2229 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 2230 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 2231 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 2232 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2233 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2234 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2235 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2236 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2237 //DAGB0_SDP_ARB_CNTL0 2238 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 2239 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 2240 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 2241 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 2242 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 2243 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 2244 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 2245 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 2246 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 2247 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 2248 //DAGB0_SDP_ARB_CNTL1 2249 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 2250 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 2251 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 2252 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 2253 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 2254 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 2255 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 2256 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 2257 //DAGB0_FATAL_ERROR_CLEAR 2258 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 2259 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 2260 //DAGB0_FATAL_ERROR_STATUS0 2261 #define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 2262 #define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 2263 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 2264 #define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 2265 #define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 2266 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 2267 //DAGB0_FATAL_ERROR_STATUS1 2268 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 2269 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x00001FFFL 2270 //DAGB0_FATAL_ERROR_STATUS2 2271 #define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 2272 #define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 2273 #define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x19 2274 #define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1e 2275 #define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL 2276 #define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x01FF0000L 2277 #define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x3E000000L 2278 #define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x40000000L 2279 //DAGB0_FATAL_ERROR_STATUS3 2280 #define DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x0 2281 #define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 2282 #define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xd 2283 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 2284 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 2285 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 2286 #define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 2287 #define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 2288 #define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 2289 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 2290 #define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x18 2291 #define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x19 2292 #define DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000003FL 2293 #define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 2294 #define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0000E000L 2295 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 2296 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 2297 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 2298 #define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 2299 #define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 2300 #define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 2301 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 2302 #define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x01000000L 2303 #define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x02000000L 2304 //DAGB0_FATAL_ERROR_STATUS4 2305 #define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 2306 #define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 2307 #define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 2308 #define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 2309 #define DAGB0_FATAL_ERROR_STATUS4__SPACE__SHIFT 0x7 2310 #define DAGB0_FATAL_ERROR_STATUS4__IO__SHIFT 0x8 2311 #define DAGB0_FATAL_ERROR_STATUS4__SIZE__SHIFT 0x9 2312 #define DAGB0_FATAL_ERROR_STATUS4__REUSE_HINT__SHIFT 0xa 2313 #define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL 2314 #define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L 2315 #define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L 2316 #define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L 2317 //DAGB0_SDP_CGTT_CLK_CTRL 2318 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2319 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2320 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2321 #define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 2322 #define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 2323 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2324 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2325 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2326 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2327 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 2328 #define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 2329 #define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 2330 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2331 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2332 //DAGB0_SDP_LATENCY_SAMPLING 2333 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 2334 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 2335 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 2336 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 2337 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 2338 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 2339 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 2340 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 2341 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 2342 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 2343 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 2344 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 2345 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 2346 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 2347 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 2348 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 2349 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 2350 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 2351 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 2352 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 2353 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 2354 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 2355 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 2356 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 2357 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 2358 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 2359 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 2360 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 2361 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 2362 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 2363 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 2364 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 2365 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 2366 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 2367 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x00FFFFFFL 2368 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 2369 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 2370 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x00FFFFFFL 2371 //DAGB1_RDCLI0 2372 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 2373 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2374 #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 2375 #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 2376 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 2377 #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 2378 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 2379 #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 2380 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2381 #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 2382 #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 2383 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2384 #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 2385 #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 2386 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2387 #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 2388 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2389 #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 2390 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2391 #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 2392 //DAGB1_RDCLI1 2393 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 2394 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2395 #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 2396 #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 2397 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 2398 #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 2399 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 2400 #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 2401 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2402 #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 2403 #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 2404 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2405 #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 2406 #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 2407 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2408 #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 2409 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2410 #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 2411 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2412 #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 2413 //DAGB1_RDCLI2 2414 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 2415 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2416 #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 2417 #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 2418 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 2419 #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 2420 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 2421 #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 2422 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2423 #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 2424 #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 2425 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2426 #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 2427 #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 2428 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2429 #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 2430 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2431 #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 2432 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2433 #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 2434 //DAGB1_RDCLI3 2435 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 2436 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2437 #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 2438 #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 2439 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 2440 #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 2441 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 2442 #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 2443 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2444 #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 2445 #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 2446 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2447 #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 2448 #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 2449 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2450 #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 2451 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2452 #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 2453 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2454 #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 2455 //DAGB1_RDCLI4 2456 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 2457 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2458 #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 2459 #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 2460 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 2461 #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 2462 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 2463 #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 2464 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2465 #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 2466 #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 2467 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2468 #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 2469 #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 2470 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2471 #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 2472 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2473 #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 2474 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2475 #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 2476 //DAGB1_RDCLI5 2477 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 2478 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2479 #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 2480 #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 2481 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 2482 #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 2483 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 2484 #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 2485 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2486 #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 2487 #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 2488 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2489 #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 2490 #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 2491 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2492 #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 2493 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2494 #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 2495 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2496 #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 2497 //DAGB1_RDCLI6 2498 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 2499 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2500 #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 2501 #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 2502 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 2503 #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 2504 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 2505 #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 2506 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2507 #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 2508 #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 2509 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2510 #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 2511 #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 2512 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2513 #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 2514 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2515 #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 2516 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2517 #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 2518 //DAGB1_RDCLI7 2519 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 2520 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2521 #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 2522 #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 2523 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 2524 #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 2525 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 2526 #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 2527 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2528 #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 2529 #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 2530 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2531 #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 2532 #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 2533 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2534 #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 2535 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2536 #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 2537 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2538 #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 2539 //DAGB1_RDCLI8 2540 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 2541 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2542 #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 2543 #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 2544 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 2545 #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 2546 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 2547 #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 2548 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2549 #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 2550 #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 2551 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2552 #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 2553 #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 2554 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2555 #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 2556 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2557 #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 2558 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2559 #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 2560 //DAGB1_RDCLI9 2561 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 2562 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2563 #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 2564 #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 2565 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 2566 #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 2567 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 2568 #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 2569 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2570 #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 2571 #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 2572 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2573 #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 2574 #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 2575 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2576 #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 2577 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2578 #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 2579 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2580 #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 2581 //DAGB1_RDCLI10 2582 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 2583 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2584 #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 2585 #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 2586 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 2587 #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 2588 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 2589 #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 2590 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2591 #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 2592 #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 2593 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2594 #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 2595 #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 2596 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2597 #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 2598 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2599 #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 2600 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2601 #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 2602 //DAGB1_RDCLI11 2603 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 2604 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2605 #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 2606 #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 2607 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 2608 #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 2609 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 2610 #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 2611 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2612 #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 2613 #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 2614 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2615 #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 2616 #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 2617 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2618 #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 2619 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2620 #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 2621 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2622 #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 2623 //DAGB1_RDCLI12 2624 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 2625 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2626 #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 2627 #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 2628 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 2629 #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 2630 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 2631 #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 2632 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2633 #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 2634 #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 2635 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2636 #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 2637 #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 2638 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2639 #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 2640 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2641 #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 2642 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2643 #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 2644 //DAGB1_RDCLI13 2645 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 2646 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2647 #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 2648 #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 2649 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 2650 #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 2651 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 2652 #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 2653 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2654 #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 2655 #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 2656 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2657 #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 2658 #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 2659 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2660 #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 2661 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2662 #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 2663 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2664 #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 2665 //DAGB1_RDCLI14 2666 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 2667 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2668 #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2669 #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2670 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2671 #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2672 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2673 #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2674 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2675 #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2676 #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2677 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2678 #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2679 #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2680 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2681 #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2682 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2683 #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2684 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2685 #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2686 //DAGB1_RDCLI15 2687 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2688 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2689 #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2690 #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2691 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2692 #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2693 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2694 #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2695 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2696 #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2697 #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2698 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2699 #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2700 #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2701 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2702 #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2703 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2704 #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2705 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2706 #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2707 //DAGB1_RDCLI16 2708 #define DAGB1_RDCLI16__VIRT_CHAN__SHIFT 0x0 2709 #define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 2710 #define DAGB1_RDCLI16__URG_HIGH__SHIFT 0x4 2711 #define DAGB1_RDCLI16__URG_LOW__SHIFT 0x8 2712 #define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 2713 #define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd 2714 #define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 2715 #define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 2716 #define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 2717 #define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a 2718 #define DAGB1_RDCLI16__VIRT_CHAN_MASK 0x00000007L 2719 #define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 2720 #define DAGB1_RDCLI16__URG_HIGH_MASK 0x000000F0L 2721 #define DAGB1_RDCLI16__URG_LOW_MASK 0x00000F00L 2722 #define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 2723 #define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L 2724 #define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 2725 #define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L 2726 #define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 2727 #define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L 2728 //DAGB1_RDCLI17 2729 #define DAGB1_RDCLI17__VIRT_CHAN__SHIFT 0x0 2730 #define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 2731 #define DAGB1_RDCLI17__URG_HIGH__SHIFT 0x4 2732 #define DAGB1_RDCLI17__URG_LOW__SHIFT 0x8 2733 #define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 2734 #define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd 2735 #define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 2736 #define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 2737 #define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 2738 #define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a 2739 #define DAGB1_RDCLI17__VIRT_CHAN_MASK 0x00000007L 2740 #define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 2741 #define DAGB1_RDCLI17__URG_HIGH_MASK 0x000000F0L 2742 #define DAGB1_RDCLI17__URG_LOW_MASK 0x00000F00L 2743 #define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 2744 #define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L 2745 #define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 2746 #define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L 2747 #define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 2748 #define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L 2749 //DAGB1_RDCLI18 2750 #define DAGB1_RDCLI18__VIRT_CHAN__SHIFT 0x0 2751 #define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 2752 #define DAGB1_RDCLI18__URG_HIGH__SHIFT 0x4 2753 #define DAGB1_RDCLI18__URG_LOW__SHIFT 0x8 2754 #define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 2755 #define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd 2756 #define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 2757 #define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 2758 #define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 2759 #define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a 2760 #define DAGB1_RDCLI18__VIRT_CHAN_MASK 0x00000007L 2761 #define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 2762 #define DAGB1_RDCLI18__URG_HIGH_MASK 0x000000F0L 2763 #define DAGB1_RDCLI18__URG_LOW_MASK 0x00000F00L 2764 #define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 2765 #define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L 2766 #define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 2767 #define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L 2768 #define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 2769 #define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L 2770 //DAGB1_RDCLI19 2771 #define DAGB1_RDCLI19__VIRT_CHAN__SHIFT 0x0 2772 #define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 2773 #define DAGB1_RDCLI19__URG_HIGH__SHIFT 0x4 2774 #define DAGB1_RDCLI19__URG_LOW__SHIFT 0x8 2775 #define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 2776 #define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd 2777 #define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 2778 #define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 2779 #define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 2780 #define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a 2781 #define DAGB1_RDCLI19__VIRT_CHAN_MASK 0x00000007L 2782 #define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 2783 #define DAGB1_RDCLI19__URG_HIGH_MASK 0x000000F0L 2784 #define DAGB1_RDCLI19__URG_LOW_MASK 0x00000F00L 2785 #define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 2786 #define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L 2787 #define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 2788 #define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L 2789 #define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 2790 #define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L 2791 //DAGB1_RDCLI20 2792 #define DAGB1_RDCLI20__VIRT_CHAN__SHIFT 0x0 2793 #define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 2794 #define DAGB1_RDCLI20__URG_HIGH__SHIFT 0x4 2795 #define DAGB1_RDCLI20__URG_LOW__SHIFT 0x8 2796 #define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 2797 #define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd 2798 #define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 2799 #define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 2800 #define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 2801 #define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a 2802 #define DAGB1_RDCLI20__VIRT_CHAN_MASK 0x00000007L 2803 #define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 2804 #define DAGB1_RDCLI20__URG_HIGH_MASK 0x000000F0L 2805 #define DAGB1_RDCLI20__URG_LOW_MASK 0x00000F00L 2806 #define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 2807 #define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L 2808 #define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 2809 #define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L 2810 #define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 2811 #define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L 2812 //DAGB1_RDCLI21 2813 #define DAGB1_RDCLI21__VIRT_CHAN__SHIFT 0x0 2814 #define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 2815 #define DAGB1_RDCLI21__URG_HIGH__SHIFT 0x4 2816 #define DAGB1_RDCLI21__URG_LOW__SHIFT 0x8 2817 #define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 2818 #define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd 2819 #define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 2820 #define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 2821 #define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 2822 #define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a 2823 #define DAGB1_RDCLI21__VIRT_CHAN_MASK 0x00000007L 2824 #define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 2825 #define DAGB1_RDCLI21__URG_HIGH_MASK 0x000000F0L 2826 #define DAGB1_RDCLI21__URG_LOW_MASK 0x00000F00L 2827 #define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 2828 #define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L 2829 #define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 2830 #define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L 2831 #define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 2832 #define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L 2833 //DAGB1_RDCLI22 2834 #define DAGB1_RDCLI22__VIRT_CHAN__SHIFT 0x0 2835 #define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 2836 #define DAGB1_RDCLI22__URG_HIGH__SHIFT 0x4 2837 #define DAGB1_RDCLI22__URG_LOW__SHIFT 0x8 2838 #define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 2839 #define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd 2840 #define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 2841 #define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 2842 #define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 2843 #define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a 2844 #define DAGB1_RDCLI22__VIRT_CHAN_MASK 0x00000007L 2845 #define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 2846 #define DAGB1_RDCLI22__URG_HIGH_MASK 0x000000F0L 2847 #define DAGB1_RDCLI22__URG_LOW_MASK 0x00000F00L 2848 #define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 2849 #define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L 2850 #define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 2851 #define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L 2852 #define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 2853 #define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L 2854 //DAGB1_RDCLI23 2855 #define DAGB1_RDCLI23__VIRT_CHAN__SHIFT 0x0 2856 #define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 2857 #define DAGB1_RDCLI23__URG_HIGH__SHIFT 0x4 2858 #define DAGB1_RDCLI23__URG_LOW__SHIFT 0x8 2859 #define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 2860 #define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd 2861 #define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 2862 #define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 2863 #define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 2864 #define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a 2865 #define DAGB1_RDCLI23__VIRT_CHAN_MASK 0x00000007L 2866 #define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 2867 #define DAGB1_RDCLI23__URG_HIGH_MASK 0x000000F0L 2868 #define DAGB1_RDCLI23__URG_LOW_MASK 0x00000F00L 2869 #define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 2870 #define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L 2871 #define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 2872 #define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L 2873 #define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 2874 #define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L 2875 //DAGB1_RD_CNTL 2876 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 2877 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 2878 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 2879 #define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 2880 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 2881 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 2882 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 2883 #define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 2884 //DAGB1_RD_IO_CNTL 2885 #define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2886 #define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2887 #define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2888 #define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2889 #define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2890 #define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2891 #define DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 2892 #define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2893 #define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2894 #define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2895 #define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2896 #define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2897 #define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2898 #define DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2899 //DAGB1_RD_GMI_CNTL 2900 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2901 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2902 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2903 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2904 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2905 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2906 #define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 2907 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2908 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2909 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2910 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2911 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2912 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2913 #define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2914 //DAGB1_RD_ADDR_DAGB 2915 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2916 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x4 2917 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x8 2918 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x9 2919 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xf 2920 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x0000000FL 2921 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x000000F0L 2922 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000100L 2923 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00007E00L 2924 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00008000L 2925 //DAGB1_RD_CGTT_CLK_CTRL 2926 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2927 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2928 #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2929 #define DAGB1_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 2930 #define DAGB1_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 2931 #define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2932 #define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2933 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2934 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2935 #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 2936 #define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2937 #define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2938 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2939 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2940 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2941 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2942 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 2943 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 2944 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2945 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2946 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2947 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2948 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 2949 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2950 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2951 //DAGB1_RD_ADDR_DAGB_MAX_BURST0 2952 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2953 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2954 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2955 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2956 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2957 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2958 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2959 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2960 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2961 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2962 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2963 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2964 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2965 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2966 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2967 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2968 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 2969 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2970 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2971 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2972 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2973 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2974 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2975 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2976 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2977 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2978 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2979 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2980 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2981 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2982 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2983 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2984 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2985 //DAGB1_RD_ADDR_DAGB_MAX_BURST1 2986 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2987 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2988 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2989 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2990 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2991 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2992 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2993 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2994 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2995 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2996 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2997 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2998 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2999 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3000 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3001 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3002 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 3003 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3004 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3005 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3006 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3007 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3008 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3009 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3010 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3011 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3012 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3013 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3014 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3015 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3016 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3017 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3018 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3019 //DAGB1_RD_ADDR_DAGB_MAX_BURST2 3020 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 3021 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 3022 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 3023 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 3024 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 3025 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 3026 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 3027 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 3028 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 3029 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 3030 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 3031 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 3032 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 3033 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 3034 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 3035 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 3036 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 3037 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 3038 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 3039 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 3040 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 3041 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 3042 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 3043 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 3044 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 3045 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 3046 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 3047 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 3048 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 3049 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 3050 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 3051 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 3052 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 3053 //DAGB1_RD_VC0_CNTL 3054 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3055 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3056 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 3057 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3058 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 3059 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3060 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 3061 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3062 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3063 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3064 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3065 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3066 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3067 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3068 //DAGB1_RD_VC1_CNTL 3069 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3070 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3071 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 3072 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3073 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 3074 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3075 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 3076 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3077 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3078 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3079 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3080 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3081 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3082 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3083 //DAGB1_RD_VC2_CNTL 3084 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3085 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3086 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 3087 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3088 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 3089 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3090 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 3091 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3092 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3093 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3094 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3095 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3096 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3097 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3098 //DAGB1_RD_VC3_CNTL 3099 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3100 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3101 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 3102 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3103 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 3104 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3105 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 3106 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3107 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3108 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3109 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3110 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3111 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3112 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3113 //DAGB1_RD_VC4_CNTL 3114 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3115 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3116 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 3117 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3118 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 3119 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3120 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 3121 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3122 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3123 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3124 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3125 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3126 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3127 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3128 //DAGB1_RD_VC5_CNTL 3129 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3130 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3131 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 3132 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3133 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 3134 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3135 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 3136 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3137 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3138 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3139 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3140 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3141 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3142 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3143 //DAGB1_RD_IO_VC_CNTL 3144 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3145 #define DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 3146 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3147 #define DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 3148 #define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3149 #define DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 3150 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3151 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 3152 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3153 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 3154 #define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3155 #define DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3156 //DAGB1_RD_GMI_VC_CNTL 3157 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3158 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 3159 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3160 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 3161 #define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3162 #define DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 3163 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3164 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 3165 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3166 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 3167 #define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3168 #define DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3169 //DAGB1_RD_CNTL_MISC 3170 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3171 #define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 3172 #define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 3173 #define DAGB1_RD_CNTL_MISC__IO_BYPASS_COMPRESSION__SHIFT 0xa 3174 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3175 #define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 3176 #define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 3177 //DAGB1_RD_TLB_CREDIT 3178 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 3179 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 3180 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 3181 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 3182 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 3183 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 3184 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 3185 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 3186 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 3187 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 3188 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 3189 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 3190 //DAGB1_RDCLI_ASK_PENDING 3191 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 3192 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0x00FFFFFFL 3193 //DAGB1_RDCLI_GO_PENDING 3194 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 3195 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0x00FFFFFFL 3196 //DAGB1_RDCLI_GBLSEND_PENDING 3197 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3198 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0x00FFFFFFL 3199 //DAGB1_RDCLI_TLB_PENDING 3200 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 3201 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0x00FFFFFFL 3202 //DAGB1_RDCLI_OARB_PENDING 3203 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 3204 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0x00FFFFFFL 3205 //DAGB1_RDCLI_ASK2ARB_PENDING 3206 #define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 3207 #define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0x00FFFFFFL 3208 //DAGB1_RDCLI_ASK2DF_PENDING 3209 #define DAGB1_RDCLI_ASK2DF_PENDING__NUM__SHIFT 0x0 3210 //DAGB1_RDCLI_OSD_PENDING 3211 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 3212 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 3213 //DAGB1_RDCLI_ASK_OSD_PENDING 3214 #define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 3215 #define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0x00FFFFFFL 3216 //DAGB1_SDP_ERR_STATUS 3217 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 3218 #define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 3219 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 3220 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_METADATA_ERROR__SHIFT 0xa 3221 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xb 3222 #define DAGB1_SDP_ERR_STATUS__WR_DATAPARITY_ERROR__SHIFT 0xc 3223 #define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd 3224 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe 3225 #define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xf 3226 #define DAGB1_SDP_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x10 3227 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 3228 #define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 3229 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 3230 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000800L 3231 #define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L 3232 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L 3233 #define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00008000L 3234 //DAGB1_DAGB_DLY 3235 #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3236 #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3237 #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3238 #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3239 #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3240 #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3241 //DAGB1_CNTL_MISC 3242 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 3243 #define DAGB1_CNTL_MISC__CLI_FATAL_EDGE_MODE__SHIFT 0x6 3244 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 3245 //DAGB1_CNTL_MISC2 3246 #define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 3247 #define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 3248 #define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 3249 #define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 3250 #define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 3251 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 3252 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x6 3253 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x7 3254 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x8 3255 #define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 3256 #define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 3257 #define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 3258 #define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 3259 #define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 3260 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 3261 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000040L 3262 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000080L 3263 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000100L 3264 //DAGB1_FIFO_EMPTY 3265 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3266 #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 3267 //DAGB1_FIFO_FULL 3268 #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3269 #define DAGB1_FIFO_FULL__FULL_MASK 0x0000FFFFL 3270 //DAGB1_RD_CREDITS_FULL 3271 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3272 #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 3273 //DAGB1_PERFCOUNTER_LO 3274 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3275 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3276 //DAGB1_PERFCOUNTER_HI 3277 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3278 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3279 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3280 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3281 //DAGB1_PERFCOUNTER0_CFG 3282 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3283 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3284 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3285 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3286 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3287 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3288 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3289 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3290 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3291 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3292 //DAGB1_PERFCOUNTER1_CFG 3293 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3294 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3295 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3296 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3297 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3298 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3299 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3300 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3301 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3302 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3303 //DAGB1_PERFCOUNTER2_CFG 3304 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3305 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3306 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3307 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3308 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3309 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3310 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3311 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3312 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3313 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3314 //DAGB1_PERFCOUNTER_RSLT_CNTL 3315 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3316 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3317 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3318 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3319 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3320 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3321 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 3322 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3323 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3324 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3325 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3326 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3327 //DAGB1_L1TLB_REG_RW 3328 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 3329 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 3330 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 3331 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 3332 //DAGB1_RESERVE0 3333 #define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 3334 #define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 3335 //DAGB1_RESERVE1 3336 #define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3337 #define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3338 //DAGB1_RESERVE2 3339 #define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3340 #define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3341 //DAGB1_RESERVE3 3342 #define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3343 #define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3344 //DAGB1_SDP_RD_BW_CNTL 3345 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3346 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 3347 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0xb 3348 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xc 3349 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0x12 3350 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3351 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000007FEL 3352 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000800L 3353 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x0003F000L 3354 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x07FC0000L 3355 //DAGB1_SDP_PRIORITY_OVERRIDE 3356 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 3357 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 3358 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 3359 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 3360 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 3361 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 3362 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 3363 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 3364 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 3365 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 3366 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 3367 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 3368 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 3369 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 3370 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 3371 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 3372 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 3373 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 3374 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 3375 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 3376 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 3377 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 3378 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 3379 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 3380 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 3381 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 3382 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 3383 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 3384 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 3385 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 3386 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 3387 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 3388 //DAGB1_SDP_RD_PRIORITY 3389 #define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 3390 #define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 3391 #define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 3392 #define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 3393 #define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 3394 #define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 3395 #define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 3396 #define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 3397 #define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 3398 #define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 3399 #define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 3400 #define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 3401 //DAGB1_SDP_RD_CLI2SDP_VC_MAP 3402 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 3403 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 3404 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 3405 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 3406 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 3407 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 3408 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 3409 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 3410 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 3411 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 3412 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 3413 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 3414 //DAGB1_SDP_ENABLE 3415 #define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 3416 #define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L 3417 //DAGB1_SDP_CREDITS 3418 #define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 3419 #define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 3420 #define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 3421 #define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 3422 #define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 3423 #define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 3424 //DAGB1_SDP_TAG_RESERVE0 3425 #define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 3426 #define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 3427 #define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 3428 #define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 3429 #define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 3430 #define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 3431 #define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 3432 #define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 3433 //DAGB1_SDP_TAG_RESERVE1 3434 #define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 3435 #define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 3436 #define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 3437 #define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 3438 #define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 3439 #define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 3440 #define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 3441 #define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 3442 //DAGB1_SDP_VCC_RESERVE0 3443 #define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 3444 #define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 3445 #define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 3446 #define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 3447 #define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 3448 #define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3449 #define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3450 #define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3451 #define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3452 #define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3453 //DAGB1_SDP_VCC_RESERVE1 3454 #define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 3455 #define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 3456 #define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 3457 #define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3458 #define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3459 #define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3460 #define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3461 #define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3462 //DAGB1_SDP_REQ_CNTL 3463 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 3464 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 3465 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 3466 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 3467 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 3468 #define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 3469 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 3470 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 3471 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 3472 #define DAGB1_SDP_REQ_CNTL__DRAM_LEGACY_WR_64B_ALIGN__SHIFT 0xc 3473 #define DAGB1_SDP_REQ_CNTL__DRAM_LARGE_WR_64B_UPSIZE__SHIFT 0xd 3474 #define DAGB1_SDP_REQ_CNTL__DRAM_RD_64B_ALIGN_UPSIZE__SHIFT 0xe 3475 #define DAGB1_SDP_REQ_CNTL__IO_LEGACY_WR_64B_ALIGN__SHIFT 0x10 3476 #define DAGB1_SDP_REQ_CNTL__IO_LARGE_WR_64B_UPSIZE__SHIFT 0x11 3477 #define DAGB1_SDP_REQ_CNTL__IO_RD_64B_ALIGN_UPSIZE__SHIFT 0x12 3478 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 3479 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 3480 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 3481 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 3482 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 3483 #define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 3484 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 3485 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 3486 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 3487 //DAGB1_SDP_MISC_AON 3488 #define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 3489 #define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 3490 #define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 3491 #define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 3492 //DAGB1_SDP_MISC 3493 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 3494 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 3495 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 3496 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 3497 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 3498 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 3499 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 3500 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 3501 #define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 3502 #define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 3503 #define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 3504 #define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 3505 #define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 3506 #define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 3507 #define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 3508 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 3509 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 3510 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 3511 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 3512 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 3513 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 3514 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 3515 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 3516 #define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 3517 #define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 3518 #define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 3519 #define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 3520 #define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 3521 #define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 3522 #define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 3523 //DAGB1_SDP_MISC2 3524 #define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 3525 #define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 3526 #define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 3527 #define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 3528 #define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 3529 #define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 3530 //DAGB1_SDP_ARB_CNTL0 3531 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 3532 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 3533 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 3534 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 3535 #define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 3536 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 3537 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 3538 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 3539 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 3540 #define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 3541 //DAGB1_SDP_ARB_CNTL1 3542 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 3543 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 3544 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 3545 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 3546 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 3547 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 3548 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 3549 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 3550 //DAGB1_SDP_CGTT_CLK_CTRL 3551 #define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3552 #define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 3553 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 3554 #define DAGB1_SDP_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 3555 #define DAGB1_SDP_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 3556 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 3557 #define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 3558 #define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 3559 #define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 3560 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 3561 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 3562 #define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 3563 //DAGB1_SDP_LATENCY_SAMPLING 3564 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 3565 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 3566 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 3567 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 3568 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 3569 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 3570 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 3571 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 3572 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 3573 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 3574 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 3575 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 3576 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 3577 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 3578 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 3579 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 3580 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 3581 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 3582 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 3583 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 3584 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 3585 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 3586 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 3587 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 3588 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 3589 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 3590 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 3591 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 3592 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 3593 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 3594 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 3595 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 3596 3597 3598 // addressBlock: mmhub_pctldec 3599 //PCTL_CTRL 3600 #define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 3601 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 3602 #define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 3603 #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 3604 #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 3605 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 3606 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 3607 #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 3608 #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 3609 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 3610 #define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b 3611 #define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c 3612 #define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d 3613 #define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e 3614 #define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f 3615 #define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 3616 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 3617 #define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L 3618 #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L 3619 #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L 3620 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 3621 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 3622 #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 3623 #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 3624 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L 3625 #define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L 3626 #define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L 3627 #define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L 3628 #define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L 3629 #define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L 3630 //PCTL_MMHUB_DEEPSLEEP_IB 3631 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 3632 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 3633 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 3634 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 3635 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 3636 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 3637 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 3638 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 3639 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 3640 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 3641 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 3642 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 3643 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 3644 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 3645 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 3646 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 3647 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 3648 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 3649 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3650 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3651 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3652 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3653 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3654 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3655 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3656 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3657 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3658 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3659 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3660 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3661 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3662 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3663 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3664 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3665 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3666 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 3667 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 3668 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 3669 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 3670 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 3671 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 3672 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 3673 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 3674 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 3675 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 3676 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 3677 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 3678 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 3679 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 3680 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 3681 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 3682 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 3683 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 3684 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 3685 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 3686 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 3687 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 3688 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 3689 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 3690 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 3691 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 3692 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 3693 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 3694 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 3695 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 3696 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 3697 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 3698 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 3699 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 3700 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 3701 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 3702 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 3703 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 3704 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 3705 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 3706 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 3707 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 3708 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 3709 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 3710 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 3711 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 3712 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 3713 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 3714 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 3715 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 3716 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 3717 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 3718 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 3719 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 3720 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 3721 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 3722 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 3723 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 3724 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 3725 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 3726 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 3727 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 3728 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 3729 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 3730 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 3731 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 3732 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 3733 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 3734 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 3735 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 3736 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 3737 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 3738 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 3739 //PCTL_PG_IGNORE_DEEPSLEEP 3740 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 3741 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 3742 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 3743 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 3744 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 3745 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 3746 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 3747 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 3748 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 3749 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 3750 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 3751 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 3752 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 3753 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 3754 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 3755 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 3756 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 3757 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 3758 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 3759 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 3760 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 3761 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 3762 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 3763 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 3764 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 3765 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 3766 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 3767 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 3768 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 3769 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 3770 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 3771 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 3772 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 3773 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 3774 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 3775 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 3776 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 3777 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 3778 //PCTL_PG_IGNORE_DEEPSLEEP_IB 3779 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 3780 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 3781 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 3782 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 3783 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 3784 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 3785 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 3786 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 3787 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 3788 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 3789 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 3790 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 3791 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 3792 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 3793 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 3794 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 3795 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 3796 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 3797 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3798 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3799 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3800 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3801 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3802 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3803 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3804 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3805 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3806 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3807 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3808 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3809 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3810 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3811 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3812 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3813 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3814 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 3815 //PCTL_UTCL2_MISC 3816 #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 3817 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 3818 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 3819 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 3820 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 3821 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3822 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3823 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3824 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3825 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3826 #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL 3827 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 3828 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 3829 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 3830 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 3831 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3832 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3833 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3834 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3835 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3836 //PCTL_SLICE0_CFG_DAGB_WRBUSY 3837 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3838 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3839 //PCTL_SLICE0_CFG_DAGB_RDBUSY 3840 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3841 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3842 //PCTL_SLICE0_CFG_DS_ALLOW 3843 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 3844 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 3845 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 3846 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 3847 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 3848 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 3849 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 3850 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 3851 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 3852 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 3853 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 3854 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 3855 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 3856 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 3857 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 3858 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 3859 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 3860 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3861 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3862 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3863 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3864 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3865 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3866 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3867 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3868 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3869 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3870 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3871 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3872 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3873 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3874 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3875 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3876 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3877 //PCTL_SLICE0_CFG_DS_ALLOW_IB 3878 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3879 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3880 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3881 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3882 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3883 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3884 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3885 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3886 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3887 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3888 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3889 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3890 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3891 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3892 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3893 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3894 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3895 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3896 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3897 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3898 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3899 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3900 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3901 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3902 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3903 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3904 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3905 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3906 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3907 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3908 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3909 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3910 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3911 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3912 //PCTL_SLICE0_MISC 3913 #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 3914 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 3915 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 3916 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 3917 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 3918 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 3919 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3920 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3921 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3922 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3923 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3924 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e 3925 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f 3926 #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 3927 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 3928 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 3929 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 3930 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 3931 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 3932 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3933 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3934 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3935 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3936 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3937 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L 3938 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L 3939 //PCTL_SLICE1_CFG_DAGB_WRBUSY 3940 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3941 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3942 //PCTL_SLICE1_CFG_DAGB_RDBUSY 3943 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3944 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3945 //PCTL_SLICE1_CFG_DS_ALLOW 3946 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 3947 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 3948 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 3949 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 3950 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 3951 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 3952 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 3953 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 3954 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 3955 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 3956 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 3957 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 3958 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 3959 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 3960 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 3961 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 3962 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 3963 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3964 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3965 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3966 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3967 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3968 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3969 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3970 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3971 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3972 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3973 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3974 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3975 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3976 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3977 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3978 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3979 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3980 //PCTL_SLICE1_CFG_DS_ALLOW_IB 3981 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3982 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3983 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3984 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3985 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3986 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3987 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3988 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3989 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3990 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3991 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3992 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3993 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3994 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3995 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3996 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3997 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3998 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3999 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 4000 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 4001 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 4002 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 4003 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 4004 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 4005 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 4006 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 4007 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 4008 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 4009 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 4010 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 4011 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 4012 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 4013 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 4014 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 4015 //PCTL_SLICE1_MISC 4016 #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 4017 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4018 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4019 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4020 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4021 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4022 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4023 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4024 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4025 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4026 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4027 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e 4028 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f 4029 #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL 4030 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4031 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4032 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4033 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4034 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4035 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4036 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4037 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4038 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4039 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4040 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L 4041 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L 4042 //PCTL_RENG_CTRL 4043 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 4044 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4045 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 4046 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4047 //PCTL_UTCL2_RENG_EXECUTE 4048 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4049 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4050 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4051 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 4052 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4053 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4054 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 4055 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 4056 //PCTL_UTCL2_RENG_RAM_INDEX 4057 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4058 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 4059 //PCTL_UTCL2_RENG_RAM_DATA 4060 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4061 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4062 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 4063 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4064 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4065 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4066 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4067 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 4068 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4069 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4070 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4071 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4072 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 4073 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4074 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4075 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4076 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4077 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 4078 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4079 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4080 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4081 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4082 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 4083 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4084 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4085 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4086 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4087 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 4088 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4089 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4090 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4091 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4092 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 4093 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4094 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4095 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4096 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4097 //PCTL_SLICE0_RENG_EXECUTE 4098 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4099 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4100 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4101 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4102 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4103 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4104 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4105 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4106 //PCTL_SLICE0_RENG_RAM_INDEX 4107 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4108 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4109 //PCTL_SLICE0_RENG_RAM_DATA 4110 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4111 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4112 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 4113 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4114 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4115 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4116 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4117 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 4118 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4119 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4120 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4121 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4122 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 4123 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4124 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4125 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4126 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4127 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 4128 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4129 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4130 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4131 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4132 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 4133 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4134 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4135 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4136 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4137 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 4138 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4139 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4140 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4141 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4142 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 4143 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4144 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4145 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4146 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4147 //PCTL_SLICE1_RENG_EXECUTE 4148 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4149 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4150 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4151 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4152 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4153 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4154 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4155 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4156 //PCTL_SLICE1_RENG_RAM_INDEX 4157 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4158 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4159 //PCTL_SLICE1_RENG_RAM_DATA 4160 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4161 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4162 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 4163 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4164 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4165 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4166 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4167 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 4168 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4169 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4170 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4171 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4172 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 4173 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4174 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4175 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4176 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4177 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 4178 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4179 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4180 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4181 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4182 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 4183 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4184 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4185 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4186 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4187 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 4188 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4189 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4190 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4191 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4192 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 4193 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4194 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4195 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4196 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4197 //PCTL_STATUS 4198 #define PCTL_STATUS__MMHUB_INTERLOCK_AUTO_ACK__SHIFT 0x0 4199 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 4200 #define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 4201 #define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 4202 #define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 4203 #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 4204 #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 4205 #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf 4206 #define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 4207 #define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 4208 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 4209 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 4210 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 4211 #define PCTL_STATUS__SLICE2_RENG_RAM_STALE__SHIFT 0x15 4212 #define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x16 4213 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L 4214 #define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L 4215 #define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L 4216 #define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L 4217 #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L 4218 #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L 4219 #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L 4220 #define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L 4221 #define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L 4222 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L 4223 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L 4224 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L 4225 #define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00400000L 4226 //PCTL_PERFCOUNTER_LO 4227 #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4228 #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4229 //PCTL_PERFCOUNTER_HI 4230 #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4231 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4232 #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4233 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4234 //PCTL_PERFCOUNTER0_CFG 4235 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4236 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4237 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4238 #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4239 #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4240 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4241 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4242 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4243 #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4244 #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4245 //PCTL_PERFCOUNTER1_CFG 4246 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4247 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4248 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4249 #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4250 #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4251 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4252 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4253 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4254 #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4255 #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4256 //PCTL_PERFCOUNTER_RSLT_CNTL 4257 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4258 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4259 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4260 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4261 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4262 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4263 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4264 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4265 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4266 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4267 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4268 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4269 //PCTL_RESERVED_0 4270 #define PCTL_RESERVED_0__WORD__SHIFT 0x0 4271 #define PCTL_RESERVED_0__BYTE__SHIFT 0x10 4272 #define PCTL_RESERVED_0__BIT7__SHIFT 0x18 4273 #define PCTL_RESERVED_0__BIT6__SHIFT 0x19 4274 #define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 4275 #define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 4276 #define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 4277 #define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 4278 #define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 4279 #define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 4280 #define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 4281 #define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 4282 #define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 4283 #define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 4284 #define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 4285 #define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 4286 #define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 4287 #define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 4288 #define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 4289 #define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 4290 //PCTL_RESERVED_1 4291 #define PCTL_RESERVED_1__WORD__SHIFT 0x0 4292 #define PCTL_RESERVED_1__BYTE__SHIFT 0x10 4293 #define PCTL_RESERVED_1__BIT7__SHIFT 0x18 4294 #define PCTL_RESERVED_1__BIT6__SHIFT 0x19 4295 #define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 4296 #define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 4297 #define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 4298 #define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 4299 #define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 4300 #define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 4301 #define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 4302 #define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 4303 #define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 4304 #define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 4305 #define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 4306 #define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 4307 #define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 4308 #define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 4309 #define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 4310 #define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 4311 //PCTL_RESERVED_2 4312 #define PCTL_RESERVED_2__WORD__SHIFT 0x0 4313 #define PCTL_RESERVED_2__BYTE__SHIFT 0x10 4314 #define PCTL_RESERVED_2__BIT7__SHIFT 0x18 4315 #define PCTL_RESERVED_2__BIT6__SHIFT 0x19 4316 #define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 4317 #define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 4318 #define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 4319 #define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 4320 #define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 4321 #define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 4322 #define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 4323 #define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 4324 #define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 4325 #define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 4326 #define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 4327 #define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 4328 #define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 4329 #define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 4330 #define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 4331 #define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 4332 //PCTL_RESERVED_3 4333 #define PCTL_RESERVED_3__WORD__SHIFT 0x0 4334 #define PCTL_RESERVED_3__BYTE__SHIFT 0x10 4335 #define PCTL_RESERVED_3__BIT7__SHIFT 0x18 4336 #define PCTL_RESERVED_3__BIT6__SHIFT 0x19 4337 #define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 4338 #define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 4339 #define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 4340 #define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 4341 #define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 4342 #define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 4343 #define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 4344 #define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 4345 #define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 4346 #define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 4347 #define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 4348 #define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 4349 #define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 4350 #define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 4351 #define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 4352 #define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 4353 4354 4355 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 4356 //MMMC_VM_NB_MMIOBASE 4357 #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 4358 #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 4359 //MMMC_VM_NB_MMIOLIMIT 4360 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 4361 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 4362 //MMMC_VM_NB_PCI_CTRL 4363 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 4364 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 4365 //MMMC_VM_NB_PCI_ARB 4366 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 4367 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 4368 //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 4369 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 4370 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 4371 //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 4372 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 4373 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 4374 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 4375 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 4376 //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 4377 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 4378 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x0000FFFFL 4379 //MMMC_VM_FB_OFFSET 4380 #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 4381 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 4382 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 4383 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 4384 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 4385 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 4386 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 4387 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 4388 //MMMC_VM_STEERING 4389 #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 4390 #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 4391 //MMMC_SHARED_VIRT_RESET_REQ 4392 #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 4393 #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x18 4394 #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x00FFFFFFL 4395 #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x01000000L 4396 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 4397 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 4398 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL 4399 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 4400 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 4401 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL 4402 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_START 4403 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 4404 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL 4405 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_END 4406 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 4407 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL 4408 //MMMC_VM_APT_CNTL 4409 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 4410 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 4411 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 4412 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 4413 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 4414 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 4415 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 4416 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 4417 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 4418 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L 4419 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L 4420 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L 4421 //MMMC_VM_LOCAL_FB_ADDRESS_START 4422 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 4423 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL 4424 //MMMC_VM_LOCAL_FB_ADDRESS_END 4425 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 4426 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL 4427 //MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 4428 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 4429 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 4430 //MMUTCL2_CGTT_CLK_CTRL 4431 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4432 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4433 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4434 #define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 4435 #define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 4436 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4437 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4438 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4439 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4440 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 4441 #define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 4442 #define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 4443 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4444 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4445 //MMMC_SHARED_ACTIVE_FCN_ID 4446 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 4447 #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 4448 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 4449 #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 4450 //MMUTCL2_CGTT_BUSY_CTRL 4451 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 4452 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 4453 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 4454 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 4455 //MMUTCL2_HARVEST_BYPASS_GROUPS 4456 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 4457 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 4458 //MMUTCL2_GROUP_RET_FAULT_STATUS 4459 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 4460 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL 4461 4462 4463 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4464 //MMVM_L2_CNTL 4465 #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4466 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4467 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4468 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4469 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4470 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4471 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4472 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4473 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4474 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4475 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4476 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4477 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4478 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4479 #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4480 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4481 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4482 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4483 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4484 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4485 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4486 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4487 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4488 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4489 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4490 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4491 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4492 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4493 //MMVM_L2_CNTL2 4494 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4495 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4496 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4497 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4498 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4499 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4500 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4501 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4502 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4503 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4504 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4505 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4506 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4507 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4508 //MMVM_L2_CNTL3 4509 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4510 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4511 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4512 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4513 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4514 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4515 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4516 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4517 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4518 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4519 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4520 #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4521 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4522 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4523 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4524 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4525 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4526 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4527 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4528 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4529 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4530 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4531 //MMVM_L2_STATUS 4532 #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4533 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4534 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4535 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4536 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4537 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 4538 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 4539 #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 4540 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 4541 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 4542 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 4543 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 4544 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 4545 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 4546 //MMVM_DUMMY_PAGE_FAULT_CNTL 4547 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 4548 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 4549 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 4550 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 4551 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 4552 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 4553 //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 4554 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 4555 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4556 //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 4557 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 4558 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 4559 //MMVM_INVALIDATE_CNTL 4560 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 4561 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 4562 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 4563 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 4564 //MMVM_L2_PROTECTION_FAULT_CNTL 4565 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4566 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 4567 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 4568 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 4569 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4570 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 4571 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 4572 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4573 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 4574 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 4575 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4576 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 4577 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4578 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 4579 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 4580 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 4581 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 4582 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4583 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 4584 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 4585 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 4586 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4587 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 4588 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 4589 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4590 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 4591 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 4592 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4593 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 4594 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4595 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 4596 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 4597 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 4598 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 4599 //MMVM_L2_PROTECTION_FAULT_CNTL2 4600 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 4601 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 4602 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 4603 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 4604 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 4605 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 4606 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 4607 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 4608 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 4609 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 4610 //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 4611 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4612 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4613 //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 4614 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4615 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4616 //MMVM_L2_PROTECTION_FAULT_STATUS_LO32 4617 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS__SHIFT 0x0 4618 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR__SHIFT 0x1 4619 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS__SHIFT 0x4 4620 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR__SHIFT 0x8 4621 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID__SHIFT 0x9 4622 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW__SHIFT 0x12 4623 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC__SHIFT 0x13 4624 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID__SHIFT 0x14 4625 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF__SHIFT 0x18 4626 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID__SHIFT 0x19 4627 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PRT__SHIFT 0x1e 4628 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__UCE__SHIFT 0x1f 4629 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS_MASK 0x00000001L 4630 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR_MASK 0x0000000EL 4631 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS_MASK 0x000000F0L 4632 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR_MASK 0x00000100L 4633 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID_MASK 0x0003FE00L 4634 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW_MASK 0x00040000L 4635 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC_MASK 0x00080000L 4636 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID_MASK 0x00F00000L 4637 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF_MASK 0x01000000L 4638 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID_MASK 0x3E000000L 4639 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PRT_MASK 0x40000000L 4640 #define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__UCE_MASK 0x80000000L 4641 //MMVM_L2_PROTECTION_FAULT_STATUS_HI32 4642 #define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED__SHIFT 0x0 4643 #define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED_MASK 0x00000001L 4644 //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 4645 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4646 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4647 //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 4648 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4649 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4650 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 4651 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 4652 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4653 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 4654 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 4655 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4656 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 4657 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4658 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4659 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 4660 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4661 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4662 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 4663 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4664 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4665 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 4666 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4667 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4668 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 4669 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 4670 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 4671 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 4672 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 4673 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 4674 //MMVM_L2_CNTL4 4675 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4676 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4677 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 4678 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 4679 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 4680 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 4681 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 4682 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 4683 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f 4684 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4685 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4686 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 4687 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 4688 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 4689 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 4690 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 4691 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 4692 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L 4693 //MMVM_L2_MM_GROUP_RT_CLASSES 4694 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 4695 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 4696 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 4697 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 4698 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 4699 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 4700 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 4701 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 4702 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 4703 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 4704 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 4705 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 4706 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 4707 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 4708 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 4709 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 4710 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 4711 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 4712 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 4713 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 4714 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 4715 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 4716 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 4717 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 4718 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 4719 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 4720 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 4721 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 4722 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 4723 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 4724 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 4725 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 4726 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 4727 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 4728 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 4729 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 4730 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 4731 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 4732 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 4733 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 4734 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 4735 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 4736 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 4737 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 4738 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 4739 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 4740 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 4741 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 4742 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 4743 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 4744 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 4745 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 4746 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 4747 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 4748 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 4749 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 4750 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 4751 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 4752 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 4753 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 4754 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 4755 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 4756 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 4757 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 4758 //MMVM_L2_BANK_SELECT_RESERVED_CID 4759 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4760 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4761 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 4762 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4763 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4764 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4765 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4766 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4767 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 4768 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4769 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4770 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4771 //MMVM_L2_BANK_SELECT_RESERVED_CID2 4772 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4773 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4774 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 4775 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4776 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4777 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4778 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4779 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4780 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 4781 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4782 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4783 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4784 //MMVM_L2_CACHE_PARITY_CNTL 4785 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 4786 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 4787 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 4788 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 4789 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 4790 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 4791 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 4792 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 4793 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 4794 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 4795 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 4796 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 4797 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 4798 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 4799 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 4800 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 4801 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 4802 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 4803 //MMVM_L2_CGTT_CLK_CTRL 4804 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4805 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4806 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4807 #define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 4808 #define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 4809 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4810 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4811 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4812 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4813 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 4814 #define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 4815 #define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 4816 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4817 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4818 //MMVM_L2_CNTL5 4819 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 4820 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 4821 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe 4822 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf 4823 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 4824 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 4825 #define MMVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF__SHIFT 0x12 4826 #define MMVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ__SHIFT 0x13 4827 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 4828 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 4829 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L 4830 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L 4831 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L 4832 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L 4833 //MMVM_L2_GCR_CNTL 4834 #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 4835 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 4836 #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 4837 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 4838 //MMVM_L2_CGTT_BUSY_CTRL 4839 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 4840 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 4841 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 4842 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 4843 //MMVM_L2_PTE_CACHE_DUMP_CNTL 4844 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 4845 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 4846 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 4847 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 4848 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 4849 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 4850 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 4851 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 4852 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 4853 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 4854 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 4855 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 4856 //MMVM_L2_PTE_CACHE_DUMP_READ 4857 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 4858 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 4859 //MMVM_L2_BANK_SELECT_MASKS 4860 #define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 4861 #define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 4862 #define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 4863 #define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc 4864 #define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL 4865 #define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L 4866 #define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L 4867 #define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L 4868 //MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 4869 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 4870 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa 4871 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL 4872 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L 4873 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 4874 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 4875 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa 4876 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL 4877 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L 4878 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 4879 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 4880 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa 4881 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL 4882 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L 4883 //MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 4884 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 4885 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa 4886 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL 4887 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L 4888 //MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 4889 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 4890 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa 4891 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 4892 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L 4893 4894 4895 // addressBlock: mmhub_mmutcl2_mmvml2prdec 4896 //MMMC_VM_L2_PERFCOUNTER_LO 4897 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4898 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4899 //MMMC_VM_L2_PERFCOUNTER_HI 4900 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4901 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4902 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4903 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4904 //MMUTCL2_PERFCOUNTER_LO 4905 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4906 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4907 //MMUTCL2_PERFCOUNTER_HI 4908 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4909 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4910 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4911 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4912 4913 4914 // addressBlock: mmhub_mmutcl2_mmvml2pldec 4915 //MMMC_VM_L2_PERFCOUNTER0_CFG 4916 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4917 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4918 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4919 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4920 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4921 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4922 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4923 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4924 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4925 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4926 //MMMC_VM_L2_PERFCOUNTER1_CFG 4927 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4928 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4929 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4930 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4931 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4932 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4933 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4934 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4935 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4936 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4937 //MMMC_VM_L2_PERFCOUNTER2_CFG 4938 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4939 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4940 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4941 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4942 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4943 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4944 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4945 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4946 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4947 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4948 //MMMC_VM_L2_PERFCOUNTER3_CFG 4949 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4950 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4951 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4952 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4953 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4954 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4955 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4956 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4957 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4958 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4959 //MMMC_VM_L2_PERFCOUNTER4_CFG 4960 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 4961 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 4962 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 4963 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 4964 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 4965 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 4966 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 4967 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 4968 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 4969 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 4970 //MMMC_VM_L2_PERFCOUNTER5_CFG 4971 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 4972 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 4973 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 4974 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 4975 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 4976 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 4977 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 4978 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 4979 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 4980 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 4981 //MMMC_VM_L2_PERFCOUNTER6_CFG 4982 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 4983 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 4984 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 4985 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 4986 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 4987 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 4988 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 4989 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 4990 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 4991 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 4992 //MMMC_VM_L2_PERFCOUNTER7_CFG 4993 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 4994 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 4995 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 4996 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 4997 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 4998 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 4999 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 5000 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 5001 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 5002 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 5003 //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 5004 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5005 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5006 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5007 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5008 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5009 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5010 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5011 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5012 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5013 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5014 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5015 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5016 //MMUTCL2_PERFCOUNTER0_CFG 5017 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5018 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5019 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5020 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5021 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5022 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5023 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5024 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5025 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5026 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5027 //MMUTCL2_PERFCOUNTER1_CFG 5028 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5029 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5030 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5031 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5032 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5033 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5034 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5035 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5036 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5037 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5038 //MMUTCL2_PERFCOUNTER2_CFG 5039 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5040 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5041 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5042 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5043 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5044 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 5045 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 5046 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 5047 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 5048 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 5049 //MMUTCL2_PERFCOUNTER3_CFG 5050 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5051 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5052 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5053 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5054 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5055 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 5056 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 5057 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 5058 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 5059 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 5060 //MMUTCL2_PERFCOUNTER_RSLT_CNTL 5061 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5062 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5063 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5064 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5065 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5066 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5067 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5068 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5069 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5070 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5071 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5072 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5073 5074 5075 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 5076 //MMMC_VM_FB_LOCATION_BASE 5077 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 5078 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 5079 //MMMC_VM_FB_LOCATION_TOP 5080 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 5081 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 5082 //MMMC_VM_AGP_TOP 5083 #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 5084 #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 5085 //MMMC_VM_AGP_BOT 5086 #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 5087 #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 5088 //MMMC_VM_AGP_BASE 5089 #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 5090 #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 5091 //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 5092 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 5093 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 5094 //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 5095 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 5096 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 5097 //MMMC_VM_MX_L1_TLB_CNTL 5098 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 5099 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 5100 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 5101 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 5102 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 5103 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 5104 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 5105 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 5106 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 5107 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 5108 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 5109 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 5110 5111 5112 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 5113 //MMVM_CONTEXT0_CNTL 5114 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5115 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5116 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5117 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5118 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5119 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5120 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5121 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5122 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5123 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5124 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5125 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5126 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5127 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5128 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5129 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5130 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5131 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5132 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5133 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5134 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5135 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5136 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5137 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5138 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5139 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5140 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5141 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5142 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5143 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5144 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5145 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5146 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5147 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5148 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5149 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5150 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5151 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5152 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5153 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5154 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5155 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5156 //MMVM_CONTEXT1_CNTL 5157 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5158 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5159 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5160 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5161 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5162 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5163 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5164 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5165 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5166 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5167 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5168 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5169 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5170 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5171 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5172 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5173 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5174 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5175 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5176 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5177 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5178 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5179 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5180 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5181 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5182 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5183 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5184 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5185 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5186 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5187 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5188 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5189 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5190 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5191 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5192 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5193 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5194 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5195 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5196 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5197 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5198 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5199 //MMVM_CONTEXT2_CNTL 5200 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5201 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5202 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5203 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5204 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5205 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5206 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5207 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5208 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5209 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5210 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5211 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5212 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5213 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5214 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5215 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5216 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5217 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5218 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5219 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5220 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5221 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5222 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5223 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5224 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5225 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5226 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5227 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5228 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5229 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5230 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5231 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5232 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5233 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5234 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5235 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5236 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5237 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5238 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5239 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5240 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5241 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5242 //MMVM_CONTEXT3_CNTL 5243 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5244 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5245 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5246 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5247 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5248 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5249 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5250 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5251 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5252 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5253 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5254 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5255 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5256 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5257 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5258 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5259 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5260 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5261 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5262 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5263 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5264 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5265 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5266 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5267 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5268 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5269 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5270 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5271 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5272 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5273 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5274 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5275 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5276 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5277 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5278 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5279 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5280 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5281 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5282 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5283 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5284 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5285 //MMVM_CONTEXT4_CNTL 5286 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5287 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5288 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5289 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5290 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5291 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5292 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5293 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5294 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5295 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5296 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5297 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5298 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5299 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5300 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5301 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5302 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5303 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5304 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5305 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5306 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5307 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5308 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5309 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5310 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5311 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5312 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5313 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5314 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5315 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5316 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5317 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5318 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5319 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5320 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5321 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5322 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5323 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5324 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5325 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5326 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5327 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5328 //MMVM_CONTEXT5_CNTL 5329 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5330 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5331 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5332 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5333 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5334 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5335 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5336 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5337 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5338 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5339 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5340 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5341 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5342 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5343 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5344 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5345 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5346 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5347 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5348 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5349 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5350 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5351 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5352 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5353 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5354 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5355 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5356 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5357 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5358 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5359 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5360 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5361 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5362 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5363 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5364 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5365 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5366 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5367 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5368 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5369 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5370 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5371 //MMVM_CONTEXT6_CNTL 5372 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5373 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5374 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5375 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5376 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5377 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5378 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5379 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5380 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5381 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5382 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5383 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5384 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5385 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5386 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5387 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5388 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5389 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5390 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5391 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5392 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5393 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5394 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5395 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5396 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5397 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5398 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5399 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5400 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5401 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5402 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5403 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5404 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5405 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5406 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5407 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5408 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5409 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5410 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5411 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5412 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5413 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5414 //MMVM_CONTEXT7_CNTL 5415 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5416 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5417 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5418 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5419 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5420 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5421 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5422 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5423 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5424 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5425 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5426 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5427 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5428 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5429 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5430 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5431 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5432 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5433 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5434 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5435 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5436 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5437 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5438 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5439 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5440 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5441 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5442 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5443 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5444 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5445 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5446 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5447 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5448 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5449 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5450 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5451 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5452 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5453 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5454 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5455 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5456 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5457 //MMVM_CONTEXT8_CNTL 5458 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5459 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5460 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5461 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5462 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5463 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5464 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5465 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5466 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5467 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5468 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5469 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5470 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5471 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5472 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5473 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5474 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5475 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5476 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5477 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5478 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5479 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5480 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5481 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5482 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5483 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5484 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5485 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5486 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5487 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5488 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5489 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5490 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5491 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5492 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5493 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5494 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5495 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5496 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5497 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5498 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5499 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5500 //MMVM_CONTEXT9_CNTL 5501 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5502 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5503 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5504 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5505 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5506 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5507 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5508 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5509 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5510 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5511 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5512 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5513 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5514 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5515 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5516 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5517 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5518 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5519 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5520 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5521 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5522 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5523 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5524 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5525 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5526 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5527 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5528 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5529 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5530 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5531 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5532 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5533 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5534 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5535 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5536 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5537 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5538 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5539 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5540 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5541 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5542 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5543 //MMVM_CONTEXT10_CNTL 5544 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5545 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5546 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5547 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5548 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5549 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5550 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5551 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5552 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5553 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5554 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5555 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5556 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5557 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5558 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5559 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5560 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5561 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5562 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5563 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5564 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5565 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5566 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5567 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5568 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5569 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5570 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5571 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5572 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5573 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5574 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5575 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5576 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5577 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5578 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5579 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5580 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5581 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5582 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5583 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5584 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5585 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5586 //MMVM_CONTEXT11_CNTL 5587 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5588 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5589 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5590 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5591 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5592 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5593 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5594 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5595 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5596 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5597 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5598 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5599 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5600 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5601 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5602 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5603 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5604 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5605 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5606 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5607 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5608 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5609 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5610 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5611 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5612 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5613 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5614 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5615 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5616 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5617 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5618 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5619 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5620 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5621 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5622 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5623 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5624 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5625 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5626 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5627 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5628 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5629 //MMVM_CONTEXT12_CNTL 5630 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5631 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5632 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5633 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5634 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5635 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5636 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5637 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5638 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5639 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5640 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5641 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5642 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5643 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5644 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5645 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5646 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5647 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5648 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5649 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5650 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5651 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5652 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5653 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5654 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5655 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5656 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5657 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5658 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5659 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5660 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5661 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5662 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5663 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5664 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5665 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5666 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5667 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5668 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5669 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5670 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5671 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5672 //MMVM_CONTEXT13_CNTL 5673 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5674 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5675 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5676 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5677 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5678 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5679 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5680 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5681 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5682 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5683 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5684 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5685 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5686 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5687 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5688 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5689 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5690 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5691 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5692 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5693 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5694 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5695 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5696 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5697 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5698 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5699 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5700 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5701 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5702 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5703 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5704 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5705 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5706 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5707 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5708 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5709 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5710 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5711 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5712 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5713 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5714 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5715 //MMVM_CONTEXT14_CNTL 5716 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5717 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5718 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5719 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5720 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5721 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5722 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5723 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5724 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5725 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5726 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5727 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5728 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5729 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5730 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5731 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5732 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5733 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5734 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5735 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5736 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5737 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5738 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5739 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5740 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5741 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5742 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5743 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5744 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5745 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5746 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5747 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5748 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5749 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5750 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5751 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5752 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5753 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5754 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5755 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5756 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5757 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5758 //MMVM_CONTEXT15_CNTL 5759 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5760 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5761 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 5762 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 5763 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 5764 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa 5765 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5766 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 5767 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 5768 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe 5769 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf 5770 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 5771 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 5772 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 5773 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 5774 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 5775 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 5776 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 5777 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 5778 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 5779 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 5780 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5781 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5782 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L 5783 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L 5784 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L 5785 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L 5786 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5787 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 5788 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 5789 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L 5790 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L 5791 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L 5792 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L 5793 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 5794 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 5795 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L 5796 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L 5797 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L 5798 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L 5799 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L 5800 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L 5801 //MMVM_CONTEXTS_DISABLE 5802 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5803 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5804 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5805 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5806 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5807 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5808 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5809 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5810 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5811 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5812 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5813 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5814 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5815 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5816 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5817 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5818 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5819 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5820 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5821 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5822 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5823 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5824 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5825 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5826 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5827 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5828 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5829 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5830 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5831 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5832 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5833 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5834 //MMVM_INVALIDATE_ENG0_SEM 5835 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5836 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5837 //MMVM_INVALIDATE_ENG1_SEM 5838 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5839 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5840 //MMVM_INVALIDATE_ENG2_SEM 5841 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5842 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5843 //MMVM_INVALIDATE_ENG3_SEM 5844 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5845 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5846 //MMVM_INVALIDATE_ENG4_SEM 5847 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5848 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5849 //MMVM_INVALIDATE_ENG5_SEM 5850 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5851 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5852 //MMVM_INVALIDATE_ENG6_SEM 5853 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5854 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5855 //MMVM_INVALIDATE_ENG7_SEM 5856 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5857 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5858 //MMVM_INVALIDATE_ENG8_SEM 5859 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5860 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5861 //MMVM_INVALIDATE_ENG9_SEM 5862 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5863 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5864 //MMVM_INVALIDATE_ENG10_SEM 5865 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5866 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5867 //MMVM_INVALIDATE_ENG11_SEM 5868 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5869 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5870 //MMVM_INVALIDATE_ENG12_SEM 5871 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5872 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 5873 //MMVM_INVALIDATE_ENG13_SEM 5874 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 5875 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 5876 //MMVM_INVALIDATE_ENG14_SEM 5877 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 5878 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 5879 //MMVM_INVALIDATE_ENG15_SEM 5880 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 5881 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 5882 //MMVM_INVALIDATE_ENG16_SEM 5883 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 5884 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 5885 //MMVM_INVALIDATE_ENG17_SEM 5886 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 5887 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 5888 //MMVM_INVALIDATE_ENG0_REQ 5889 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5890 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 5891 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5892 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5893 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5894 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5895 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5896 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5897 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 5898 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5899 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5900 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 5901 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5902 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5903 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5904 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5905 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5906 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5907 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 5908 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5909 //MMVM_INVALIDATE_ENG1_REQ 5910 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5911 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 5912 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5913 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5914 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5915 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5916 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5917 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5918 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 5919 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5920 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5921 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 5922 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5923 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5924 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5925 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5926 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5927 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5928 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 5929 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5930 //MMVM_INVALIDATE_ENG2_REQ 5931 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5932 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 5933 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5934 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5935 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5936 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5937 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5938 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5939 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 5940 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5941 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5942 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 5943 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5944 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5945 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5946 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5947 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5948 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5949 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 5950 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5951 //MMVM_INVALIDATE_ENG3_REQ 5952 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5953 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 5954 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5955 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5956 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5957 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5958 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5959 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5960 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 5961 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5962 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5963 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 5964 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5965 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5966 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5967 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5968 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5969 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5970 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 5971 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5972 //MMVM_INVALIDATE_ENG4_REQ 5973 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5974 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 5975 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5976 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5977 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5978 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5979 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5980 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5981 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 5982 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5983 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5984 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 5985 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5986 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5987 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5988 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5989 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5990 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5991 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 5992 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5993 //MMVM_INVALIDATE_ENG5_REQ 5994 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5995 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 5996 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5997 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5998 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5999 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6000 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6001 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6002 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 6003 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6004 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6005 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 6006 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6007 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6008 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6009 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6010 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6011 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6012 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 6013 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6014 //MMVM_INVALIDATE_ENG6_REQ 6015 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6016 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 6017 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6018 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6019 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6020 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6021 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6022 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6023 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 6024 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6025 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6026 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 6027 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6028 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6029 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6030 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6031 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6032 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6033 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 6034 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6035 //MMVM_INVALIDATE_ENG7_REQ 6036 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6037 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 6038 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6039 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6040 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6041 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6042 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6043 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6044 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 6045 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6046 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6047 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 6048 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6049 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6050 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6051 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6052 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6053 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6054 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 6055 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6056 //MMVM_INVALIDATE_ENG8_REQ 6057 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6058 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 6059 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6060 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6061 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6062 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6063 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6064 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6065 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 6066 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6067 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6068 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 6069 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6070 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6071 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6072 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6073 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6074 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6075 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 6076 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6077 //MMVM_INVALIDATE_ENG9_REQ 6078 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6079 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 6080 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6081 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6082 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6083 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6084 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6085 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6086 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 6087 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6088 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6089 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6090 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6091 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6092 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6093 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6094 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6095 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6096 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6097 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6098 //MMVM_INVALIDATE_ENG10_REQ 6099 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6100 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6101 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6102 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6103 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6104 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6105 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6106 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6107 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6108 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6109 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6110 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6111 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6112 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6113 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6114 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6115 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6116 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6117 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6118 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6119 //MMVM_INVALIDATE_ENG11_REQ 6120 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6121 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6122 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6123 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6124 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6125 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6126 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6127 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6128 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6129 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6130 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6131 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6132 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6133 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6134 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6135 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6136 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6137 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6138 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6139 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6140 //MMVM_INVALIDATE_ENG12_REQ 6141 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6142 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6143 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6144 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6145 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6146 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6147 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6148 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6149 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6150 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6151 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6152 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6153 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6154 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6155 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6156 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6157 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6158 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6159 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6160 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6161 //MMVM_INVALIDATE_ENG13_REQ 6162 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6163 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6164 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6165 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6166 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6167 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6168 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6169 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6170 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6171 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6172 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6173 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6174 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6175 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6176 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6177 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6178 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6179 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6180 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6181 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6182 //MMVM_INVALIDATE_ENG14_REQ 6183 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6184 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6185 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6186 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6187 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6188 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6189 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6190 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6191 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6192 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6193 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6194 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6195 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6196 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6197 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6198 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6199 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6200 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6201 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6202 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6203 //MMVM_INVALIDATE_ENG15_REQ 6204 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6205 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6206 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6207 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6208 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6209 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6210 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6211 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6212 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6213 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6214 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6215 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6216 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6217 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6218 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6219 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6220 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6221 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6222 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6223 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6224 //MMVM_INVALIDATE_ENG16_REQ 6225 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6226 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6227 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6228 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6229 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6230 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6231 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6232 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6233 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6234 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6235 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6236 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6237 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6238 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6239 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6240 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6241 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6242 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6243 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6244 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6245 //MMVM_INVALIDATE_ENG17_REQ 6246 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6247 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6248 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6249 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6250 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6251 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6252 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6253 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6254 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6255 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6256 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6257 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6258 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6259 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6260 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6261 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6262 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6263 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6264 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6265 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6266 //MMVM_INVALIDATE_ENG0_ACK 6267 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6268 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6269 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6270 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6271 //MMVM_INVALIDATE_ENG1_ACK 6272 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6273 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6274 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6275 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6276 //MMVM_INVALIDATE_ENG2_ACK 6277 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6278 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6279 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6280 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6281 //MMVM_INVALIDATE_ENG3_ACK 6282 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6283 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6284 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6285 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6286 //MMVM_INVALIDATE_ENG4_ACK 6287 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6288 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6289 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6290 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6291 //MMVM_INVALIDATE_ENG5_ACK 6292 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6293 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6294 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6295 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6296 //MMVM_INVALIDATE_ENG6_ACK 6297 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6298 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6299 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6300 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6301 //MMVM_INVALIDATE_ENG7_ACK 6302 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6303 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6304 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6305 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6306 //MMVM_INVALIDATE_ENG8_ACK 6307 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6308 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6309 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6310 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6311 //MMVM_INVALIDATE_ENG9_ACK 6312 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6313 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6314 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6315 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6316 //MMVM_INVALIDATE_ENG10_ACK 6317 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6318 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6319 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6320 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6321 //MMVM_INVALIDATE_ENG11_ACK 6322 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6323 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6324 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6325 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6326 //MMVM_INVALIDATE_ENG12_ACK 6327 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6328 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6329 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6330 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6331 //MMVM_INVALIDATE_ENG13_ACK 6332 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6333 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6334 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6335 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6336 //MMVM_INVALIDATE_ENG14_ACK 6337 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6338 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6339 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6340 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6341 //MMVM_INVALIDATE_ENG15_ACK 6342 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6343 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6344 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6345 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6346 //MMVM_INVALIDATE_ENG16_ACK 6347 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6348 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6349 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6350 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6351 //MMVM_INVALIDATE_ENG17_ACK 6352 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6353 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6354 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6355 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6356 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6357 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6358 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6359 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6360 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6361 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6362 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6363 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6364 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6365 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6366 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6367 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6368 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6369 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6370 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6371 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6372 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6373 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6374 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6375 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6376 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6377 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6378 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6379 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6380 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6381 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6382 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6383 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6384 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6385 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6386 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6387 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6388 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6389 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6390 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6391 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6392 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6393 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6394 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6395 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6396 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6397 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6398 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6399 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6400 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6401 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6402 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6403 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6404 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6405 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6406 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6407 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6408 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6409 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6410 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6411 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6412 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6413 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6414 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6415 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6416 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6417 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6418 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6419 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6420 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6421 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6422 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6423 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6424 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6425 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6426 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6427 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6428 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6429 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6430 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6431 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6432 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6433 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6434 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6435 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6436 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6437 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6438 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6439 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6440 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6441 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6442 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6443 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6444 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6445 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6446 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6447 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6448 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6449 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6450 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6451 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6452 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6453 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6454 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6455 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6456 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6457 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6458 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6459 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6460 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6461 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6462 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6463 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6464 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6465 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6466 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6467 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6468 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6469 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6470 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6471 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6472 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6473 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6474 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6475 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6476 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6477 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6478 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6479 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6480 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6481 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6482 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6483 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6484 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6485 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6486 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6487 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6488 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6489 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6490 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6491 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6492 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6493 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6494 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6495 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6496 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6497 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6498 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6499 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6500 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6501 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6502 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6503 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6504 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6505 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6506 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6507 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6508 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6509 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6510 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6511 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6512 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6513 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6514 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6515 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6516 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6517 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6518 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6519 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6520 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6521 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6522 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6523 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6524 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6525 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6526 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6527 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6528 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6529 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6530 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6531 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6532 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6533 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6534 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6535 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6536 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6537 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6538 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6539 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6540 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6541 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6542 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6543 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6544 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6545 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6546 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6547 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6548 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6549 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6550 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6551 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6552 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6553 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6554 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6555 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6556 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6557 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6558 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6559 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6560 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6561 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6562 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6563 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6564 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6565 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6566 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6567 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6568 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6569 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6570 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6571 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6572 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6573 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6574 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6575 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6576 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6577 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6578 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6579 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6580 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6581 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6582 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6583 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6584 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6585 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6586 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6587 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6588 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6589 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6590 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6591 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6592 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6593 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6594 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6595 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6596 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6597 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6598 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6599 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6600 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6601 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6602 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6603 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6604 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6605 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6606 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6607 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6608 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6609 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6610 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6611 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6612 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6613 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6614 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6615 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6616 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6617 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6618 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6619 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6620 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6621 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6622 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6623 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6624 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6625 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6626 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6627 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6628 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6629 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6630 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6631 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6632 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6633 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6634 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6635 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6636 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6637 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6638 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6639 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6640 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6641 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6642 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6643 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6644 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6645 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6646 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6647 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6648 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6649 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6650 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6651 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6652 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6653 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6654 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6655 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6656 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6657 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6658 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6659 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6660 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6661 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6662 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6663 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6664 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6665 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6666 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6667 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6668 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6669 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6670 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6671 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6672 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6673 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6674 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6675 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6676 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6677 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6678 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6679 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6680 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6681 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6682 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6683 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6684 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6685 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6686 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6687 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6688 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6689 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6690 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6691 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6692 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6693 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6694 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6695 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6696 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6697 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6698 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6699 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6700 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6701 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6702 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6703 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6704 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6705 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6706 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6707 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6708 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6709 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6710 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6711 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6712 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6713 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6714 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6715 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6716 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6717 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6718 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6719 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6720 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6721 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6722 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6723 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6724 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6725 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6726 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6727 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6728 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6729 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6730 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6731 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6732 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6733 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6734 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6735 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6736 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6737 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6738 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6739 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6740 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6741 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6742 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6743 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6744 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6745 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6746 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6747 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6748 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6749 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6750 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6751 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6752 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6753 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6754 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6755 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6756 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6757 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6758 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6759 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6760 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6761 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6762 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6763 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6764 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6765 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6766 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6767 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6768 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6769 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6770 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6771 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6772 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6773 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6774 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6775 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6776 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6777 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6778 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6779 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6780 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6781 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6782 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6783 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6784 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6785 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6786 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6787 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6788 //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6789 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6790 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6791 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6792 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6793 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6794 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6795 //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6796 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6797 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6798 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6799 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6800 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6801 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6802 //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6803 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6804 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6805 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6806 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6807 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6808 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6809 //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6810 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6811 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6812 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6813 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6814 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6815 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6816 //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6817 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6818 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6819 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6820 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6821 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6822 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6823 //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6824 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6825 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6826 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6827 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6828 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6829 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6830 //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6831 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6832 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6833 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6834 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6835 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6836 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6837 //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6838 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6839 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6840 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6841 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6842 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6843 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6844 //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6845 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6846 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6847 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6848 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6849 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6850 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6851 //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6852 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6853 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6854 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6855 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6856 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6857 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6858 //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6859 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6860 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6861 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6862 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6863 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6864 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6865 //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6866 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6867 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6868 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6869 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6870 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6871 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6872 //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6873 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6874 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6875 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6876 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6877 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6878 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6879 //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6880 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6881 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6882 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6883 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6884 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6885 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6886 //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6887 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6888 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6889 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6890 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6891 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6892 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6893 //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6894 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6895 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6896 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6897 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6898 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6899 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6900 //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6901 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6902 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6903 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6904 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6905 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6906 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6907 6908 6909 // addressBlock: mmhub_mmutcl2_mmvml2pspdec 6910 //MMUTCL2_TRANSLATION_BYPASS_BY_VMID 6911 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 6912 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 6913 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL 6914 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L 6915 //MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 6916 #define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 6917 #define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L 6918 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 6919 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 6920 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L 6921 //MMVM_IOMMU_CONTROL_REGISTER 6922 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 6923 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 6924 //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 6925 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 6926 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 6927 //MMUTC_TRANSLATION_FAULT_CNTL0 6928 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 6929 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL 6930 //MMUTC_TRANSLATION_FAULT_CNTL1 6931 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 6932 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 6933 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 6934 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 6935 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL 6936 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L 6937 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L 6938 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L 6939 //MMUTCL2_VSCH_POWER_STATUS 6940 #define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN__SHIFT 0x0 6941 #define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN_MASK 0x00000001L 6942 6943 #endif 6944