1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_3_3_0_SH_MASK_HEADER 24 #define _mmhub_3_3_0_SH_MASK_HEADER 25 26 27 // addressBlock: mmhub_dagbdec 28 //DAGB0_RDCLI0 29 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 //DAGB0_RDCLI1 50 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 //DAGB0_RDCLI2 71 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 //DAGB0_RDCLI3 92 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 //DAGB0_RDCLI4 113 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 //DAGB0_RDCLI5 134 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 //DAGB0_RDCLI6 155 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 //DAGB0_RDCLI7 176 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 //DAGB0_RDCLI8 197 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 //DAGB0_RDCLI9 218 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 //DAGB0_RDCLI10 239 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 //DAGB0_RDCLI11 260 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 //DAGB0_RDCLI12 281 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 //DAGB0_RDCLI13 302 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 //DAGB0_RDCLI14 323 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 //DAGB0_RDCLI15 344 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 //DAGB0_RDCLI16 365 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367 #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368 #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369 #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370 #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371 #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372 #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374 #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375 #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377 #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378 #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379 #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380 #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381 #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382 #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384 #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385 //DAGB0_RDCLI17 386 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388 #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389 #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390 #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391 #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392 #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393 #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395 #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396 #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398 #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399 #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400 #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401 #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402 #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403 #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405 #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406 //DAGB0_RDCLI18 407 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409 #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410 #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411 #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412 #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413 #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414 #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416 #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417 #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419 #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420 #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421 #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422 #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423 #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424 #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426 #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427 //DAGB0_RDCLI19 428 #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430 #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431 #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432 #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433 #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434 #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435 #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437 #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438 #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440 #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441 #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442 #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443 #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444 #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445 #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447 #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448 //DAGB0_RDCLI20 449 #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451 #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452 #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453 #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454 #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455 #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456 #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458 #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459 #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461 #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462 #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463 #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464 #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465 #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466 #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468 #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469 //DAGB0_RDCLI21 470 #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472 #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473 #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474 #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475 #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476 #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477 #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479 #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480 #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482 #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483 #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484 #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485 #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486 #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487 #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489 #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490 //DAGB0_RDCLI22 491 #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493 #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494 #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495 #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496 #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497 #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498 #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500 #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501 #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503 #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504 #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505 #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506 #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507 #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508 #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510 #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511 //DAGB0_RDCLI23 512 #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514 #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515 #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516 #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517 #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518 #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519 #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521 #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522 #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524 #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525 #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526 #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527 #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528 #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529 #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531 #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532 //DAGB0_RDCLI24 533 #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 534 #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 535 #define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 536 #define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 537 #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc 538 #define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd 539 #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 540 #define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 541 #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 542 #define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a 543 #define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L 544 #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 545 #define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L 546 #define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L 547 #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L 548 #define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L 549 #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L 550 #define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L 551 #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 552 #define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L 553 //DAGB0_RDCLI25 554 #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 555 #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 556 #define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 557 #define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 558 #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc 559 #define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd 560 #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 561 #define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 562 #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 563 #define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a 564 #define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L 565 #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 566 #define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L 567 #define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L 568 #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L 569 #define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L 570 #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L 571 #define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L 572 #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 573 #define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L 574 //DAGB0_RDCLI26 575 #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 576 #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 577 #define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 578 #define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 579 #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc 580 #define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd 581 #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 582 #define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 583 #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 584 #define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a 585 #define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L 586 #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 587 #define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L 588 #define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L 589 #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L 590 #define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L 591 #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L 592 #define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L 593 #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 594 #define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L 595 //DAGB0_RDCLI27 596 #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 597 #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 598 #define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 599 #define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 600 #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc 601 #define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd 602 #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 603 #define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 604 #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 605 #define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a 606 #define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L 607 #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 608 #define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L 609 #define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L 610 #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L 611 #define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L 612 #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L 613 #define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L 614 #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 615 #define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L 616 //DAGB0_RDCLI28 617 #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 618 #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 619 #define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 620 #define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 621 #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc 622 #define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd 623 #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 624 #define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 625 #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 626 #define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a 627 #define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L 628 #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 629 #define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L 630 #define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L 631 #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L 632 #define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L 633 #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L 634 #define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L 635 #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 636 #define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L 637 //DAGB0_RDCLI29 638 #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 639 #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 640 #define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 641 #define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 642 #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc 643 #define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd 644 #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 645 #define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 646 #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 647 #define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a 648 #define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L 649 #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 650 #define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L 651 #define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L 652 #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L 653 #define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L 654 #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L 655 #define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L 656 #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 657 #define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L 658 //DAGB0_RDCLI30 659 #define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 660 #define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 661 #define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 662 #define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 663 #define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc 664 #define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd 665 #define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 666 #define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 667 #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 668 #define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a 669 #define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L 670 #define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 671 #define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L 672 #define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L 673 #define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L 674 #define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L 675 #define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L 676 #define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L 677 #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 678 #define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L 679 //DAGB0_RD_CNTL 680 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 681 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 682 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 683 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 684 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 685 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 686 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 687 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 688 //DAGB0_RD_IO_CNTL 689 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 690 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 691 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 692 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 693 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 694 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 695 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 696 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 697 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 698 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 699 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 700 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 701 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 702 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 703 //DAGB0_RD_GMI_CNTL 704 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 705 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 706 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 707 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 708 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 709 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 710 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 711 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 712 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 713 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 714 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 715 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 716 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 717 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 718 //DAGB0_RD_ADDR_DAGB 719 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 720 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 721 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 722 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 723 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 724 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 725 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 726 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 727 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 728 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 729 //DAGB0_RD_CGTT_CLK_CTRL 730 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 731 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 732 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 733 #define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 734 #define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 735 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 736 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 737 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 738 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 739 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 740 #define DAGB0_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 741 #define DAGB0_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 742 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 743 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 744 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 745 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 746 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 747 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 748 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 749 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 750 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 751 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 752 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 753 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 754 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 755 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 756 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 757 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 758 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 759 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 760 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 761 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 762 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 763 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 764 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 765 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 766 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 767 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 768 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 769 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 770 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 771 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 772 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 773 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 774 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 775 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 776 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 777 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 778 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 779 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 780 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 781 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 782 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 783 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 784 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 785 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 786 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 787 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 788 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 789 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 790 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 791 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 792 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 793 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 794 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 795 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 796 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 797 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 798 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 799 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 800 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 801 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 802 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 803 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 804 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 805 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 806 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 807 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 808 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 809 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 810 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 811 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 812 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 813 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 814 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 815 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 816 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 817 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 818 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 819 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 820 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 821 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 822 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 823 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 824 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 825 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 826 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 827 //DAGB0_RD_ADDR_DAGB_MAX_BURST2 828 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 829 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 830 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 831 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 832 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 833 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 834 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 835 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 836 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 837 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 838 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 839 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 840 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 841 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 842 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 843 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 844 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 845 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 846 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 847 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 848 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 849 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 850 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 851 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 852 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 853 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 854 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 855 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 856 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 857 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 858 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 859 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 860 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 861 //DAGB0_RD_ADDR_DAGB_MAX_BURST3 862 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 863 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 864 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 865 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 866 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 867 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 868 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 869 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 870 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 871 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 872 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 873 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 874 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 875 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 876 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 877 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 878 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 879 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 880 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 881 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 882 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 883 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 884 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 885 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 886 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 887 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 888 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 889 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 890 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 891 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 892 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 893 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 894 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 895 //DAGB0_RD_VC0_CNTL 896 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 897 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 898 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 899 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 900 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 901 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 902 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 903 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000007FL 904 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 905 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 906 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 907 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 908 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 909 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 910 //DAGB0_RD_VC1_CNTL 911 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 912 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 913 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 914 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 915 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 916 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 917 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 918 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000007FL 919 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 920 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 921 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 922 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 923 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 924 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 925 //DAGB0_RD_VC2_CNTL 926 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 927 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 928 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 929 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 930 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 931 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 932 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 933 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000007FL 934 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 935 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 936 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 937 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 938 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 939 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 940 //DAGB0_RD_VC3_CNTL 941 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 942 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 943 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 944 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 945 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 946 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 947 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 948 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000007FL 949 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 950 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 951 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 952 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 953 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 954 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 955 //DAGB0_RD_VC4_CNTL 956 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 957 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 958 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 959 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 960 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 961 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 962 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 963 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000007FL 964 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 965 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 966 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 967 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 968 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 969 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 970 //DAGB0_RD_VC5_CNTL 971 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 972 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 973 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 974 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 975 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 976 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 977 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 978 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000007FL 979 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 980 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 981 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 982 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 983 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 984 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 985 //DAGB0_RD_IO_VC_CNTL 986 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 987 #define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 988 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 989 #define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 990 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 991 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 992 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 993 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 994 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 995 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 996 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 997 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 998 //DAGB0_RD_GMI_VC_CNTL 999 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1000 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 1001 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1002 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 1003 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1004 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 1005 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1006 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 1007 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1008 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 1009 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1010 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1011 //DAGB0_RD_CNTL_MISC 1012 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1013 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x8 1014 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x000000FFL 1015 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x00000700L 1016 //DAGB0_RD_TLB_CREDIT 1017 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 1018 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 1019 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 1020 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 1021 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 1022 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 1023 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 1024 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 1025 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 1026 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 1027 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 1028 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 1029 //DAGB0_RDCLI_ASK_PENDING 1030 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 1031 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1032 //DAGB0_RDCLI_GO_PENDING 1033 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 1034 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1035 //DAGB0_RDCLI_GBLSEND_PENDING 1036 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1037 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1038 //DAGB0_RDCLI_TLB_PENDING 1039 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 1040 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1041 //DAGB0_RDCLI_OARB_PENDING 1042 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 1043 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1044 //DAGB0_RDCLI_ASK2ARB_PENDING 1045 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 1046 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1047 //DAGB0_RDCLI_ASK2DF_PENDING 1048 #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 1049 #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 1050 //DAGB0_RDCLI_OSD_PENDING 1051 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 1052 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1053 //DAGB0_RDCLI_ASK_OSD_PENDING 1054 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 1055 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1056 //DAGB0_RDCLI_NOALLOC_OVERRIDE 1057 #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 1058 #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1059 //DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 1060 #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 1061 #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 1062 //DAGB0_WRCLI0 1063 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 1064 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1065 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 1066 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 1067 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 1068 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 1069 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 1070 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 1071 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1072 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 1073 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 1074 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1075 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 1076 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 1077 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1078 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 1079 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1080 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 1081 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1082 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 1083 //DAGB0_WRCLI1 1084 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 1085 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1086 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 1087 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 1088 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 1089 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 1090 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 1091 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 1092 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1093 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 1094 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 1095 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1096 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 1097 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 1098 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1099 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 1100 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1101 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 1102 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1103 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 1104 //DAGB0_WRCLI2 1105 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 1106 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1107 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 1108 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 1109 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 1110 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 1111 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 1112 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 1113 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1114 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 1115 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 1116 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1117 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 1118 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 1119 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1120 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 1121 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1122 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 1123 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1124 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 1125 //DAGB0_WRCLI3 1126 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 1127 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1128 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 1129 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 1130 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 1131 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 1132 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 1133 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 1134 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1135 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 1136 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 1137 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1138 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 1139 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 1140 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1141 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 1142 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1143 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 1144 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1145 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 1146 //DAGB0_WRCLI4 1147 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 1148 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1149 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 1150 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 1151 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 1152 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 1153 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 1154 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 1155 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1156 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 1157 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 1158 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1159 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 1160 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 1161 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1162 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 1163 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1164 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 1165 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1166 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1167 //DAGB0_WRCLI5 1168 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1169 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1170 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1171 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1172 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1173 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1174 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1175 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1176 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1177 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1178 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1179 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1180 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1181 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1182 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1183 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1184 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1185 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1186 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1187 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1188 //DAGB0_WRCLI6 1189 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1190 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1191 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1192 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1193 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1194 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1195 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1196 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1197 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1198 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1199 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1200 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1201 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1202 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1203 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1204 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1205 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1206 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1207 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1208 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1209 //DAGB0_WRCLI7 1210 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1211 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1212 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1213 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1214 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1215 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1216 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1217 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1218 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1219 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1220 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1221 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1222 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1223 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1224 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1225 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1226 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1227 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1228 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1229 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1230 //DAGB0_WRCLI8 1231 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1232 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1233 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1234 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1235 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1236 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1237 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1238 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1239 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1240 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1241 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1242 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1243 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1244 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1245 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1246 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1247 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1248 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1249 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1250 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1251 //DAGB0_WRCLI9 1252 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1253 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1254 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1255 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1256 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1257 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1258 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1259 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1260 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1261 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1262 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1263 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1264 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1265 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1266 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1267 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1268 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1269 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1270 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1271 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1272 //DAGB0_WRCLI10 1273 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1274 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1275 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1276 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1277 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1278 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1279 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1280 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1281 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1282 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1283 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1284 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1285 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1286 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1287 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1288 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1289 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1290 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1291 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1292 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1293 //DAGB0_WRCLI11 1294 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1295 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1296 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1297 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1298 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1299 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1300 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1301 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1302 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1303 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1304 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1305 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1306 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1307 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1308 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1309 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1310 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1311 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1312 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1313 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1314 //DAGB0_WRCLI12 1315 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1316 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1317 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1318 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1319 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1320 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1321 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1322 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1323 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1324 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1325 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1326 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1327 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1328 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1329 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1330 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1331 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1332 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1333 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1334 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1335 //DAGB0_WRCLI13 1336 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1337 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1338 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1339 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1340 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1341 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1342 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1343 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1344 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1345 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1346 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1347 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1348 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1349 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1350 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1351 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1352 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1353 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1354 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1355 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1356 //DAGB0_WRCLI14 1357 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1358 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1359 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1360 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1361 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1362 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1363 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1364 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1365 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1366 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1367 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1368 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1369 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1370 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1371 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1372 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1373 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1374 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1375 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1376 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1377 //DAGB0_WRCLI15 1378 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1379 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1380 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1381 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1382 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1383 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1384 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1385 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1386 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1387 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1388 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1389 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1390 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1391 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1392 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1393 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1394 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1395 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1396 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1397 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1398 //DAGB0_WRCLI16 1399 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1400 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1401 #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1402 #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1403 #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1404 #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1405 #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1406 #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1407 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1408 #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1409 #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1410 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1411 #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1412 #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1413 #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1414 #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1415 #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1416 #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1417 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1418 #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1419 //DAGB0_WRCLI17 1420 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1421 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1422 #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1423 #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1424 #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1425 #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1426 #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1427 #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1428 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1429 #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1430 #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1431 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1432 #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1433 #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1434 #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1435 #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1436 #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1437 #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1438 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1439 #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1440 //DAGB0_WRCLI18 1441 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1442 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1443 #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1444 #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1445 #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1446 #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1447 #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1448 #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1449 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1450 #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1451 #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1452 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1453 #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1454 #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1455 #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1456 #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1457 #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1458 #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1459 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1460 #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1461 //DAGB0_WRCLI19 1462 #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1463 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1464 #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1465 #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1466 #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1467 #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1468 #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1469 #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1470 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1471 #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1472 #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1473 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1474 #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1475 #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1476 #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1477 #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1478 #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1479 #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1480 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1481 #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1482 //DAGB0_WRCLI20 1483 #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1484 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1485 #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1486 #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1487 #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1488 #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1489 #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1490 #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1491 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1492 #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1493 #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1494 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1495 #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1496 #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1497 #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1498 #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1499 #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1500 #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1501 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1502 #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1503 //DAGB0_WRCLI21 1504 #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1505 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1506 #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1507 #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1508 #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1509 #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1510 #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1511 #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1512 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1513 #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1514 #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1515 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1516 #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1517 #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1518 #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1519 #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1520 #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1521 #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1522 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1523 #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1524 //DAGB0_WRCLI22 1525 #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1526 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1527 #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1528 #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1529 #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1530 #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1531 #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1532 #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1533 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1534 #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1535 #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1536 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1537 #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1538 #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1539 #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1540 #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1541 #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1542 #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1543 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1544 #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1545 //DAGB0_WRCLI23 1546 #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1547 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1548 #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1549 #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1550 #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1551 #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1552 #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1553 #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1554 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1555 #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1556 #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1557 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1558 #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1559 #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1560 #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1561 #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1562 #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1563 #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1564 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1565 #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1566 //DAGB0_WRCLI24 1567 #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 1568 #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 1569 #define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 1570 #define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 1571 #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc 1572 #define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd 1573 #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 1574 #define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 1575 #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 1576 #define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a 1577 #define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L 1578 #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 1579 #define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L 1580 #define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L 1581 #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L 1582 #define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L 1583 #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L 1584 #define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L 1585 #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 1586 #define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L 1587 //DAGB0_WRCLI25 1588 #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 1589 #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 1590 #define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 1591 #define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 1592 #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc 1593 #define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd 1594 #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 1595 #define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 1596 #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 1597 #define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a 1598 #define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L 1599 #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 1600 #define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L 1601 #define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L 1602 #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L 1603 #define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L 1604 #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L 1605 #define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L 1606 #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 1607 #define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L 1608 //DAGB0_WRCLI26 1609 #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 1610 #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 1611 #define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 1612 #define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 1613 #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc 1614 #define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd 1615 #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 1616 #define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 1617 #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 1618 #define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a 1619 #define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L 1620 #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 1621 #define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L 1622 #define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L 1623 #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L 1624 #define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L 1625 #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L 1626 #define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L 1627 #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 1628 #define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L 1629 //DAGB0_WRCLI27 1630 #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 1631 #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 1632 #define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 1633 #define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 1634 #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc 1635 #define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd 1636 #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 1637 #define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 1638 #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 1639 #define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a 1640 #define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L 1641 #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 1642 #define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L 1643 #define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L 1644 #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L 1645 #define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L 1646 #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L 1647 #define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L 1648 #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 1649 #define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L 1650 //DAGB0_WRCLI28 1651 #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 1652 #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 1653 #define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 1654 #define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 1655 #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc 1656 #define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd 1657 #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 1658 #define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 1659 #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 1660 #define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a 1661 #define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L 1662 #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 1663 #define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L 1664 #define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L 1665 #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L 1666 #define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L 1667 #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L 1668 #define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L 1669 #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 1670 #define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L 1671 //DAGB0_WRCLI29 1672 #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 1673 #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 1674 #define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 1675 #define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 1676 #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc 1677 #define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd 1678 #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 1679 #define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 1680 #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 1681 #define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a 1682 #define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L 1683 #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 1684 #define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L 1685 #define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L 1686 #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L 1687 #define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L 1688 #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L 1689 #define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L 1690 #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 1691 #define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L 1692 //DAGB0_WRCLI30 1693 #define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 1694 #define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 1695 #define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 1696 #define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 1697 #define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc 1698 #define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd 1699 #define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 1700 #define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 1701 #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 1702 #define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a 1703 #define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L 1704 #define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 1705 #define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L 1706 #define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L 1707 #define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L 1708 #define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L 1709 #define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L 1710 #define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L 1711 #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 1712 #define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L 1713 //DAGB0_WR_CNTL 1714 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 1715 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 1716 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc 1717 #define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd 1718 #define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe 1719 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 1720 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 1721 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L 1722 #define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L 1723 #define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L 1724 //DAGB0_WR_IO_CNTL 1725 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1726 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1727 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1728 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1729 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1730 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1731 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 1732 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1733 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1734 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1735 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1736 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1737 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1738 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1739 //DAGB0_WR_GMI_CNTL 1740 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1741 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1742 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1743 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1744 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1745 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1746 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 1747 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1748 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1749 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1750 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1751 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1752 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1753 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1754 //DAGB0_WR_ADDR_DAGB 1755 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1756 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1757 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1758 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1759 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1760 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1761 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1762 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1763 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1764 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1765 //DAGB0_WR_CGTT_CLK_CTRL 1766 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1767 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1768 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1769 #define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 1770 #define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 1771 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1772 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1773 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1774 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1775 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 1776 #define DAGB0_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 1777 #define DAGB0_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 1778 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1779 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1780 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1781 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1782 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1783 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1784 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 1785 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 1786 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1787 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1788 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1789 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1790 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 1791 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 1792 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 1793 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1794 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1795 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1796 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1797 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1798 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1799 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1800 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1801 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1802 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1803 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1804 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1805 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1806 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1807 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1808 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1809 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1810 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1811 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1812 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1813 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1814 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1815 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1816 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1817 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1818 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1819 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1820 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1821 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1822 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1823 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1824 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1825 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1826 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1827 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1828 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1829 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1830 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1831 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1832 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1833 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1834 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1835 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1836 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1837 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1838 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1839 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1840 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1841 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1842 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1843 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1844 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1845 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1846 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1847 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1848 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1849 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1850 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1851 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1852 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1853 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1854 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1855 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1856 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1857 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1858 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1859 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1860 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1861 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1862 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1863 //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1864 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1865 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1866 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1867 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1868 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1869 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1870 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1871 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1872 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1873 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1874 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1875 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1876 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1877 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1878 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1879 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1880 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1881 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1882 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1883 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1884 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1885 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1886 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1887 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1888 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1889 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1890 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1891 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1892 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1893 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1894 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1895 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1896 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1897 //DAGB0_WR_ADDR_DAGB_MAX_BURST3 1898 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 1899 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 1900 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 1901 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 1902 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 1903 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 1904 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 1905 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 1906 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 1907 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 1908 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 1909 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 1910 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 1911 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 1912 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 1913 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 1914 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 1915 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 1916 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 1917 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 1918 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 1919 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 1920 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 1921 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 1922 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 1923 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 1924 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 1925 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 1926 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 1927 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 1928 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 1929 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 1930 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 1931 //DAGB0_WR_DATA_DAGB 1932 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1933 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1934 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1935 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1936 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1937 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1938 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1939 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1940 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1941 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1942 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1943 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1944 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1945 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1946 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1947 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1948 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1949 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1950 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1951 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1952 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1953 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1954 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1955 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1956 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1957 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1958 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1959 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1960 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1961 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1962 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1963 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1964 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1965 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1966 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1967 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1968 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1969 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1970 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1971 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1972 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1973 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1974 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1975 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1976 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1977 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1978 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1979 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1980 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1981 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1982 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1983 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1984 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1985 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1986 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1987 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1988 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1989 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1990 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1991 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1992 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1993 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1994 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1995 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1996 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1997 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1998 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1999 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2000 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2001 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2002 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2003 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2004 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2005 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2006 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2007 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2008 //DAGB0_WR_DATA_DAGB_MAX_BURST2 2009 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 2010 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 2011 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 2012 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 2013 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 2014 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 2015 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 2016 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 2017 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 2018 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 2019 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 2020 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 2021 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 2022 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 2023 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 2024 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 2025 //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 2026 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 2027 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 2028 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 2029 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 2030 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 2031 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 2032 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 2033 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 2034 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 2035 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 2036 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 2037 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 2038 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 2039 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 2040 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 2041 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 2042 //DAGB0_WR_DATA_DAGB_MAX_BURST3 2043 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 2044 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 2045 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 2046 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 2047 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 2048 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 2049 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 2050 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 2051 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 2052 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 2053 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 2054 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 2055 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 2056 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 2057 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 2058 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 2059 //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 2060 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 2061 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 2062 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 2063 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2064 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2065 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2066 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2067 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2068 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2069 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2070 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2071 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2072 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2073 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2074 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2075 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2076 //DAGB0_WR_VC0_CNTL 2077 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2078 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2079 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 2080 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2081 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 2082 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2083 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 2084 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000007FL 2085 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2086 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2087 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2088 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2089 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2090 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2091 //DAGB0_WR_VC1_CNTL 2092 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2093 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2094 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 2095 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2096 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 2097 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2098 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 2099 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000007FL 2100 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2101 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2102 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2103 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2104 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2105 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2106 //DAGB0_WR_VC2_CNTL 2107 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2108 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2109 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 2110 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2111 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 2112 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2113 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 2114 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000007FL 2115 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2116 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2117 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2118 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2119 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2120 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2121 //DAGB0_WR_VC3_CNTL 2122 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2123 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2124 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 2125 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2126 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 2127 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2128 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 2129 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000007FL 2130 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2131 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2132 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2133 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2134 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2135 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2136 //DAGB0_WR_VC4_CNTL 2137 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2138 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2139 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 2140 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2141 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 2142 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2143 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 2144 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000007FL 2145 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2146 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2147 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2148 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2149 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2150 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2151 //DAGB0_WR_VC5_CNTL 2152 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2153 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2154 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 2155 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2156 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 2157 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2158 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 2159 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000007FL 2160 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2161 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2162 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2163 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2164 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2165 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2166 //DAGB0_WR_IO_VC_CNTL 2167 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2168 #define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc 2169 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2170 #define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 2171 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2172 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 2173 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2174 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 2175 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2176 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 2177 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2178 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 2179 //DAGB0_WR_GMI_VC_CNTL 2180 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2181 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 2182 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2183 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 2184 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2185 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 2186 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2187 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 2188 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2189 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 2190 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2191 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 2192 //DAGB0_WR_CNTL_MISC 2193 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2194 #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x8 2195 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x000000FFL 2196 #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x00001F00L 2197 //DAGB0_WR_TLB_CREDIT 2198 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 2199 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 2200 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 2201 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 2202 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 2203 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 2204 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 2205 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 2206 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 2207 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 2208 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 2209 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 2210 //DAGB0_WR_DATA_CREDIT 2211 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 2212 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 2213 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 2214 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 2215 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 2216 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 2217 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 2218 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 2219 //DAGB0_WR_MISC_CREDIT 2220 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 2221 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 2222 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 2223 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 2224 //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 2225 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2226 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2227 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2228 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2229 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2230 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b 2231 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c 2232 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2233 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2234 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2235 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2236 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x07F00000L 2237 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L 2238 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L 2239 //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 2240 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2241 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2242 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2243 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2244 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2245 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 2246 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 2247 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2248 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2249 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2250 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2251 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L 2252 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 2253 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 2254 //DAGB0_WRCLI_ASK_PENDING 2255 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 2256 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2257 //DAGB0_WRCLI_GO_PENDING 2258 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 2259 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2260 //DAGB0_WRCLI_GBLSEND_PENDING 2261 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2262 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2263 //DAGB0_WRCLI_TLB_PENDING 2264 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 2265 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2266 //DAGB0_WRCLI_OARB_PENDING 2267 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 2268 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2269 //DAGB0_WRCLI_ASK2ARB_PENDING 2270 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 2271 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2272 //DAGB0_WRCLI_ASK2DF_PENDING 2273 #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 2274 #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 2275 //DAGB0_WRCLI_OSD_PENDING 2276 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 2277 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2278 //DAGB0_WRCLI_ASK_OSD_PENDING 2279 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 2280 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2281 //DAGB0_WRCLI_DBUS_ASK_PENDING 2282 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 2283 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2284 //DAGB0_WRCLI_DBUS_GO_PENDING 2285 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 2286 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2287 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 2288 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 2289 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 2290 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 2291 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 2292 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 2293 //DAGB0_WRCLI_NOALLOC_OVERRIDE 2294 #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 2295 #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 2296 //DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 2297 #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 2298 #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 2299 //DAGB0_DAGB_DLY 2300 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 2301 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 2302 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 2303 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 2304 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 2305 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 2306 //DAGB0_CNTL_MISC 2307 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 2308 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 2309 //DAGB0_CNTL_MISC2 2310 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 2311 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 2312 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 2313 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 2314 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 2315 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 2316 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 2317 #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 2318 #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 2319 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 2320 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 2321 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 2322 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 2323 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 2324 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 2325 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 2326 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 2327 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 2328 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 2329 #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 2330 #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 2331 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 2332 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 2333 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 2334 //DAGB0_FIFO_EMPTY 2335 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 2336 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 2337 //DAGB0_FIFO_FULL 2338 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 2339 #define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL 2340 //DAGB0_RD_CREDITS_FULL 2341 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 2342 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 2343 //DAGB0_WR_CREDITS_FULL 2344 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 2345 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL 2346 //DAGB0_PERFCOUNTER_LO 2347 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2348 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2349 //DAGB0_PERFCOUNTER_HI 2350 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2351 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2352 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2353 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2354 //DAGB0_PERFCOUNTER0_CFG 2355 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2356 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2357 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2358 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2359 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2360 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2361 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2362 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2363 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2364 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2365 //DAGB0_PERFCOUNTER1_CFG 2366 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2367 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2368 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2369 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2370 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2371 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2372 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2373 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2374 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2375 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2376 //DAGB0_PERFCOUNTER2_CFG 2377 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2378 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2379 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2380 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2381 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2382 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2383 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2384 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2385 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2386 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2387 //DAGB0_PERFCOUNTER_RSLT_CNTL 2388 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2389 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2390 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2391 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2392 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2393 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2394 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 2395 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2396 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2397 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2398 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2399 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2400 //DAGB0_L1TLB_REG_RW 2401 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 2402 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 2403 #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 2404 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 2405 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 2406 #define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 2407 //DAGB0_RESERVE1 2408 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2409 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2410 //DAGB0_RESERVE2 2411 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2412 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2413 //DAGB0_RESERVE3 2414 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2415 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2416 //DAGB0_RESERVE4 2417 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2418 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2419 //DAGB0_SDP_RD_BW_CNTL 2420 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2421 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x1 2422 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0x2 2423 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0xb 2424 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0x15 2425 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2426 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000002L 2427 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x000007FCL 2428 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x001FF800L 2429 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x07E00000L 2430 //DAGB0_SDP_PRIORITY_OVERRIDE 2431 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 2432 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2433 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 2434 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 2435 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 2436 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 2437 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 2438 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 2439 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 2440 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 2441 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 2442 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 2443 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 2444 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 2445 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 2446 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 2447 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 2448 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2449 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 2450 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 2451 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 2452 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 2453 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 2454 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 2455 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 2456 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 2457 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 2458 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 2459 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 2460 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 2461 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 2462 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 2463 //DAGB0_SDP_RD_PRIORITY 2464 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 2465 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 2466 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 2467 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 2468 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 2469 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 2470 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 2471 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 2472 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 2473 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 2474 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 2475 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 2476 //DAGB0_SDP_WR_PRIORITY 2477 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 2478 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 2479 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 2480 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc 2481 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 2482 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 2483 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL 2484 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L 2485 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L 2486 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L 2487 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L 2488 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L 2489 //DAGB0_SDP_RD_CLI2SDP_VC_MAP 2490 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2491 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2492 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2493 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2494 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2495 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2496 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2497 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2498 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2499 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2500 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2501 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2502 //DAGB0_SDP_WR_CLI2SDP_VC_MAP 2503 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2504 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2505 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2506 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2507 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2508 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2509 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2510 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2511 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2512 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2513 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2514 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2515 //DAGB0_SDP_ENABLE 2516 #define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 2517 #define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L 2518 //DAGB0_SDP_CREDITS 2519 #define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 2520 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 2521 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 2522 #define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 2523 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 2524 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 2525 //DAGB0_SDP_TAG_RESERVE0 2526 #define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 2527 #define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 2528 #define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 2529 #define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 2530 #define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 2531 #define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 2532 #define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 2533 #define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 2534 //DAGB0_SDP_TAG_RESERVE1 2535 #define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 2536 #define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 2537 #define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 2538 #define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 2539 #define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 2540 #define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 2541 #define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 2542 #define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 2543 //DAGB0_SDP_VCC_RESERVE0 2544 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 2545 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 2546 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 2547 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 2548 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 2549 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2550 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2551 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2552 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2553 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2554 //DAGB0_SDP_VCC_RESERVE1 2555 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 2556 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 2557 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 2558 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2559 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2560 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2561 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2562 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2563 //DAGB0_SDP_ERR_STATUS 2564 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 2565 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 2566 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 2567 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 2568 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 2569 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 2570 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 2571 #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 2572 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 2573 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 2574 #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 2575 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 2576 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 2577 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 2578 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 2579 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 2580 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 2581 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 2582 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 2583 #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 2584 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 2585 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 2586 #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 2587 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 2588 //DAGB0_SDP_REQ_CNTL 2589 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 2590 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 2591 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 2592 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 2593 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 2594 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 2595 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 2596 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 2597 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 2598 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 2599 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 2600 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 2601 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 2602 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 2603 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 2604 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 2605 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 2606 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 2607 //DAGB0_SDP_MISC_AON 2608 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 2609 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 2610 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 2611 #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 2612 //DAGB0_SDP_MISC 2613 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 2614 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 2615 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 2616 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 2617 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 2618 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 2619 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 2620 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 2621 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 2622 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 2623 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 2624 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 2625 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 2626 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 2627 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 2628 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 2629 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 2630 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 2631 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 2632 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 2633 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 2634 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 2635 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 2636 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 2637 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 2638 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 2639 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 2640 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 2641 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 2642 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 2643 //DAGB0_SDP_MISC2 2644 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 2645 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 2646 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 2647 #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 2648 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 2649 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 2650 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 2651 #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 2652 //DAGB0_SDP_VCD_RESERVE0 2653 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 2654 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 2655 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 2656 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 2657 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 2658 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2659 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2660 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2661 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2662 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2663 //DAGB0_SDP_VCD_RESERVE1 2664 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 2665 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 2666 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 2667 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 2668 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2669 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2670 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2671 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L 2672 //DAGB0_SDP_ARB_CNTL0 2673 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 2674 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 2675 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 2676 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 2677 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 2678 #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 2679 #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 2680 #define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 2681 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 2682 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 2683 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 2684 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 2685 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 2686 #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 2687 #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 2688 #define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 2689 //DAGB0_SDP_ARB_CNTL1 2690 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 2691 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 2692 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 2693 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 2694 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 2695 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 2696 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 2697 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 2698 //DAGB0_SDP_CGTT_CLK_CTRL 2699 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2700 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2701 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2702 #define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 2703 #define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 2704 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2705 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2706 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2707 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2708 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 2709 #define DAGB0_SDP_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 2710 #define DAGB0_SDP_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 2711 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2712 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2713 //DAGB0_SDP_LATENCY_SAMPLING 2714 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 2715 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 2716 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 2717 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 2718 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 2719 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 2720 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 2721 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 2722 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 2723 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 2724 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 2725 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 2726 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 2727 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 2728 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 2729 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 2730 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 2731 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 2732 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 2733 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 2734 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 2735 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 2736 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 2737 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 2738 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 2739 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 2740 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 2741 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 2742 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 2743 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 2744 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 2745 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 2746 2747 2748 // addressBlock: mmhub_pctldec 2749 //PCTL_CTRL 2750 #define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 2751 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 2752 #define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 2753 #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 2754 #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 2755 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 2756 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 2757 #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 2758 #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 2759 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 2760 #define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b 2761 #define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c 2762 #define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d 2763 #define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e 2764 #define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f 2765 #define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 2766 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 2767 #define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L 2768 #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L 2769 #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L 2770 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 2771 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 2772 #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 2773 #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 2774 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L 2775 #define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L 2776 #define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L 2777 #define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L 2778 #define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L 2779 #define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L 2780 //PCTL_MMHUB_DEEPSLEEP_IB 2781 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 2782 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 2783 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 2784 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 2785 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 2786 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 2787 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 2788 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 2789 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 2790 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 2791 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 2792 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 2793 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 2794 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 2795 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 2796 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 2797 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 2798 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 2799 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 2800 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 2801 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 2802 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 2803 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 2804 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 2805 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 2806 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 2807 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 2808 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 2809 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 2810 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 2811 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 2812 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 2813 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 2814 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 2815 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 2816 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 2817 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 2818 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 2819 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 2820 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 2821 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 2822 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 2823 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 2824 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 2825 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 2826 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 2827 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 2828 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 2829 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 2830 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 2831 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 2832 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 2833 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 2834 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 2835 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 2836 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 2837 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 2838 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 2839 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 2840 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 2841 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 2842 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 2843 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 2844 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 2845 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 2846 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 2847 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 2848 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 2849 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 2850 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 2851 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 2852 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 2853 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 2854 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 2855 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 2856 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 2857 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 2858 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 2859 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 2860 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 2861 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 2862 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 2863 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 2864 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 2865 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 2866 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 2867 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 2868 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 2869 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 2870 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 2871 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 2872 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 2873 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 2874 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 2875 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 2876 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 2877 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 2878 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 2879 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 2880 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 2881 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 2882 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 2883 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 2884 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 2885 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 2886 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 2887 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 2888 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 2889 //PCTL_PG_IGNORE_DEEPSLEEP 2890 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 2891 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 2892 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 2893 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 2894 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 2895 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 2896 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 2897 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 2898 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 2899 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 2900 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 2901 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 2902 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 2903 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 2904 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 2905 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 2906 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 2907 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 2908 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 2909 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 2910 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 2911 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 2912 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 2913 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 2914 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 2915 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 2916 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 2917 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 2918 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 2919 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 2920 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 2921 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 2922 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 2923 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 2924 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 2925 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 2926 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 2927 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 2928 //PCTL_PG_IGNORE_DEEPSLEEP_IB 2929 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 2930 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 2931 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 2932 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 2933 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 2934 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 2935 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 2936 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 2937 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 2938 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 2939 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 2940 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 2941 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 2942 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 2943 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 2944 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 2945 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 2946 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 2947 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 2948 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 2949 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 2950 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 2951 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 2952 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 2953 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 2954 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 2955 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 2956 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 2957 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 2958 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 2959 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 2960 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 2961 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 2962 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 2963 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 2964 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 2965 //PCTL_SLICE0_CFG_DAGB_WRBUSY 2966 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 2967 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2968 //PCTL_SLICE0_CFG_DAGB_RDBUSY 2969 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 2970 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 2971 //PCTL_SLICE0_CFG_DS_ALLOW 2972 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 2973 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 2974 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 2975 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 2976 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 2977 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 2978 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 2979 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 2980 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 2981 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 2982 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 2983 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 2984 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 2985 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 2986 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 2987 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 2988 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 2989 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 2990 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 2991 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 2992 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 2993 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 2994 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 2995 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 2996 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 2997 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 2998 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 2999 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3000 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3001 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3002 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3003 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3004 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3005 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3006 //PCTL_SLICE0_CFG_DS_ALLOW_IB 3007 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3008 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3009 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3010 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3011 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3012 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3013 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3014 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3015 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3016 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3017 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3018 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3019 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3020 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3021 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3022 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3023 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3024 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3025 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3026 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3027 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3028 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3029 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3030 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3031 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3032 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3033 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3034 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3035 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3036 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3037 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3038 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3039 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3040 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3041 //PCTL_SLICE1_CFG_DAGB_WRBUSY 3042 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3043 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3044 //PCTL_SLICE1_CFG_DAGB_RDBUSY 3045 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3046 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3047 //PCTL_SLICE1_CFG_DS_ALLOW 3048 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 3049 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 3050 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 3051 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 3052 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 3053 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 3054 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 3055 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 3056 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 3057 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 3058 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 3059 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 3060 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 3061 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 3062 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 3063 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 3064 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 3065 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3066 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3067 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3068 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3069 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3070 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3071 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3072 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3073 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3074 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3075 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3076 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3077 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3078 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3079 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3080 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3081 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3082 //PCTL_SLICE1_CFG_DS_ALLOW_IB 3083 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3084 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3085 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3086 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3087 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3088 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3089 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3090 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3091 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3092 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3093 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3094 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3095 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3096 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3097 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3098 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3099 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3100 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3101 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3102 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3103 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3104 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3105 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3106 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3107 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3108 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3109 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3110 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3111 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3112 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3113 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3114 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3115 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3116 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3117 //PCTL_UTCL2_MISC 3118 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 3119 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 3120 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 3121 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 3122 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3123 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3124 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3125 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3126 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3127 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 3128 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 3129 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 3130 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 3131 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3132 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3133 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3134 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3135 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3136 //PCTL_SLICE0_MISC 3137 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 3138 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 3139 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 3140 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 3141 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 3142 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3143 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3144 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3145 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3146 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3147 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e 3148 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f 3149 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 3150 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 3151 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 3152 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 3153 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 3154 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3155 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3156 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3157 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3158 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3159 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L 3160 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L 3161 //PCTL_SLICE1_MISC 3162 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 3163 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 3164 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 3165 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 3166 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 3167 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 3168 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 3169 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 3170 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 3171 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 3172 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e 3173 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f 3174 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 3175 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 3176 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 3177 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 3178 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 3179 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 3180 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 3181 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 3182 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 3183 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 3184 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L 3185 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L 3186 //PCTL_RENG_CTRL 3187 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 3188 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3189 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 3190 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3191 //PCTL_UTCL2_RENG_EXECUTE 3192 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3193 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3194 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3195 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 3196 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3197 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3198 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 3199 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 3200 //PCTL_SLICE0_RENG_EXECUTE 3201 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3202 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3203 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3204 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 3205 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3206 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3207 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 3208 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 3209 //PCTL_SLICE1_RENG_EXECUTE 3210 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 3211 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 3212 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 3213 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 3214 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 3215 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 3216 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 3217 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 3218 //PCTL_UTCL2_RENG_RAM_INDEX 3219 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3220 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 3221 //PCTL_UTCL2_RENG_RAM_DATA 3222 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3223 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3224 //PCTL_SLICE0_RENG_RAM_INDEX 3225 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3226 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 3227 //PCTL_SLICE0_RENG_RAM_DATA 3228 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3229 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3230 //PCTL_SLICE1_RENG_RAM_INDEX 3231 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 3232 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 3233 //PCTL_SLICE1_RENG_RAM_DATA 3234 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 3235 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 3236 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 3237 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3238 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3239 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3240 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3241 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 3242 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3243 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3244 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3245 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3246 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 3247 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3248 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3249 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3250 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3251 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 3252 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3253 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3254 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3255 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3256 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 3257 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3258 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3259 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3260 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3261 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 3262 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3263 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3264 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3265 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3266 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 3267 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3268 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3269 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3270 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3271 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 3272 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3273 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3274 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3275 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3276 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 3277 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3278 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3279 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3280 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3281 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 3282 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3283 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3284 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3285 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3286 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 3287 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3288 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3289 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3290 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3291 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 3292 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3293 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3294 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3295 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3296 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 3297 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3298 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3299 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3300 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3301 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 3302 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3303 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3304 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3305 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3306 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 3307 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3308 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3309 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3310 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3311 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 3312 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3313 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3314 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3315 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3316 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 3317 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3318 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3319 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3320 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3321 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 3322 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3323 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3324 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3325 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3326 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 3327 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 3328 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 3329 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 3330 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 3331 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 3332 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 3333 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 3334 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 3335 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 3336 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 3337 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 3338 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 3339 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 3340 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 3341 //PCTL_STATUS 3342 #define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 3343 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 3344 #define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 3345 #define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 3346 #define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 3347 #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 3348 #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 3349 #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf 3350 #define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 3351 #define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 3352 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 3353 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 3354 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 3355 #define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L 3356 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L 3357 #define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L 3358 #define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L 3359 #define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L 3360 #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L 3361 #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L 3362 #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L 3363 #define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L 3364 #define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L 3365 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L 3366 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L 3367 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L 3368 //PCTL_PERFCOUNTER_LO 3369 #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3370 #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3371 //PCTL_PERFCOUNTER_HI 3372 #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3373 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3374 #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3375 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3376 //PCTL_PERFCOUNTER0_CFG 3377 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3378 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3379 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3380 #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3381 #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3382 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3383 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3384 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3385 #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3386 #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3387 //PCTL_PERFCOUNTER1_CFG 3388 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3389 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3390 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3391 #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3392 #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3393 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3394 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3395 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3396 #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3397 #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3398 //PCTL_PERFCOUNTER_RSLT_CNTL 3399 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3400 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3401 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3402 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3403 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3404 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3405 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3406 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3407 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3408 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3409 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3410 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3411 //PCTL_RESERVED_0 3412 #define PCTL_RESERVED_0__WORD__SHIFT 0x0 3413 #define PCTL_RESERVED_0__BYTE__SHIFT 0x10 3414 #define PCTL_RESERVED_0__BIT7__SHIFT 0x18 3415 #define PCTL_RESERVED_0__BIT6__SHIFT 0x19 3416 #define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 3417 #define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 3418 #define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 3419 #define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 3420 #define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 3421 #define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 3422 #define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 3423 #define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 3424 #define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 3425 #define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 3426 #define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 3427 #define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 3428 #define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 3429 #define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 3430 #define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 3431 #define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 3432 //PCTL_RESERVED_1 3433 #define PCTL_RESERVED_1__WORD__SHIFT 0x0 3434 #define PCTL_RESERVED_1__BYTE__SHIFT 0x10 3435 #define PCTL_RESERVED_1__BIT7__SHIFT 0x18 3436 #define PCTL_RESERVED_1__BIT6__SHIFT 0x19 3437 #define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 3438 #define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 3439 #define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 3440 #define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 3441 #define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 3442 #define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 3443 #define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 3444 #define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 3445 #define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 3446 #define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 3447 #define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 3448 #define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 3449 #define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 3450 #define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 3451 #define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 3452 #define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 3453 //PCTL_RESERVED_2 3454 #define PCTL_RESERVED_2__WORD__SHIFT 0x0 3455 #define PCTL_RESERVED_2__BYTE__SHIFT 0x10 3456 #define PCTL_RESERVED_2__BIT7__SHIFT 0x18 3457 #define PCTL_RESERVED_2__BIT6__SHIFT 0x19 3458 #define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 3459 #define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 3460 #define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 3461 #define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 3462 #define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 3463 #define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 3464 #define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 3465 #define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 3466 #define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 3467 #define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 3468 #define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 3469 #define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 3470 #define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 3471 #define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 3472 #define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 3473 #define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 3474 //PCTL_RESERVED_3 3475 #define PCTL_RESERVED_3__WORD__SHIFT 0x0 3476 #define PCTL_RESERVED_3__BYTE__SHIFT 0x10 3477 #define PCTL_RESERVED_3__BIT7__SHIFT 0x18 3478 #define PCTL_RESERVED_3__BIT6__SHIFT 0x19 3479 #define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 3480 #define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 3481 #define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 3482 #define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 3483 #define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 3484 #define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 3485 #define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 3486 #define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 3487 #define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 3488 #define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 3489 #define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 3490 #define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 3491 #define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 3492 #define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 3493 #define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 3494 #define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 3495 3496 3497 // addressBlock: mmhub_l1tlb_mmutcl1pfdec 3498 //MMMC_VM_MX_L1_TLB0_STATUS 3499 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 3500 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3501 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3502 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 3503 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3504 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3505 //MMMC_VM_MX_L1_TLB1_STATUS 3506 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 3507 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3508 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3509 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 3510 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3511 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3512 //MMMC_VM_MX_L1_TLB2_STATUS 3513 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 3514 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3515 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3516 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 3517 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3518 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3519 //MMMC_VM_MX_L1_TLB3_STATUS 3520 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 3521 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3522 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3523 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 3524 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3525 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3526 //MMMC_VM_MX_L1_TLB4_STATUS 3527 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 3528 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3529 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3530 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 3531 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3532 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3533 //MMMC_VM_MX_L1_TLB5_STATUS 3534 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 3535 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3536 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3537 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 3538 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3539 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3540 //MMMC_VM_MX_L1_TLB6_STATUS 3541 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 3542 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3543 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3544 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 3545 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3546 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3547 //MMMC_VM_MX_L1_TLB7_STATUS 3548 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 3549 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 3550 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 3551 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 3552 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 3553 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 3554 3555 3556 // addressBlock: mmhub_l1tlb_mmutcl1pldec 3557 //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 3558 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3559 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3560 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3561 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3562 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3563 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3564 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3565 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3566 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3567 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3568 //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 3569 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3570 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3571 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3572 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3573 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3574 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3575 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3576 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3577 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3578 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3579 //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 3580 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3581 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3582 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3583 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3584 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3585 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3586 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3587 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3588 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3589 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3590 //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 3591 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 3592 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 3593 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 3594 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 3595 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 3596 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 3597 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 3598 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 3599 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 3600 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 3601 //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 3602 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3603 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3604 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3605 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3606 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3607 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3608 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3609 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3610 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3611 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3612 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3613 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3614 3615 3616 // addressBlock: mmhub_l1tlb_mmutcl1prdec 3617 //MMMC_VM_MX_L1_PERFCOUNTER_LO 3618 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3619 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3620 //MMMC_VM_MX_L1_PERFCOUNTER_HI 3621 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3622 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3623 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3624 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3625 3626 3627 // addressBlock: mmhub_l1tlb_mmvmtlspfdec 3628 #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x4 3629 #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x5 3630 #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000010L 3631 #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000020L 3632 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 3633 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 3634 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc 3635 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 3636 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 3637 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 3638 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000FFL 3639 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x001FF000L 3640 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L 3641 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1E000000L 3642 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000L 3643 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 3644 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 3645 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 3646 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 3647 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 3648 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 3649 //MMVM_L2_SAW_CNTL 3650 #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 3651 #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 3652 #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 3653 #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 3654 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 3655 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 3656 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 3657 #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 3658 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 3659 #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 3660 #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 3661 #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 3662 #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 3663 #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 3664 #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 3665 #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 3666 #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 3667 #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 3668 #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 3669 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 3670 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 3671 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 3672 #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 3673 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 3674 #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 3675 #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 3676 #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 3677 #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 3678 #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L 3679 #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 3680 //MMVM_L2_SAW_CNTL2 3681 #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 3682 #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 3683 #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 3684 #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 3685 #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 3686 #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 3687 #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 3688 #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 3689 #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 3690 #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 3691 #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 3692 #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 3693 #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 3694 #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 3695 //MMVM_L2_SAW_CNTL3 3696 #define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 3697 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 3698 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 3699 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 3700 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 3701 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 3702 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 3703 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 3704 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 3705 #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 3706 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 3707 #define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL 3708 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 3709 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 3710 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 3711 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 3712 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 3713 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 3714 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 3715 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 3716 #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 3717 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 3718 //MMVM_L2_SAW_CNTL4 3719 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 3720 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 3721 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 3722 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 3723 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 3724 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 3725 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 3726 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 3727 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 3728 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 3729 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 3730 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 3731 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 3732 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 3733 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 3734 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 3735 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L 3736 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L 3737 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L 3738 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L 3739 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L 3740 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L 3741 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L 3742 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L 3743 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L 3744 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L 3745 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L 3746 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L 3747 //MMVM_L2_SAW_CONTEXT0_CNTL 3748 #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 3749 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 3750 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 3751 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 3752 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 3753 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 3754 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 3755 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 3756 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 3757 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 3758 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 3759 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 3760 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 3761 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 3762 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 3763 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 3764 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 3765 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 3766 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 3767 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 3768 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 3769 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 3770 #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 3771 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 3772 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 3773 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 3774 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 3775 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 3776 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 3777 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 3778 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 3779 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 3780 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 3781 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 3782 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 3783 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 3784 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 3785 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 3786 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 3787 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 3788 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 3789 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 3790 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 3791 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L 3792 //MMVM_L2_SAW_CONTEXT0_CNTL2 3793 #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 3794 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 3795 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 3796 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 3797 #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 3798 #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 3799 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 3800 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 3801 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 3802 #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 3803 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 3804 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 3805 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 3806 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 3807 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 3808 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 3809 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 3810 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 3811 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 3812 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 3813 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 3814 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 3815 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 3816 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 3817 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 3818 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 3819 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 3820 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 3821 //MMVM_L2_SAW_CONTEXTS_DISABLE 3822 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 3823 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 3824 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 3825 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 3826 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 3827 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 3828 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 3829 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 3830 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 3831 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 3832 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 3833 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 3834 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 3835 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 3836 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 3837 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 3838 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 3839 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 3840 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 3841 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 3842 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 3843 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 3844 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 3845 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 3846 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 3847 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 3848 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 3849 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 3850 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 3851 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 3852 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 3853 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 3854 //MMVM_L2_SAW_PIPES_BUSY_LO32 3855 #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT 0x0 3856 #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL 3857 //MMVM_L2_SAW_PIPES_BUSY_HI32 3858 #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT 0x0 3859 #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL 3860 //MMVM_L2_SAW_PIPES_BUSY_1_LO32 3861 #define MMVM_L2_SAW_PIPES_BUSY_1_LO32__PIPES_BUSY_LO32__SHIFT 0x0 3862 #define MMVM_L2_SAW_PIPES_BUSY_1_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL 3863 //MMVM_L2_SAW_PIPES_BUSY_1_HI32 3864 #define MMVM_L2_SAW_PIPES_BUSY_1_HI32__PIPES_BUSY_HI32__SHIFT 0x0 3865 #define MMVM_L2_SAW_PIPES_BUSY_1_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL 3866 3867 3868 // addressBlock: mmhub_mmutcl2_mmatcl2dec 3869 //MM_ATC_L2_CNTL 3870 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 3871 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 3872 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 3873 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 3874 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 3875 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 3876 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 3877 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 3878 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 3879 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 3880 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 3881 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 3882 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 3883 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 3884 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 3885 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 3886 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 3887 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 3888 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 3889 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 3890 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 3891 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 3892 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L 3893 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L 3894 //MM_ATC_L2_CNTL2 3895 #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 3896 #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 3897 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 3898 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb 3899 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc 3900 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf 3901 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 3902 #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 3903 #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L 3904 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L 3905 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L 3906 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L 3907 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L 3908 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L 3909 //MM_ATC_L2_CACHE_DATA0 3910 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 3911 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 3912 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 3913 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 3914 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 3915 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 3916 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 3917 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 3918 //MM_ATC_L2_CACHE_DATA1 3919 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 3920 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 3921 //MM_ATC_L2_CACHE_DATA2 3922 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 3923 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 3924 //MM_ATC_L2_CNTL3 3925 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 3926 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 3927 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 3928 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 3929 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 3930 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b 3931 #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e 3932 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 3933 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 3934 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 3935 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L 3936 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L 3937 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L 3938 #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L 3939 //MM_ATC_L2_CNTL4 3940 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 3941 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 3942 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 3943 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 3944 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 3945 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 3946 //MM_ATC_L2_CNTL5 3947 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 3948 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 3949 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 3950 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 3951 //MM_ATC_L2_MM_GROUP_RT_CLASSES 3952 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 3953 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 3954 //MM_ATC_L2_STATUS 3955 #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 3956 #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 3957 #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 3958 #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L 3959 //MM_ATC_L2_STATUS2 3960 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 3961 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 3962 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 3963 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 3964 //MM_ATC_L2_MISC_CG 3965 #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 3966 #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 3967 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 3968 #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 3969 #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 3970 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 3971 //MM_ATC_L2_MEM_POWER_LS 3972 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 3973 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 3974 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 3975 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 3976 //MM_ATC_L2_CGTT_CLK_CTRL 3977 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3978 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 3979 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 3980 #define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 3981 #define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 3982 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 3983 #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 3984 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 3985 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 3986 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 3987 #define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 3988 #define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 3989 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 3990 #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 3991 //MM_ATC_L2_SDPPORT_CTRL 3992 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 3993 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 3994 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 3995 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 3996 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 3997 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 3998 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 3999 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 4000 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 4001 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 4002 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 4003 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 4004 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 4005 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 4006 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 4007 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 4008 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 4009 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 4010 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 4011 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 4012 4013 4014 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4015 //MMVM_L2_CNTL 4016 #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4017 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4018 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4019 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4020 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4021 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4022 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4023 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4024 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4025 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4026 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4027 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4028 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4029 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4030 #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4031 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4032 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4033 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4034 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4035 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4036 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4037 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4038 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4039 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4040 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4041 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4042 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4043 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4044 //MMVM_L2_CNTL2 4045 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4046 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4047 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4048 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4049 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4050 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4051 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4052 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4053 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4054 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4055 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4056 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4057 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4058 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4059 //MMVM_L2_CNTL3 4060 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4061 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4062 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4063 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4064 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4065 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4066 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4067 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4068 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4069 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4070 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4071 #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4072 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4073 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4074 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4075 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4076 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4077 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4078 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4079 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4080 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4081 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4082 //MMVM_L2_STATUS 4083 #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4084 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4085 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4086 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4087 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4088 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 4089 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 4090 #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 4091 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 4092 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 4093 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 4094 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 4095 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 4096 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 4097 //MMVM_DUMMY_PAGE_FAULT_CNTL 4098 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 4099 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 4100 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 4101 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 4102 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 4103 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 4104 //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 4105 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 4106 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4107 //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 4108 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 4109 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 4110 //MMVM_INVALIDATE_CNTL 4111 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 4112 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 4113 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 4114 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 4115 //MMVM_L2_PROTECTION_FAULT_CNTL 4116 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4117 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 4118 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 4119 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 4120 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4121 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 4122 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 4123 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4124 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 4125 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 4126 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4127 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 4128 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4129 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 4130 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 4131 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 4132 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 4133 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4134 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 4135 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 4136 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 4137 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4138 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 4139 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 4140 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4141 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 4142 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 4143 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4144 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 4145 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4146 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 4147 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 4148 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 4149 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 4150 //MMVM_L2_PROTECTION_FAULT_CNTL2 4151 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 4152 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 4153 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 4154 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 4155 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 4156 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 4157 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 4158 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 4159 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 4160 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 4161 //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 4162 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4163 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4164 //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 4165 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4166 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4167 //MMVM_L2_PROTECTION_FAULT_STATUS 4168 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 4169 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 4170 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 4171 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 4172 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 4173 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 4174 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 4175 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 4176 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 4177 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 4178 #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d 4179 #define MMVM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e 4180 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 4181 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 4182 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 4183 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 4184 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 4185 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 4186 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 4187 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 4188 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 4189 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 4190 #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L 4191 #define MMVM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L 4192 //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 4193 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4194 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4195 //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 4196 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4197 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4198 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 4199 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 4200 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4201 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 4202 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 4203 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4204 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 4205 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4206 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4207 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 4208 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4209 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4210 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 4211 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4212 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4213 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 4214 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4215 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4216 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 4217 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 4218 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 4219 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 4220 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 4221 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 4222 //MMVM_L2_CNTL4 4223 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4224 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4225 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 4226 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 4227 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 4228 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 4229 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 4230 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 4231 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f 4232 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4233 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4234 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 4235 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 4236 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 4237 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 4238 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 4239 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 4240 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L 4241 //MMVM_L2_MM_GROUP_RT_CLASSES 4242 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 4243 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 4244 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 4245 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 4246 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 4247 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 4248 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 4249 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 4250 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 4251 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 4252 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 4253 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 4254 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 4255 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 4256 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 4257 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 4258 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 4259 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 4260 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 4261 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 4262 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 4263 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 4264 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 4265 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 4266 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 4267 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 4268 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 4269 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 4270 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 4271 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 4272 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 4273 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 4274 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 4275 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 4276 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 4277 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 4278 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 4279 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 4280 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 4281 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 4282 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 4283 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 4284 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 4285 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 4286 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 4287 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 4288 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 4289 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 4290 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 4291 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 4292 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 4293 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 4294 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 4295 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 4296 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 4297 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 4298 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 4299 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 4300 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 4301 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 4302 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 4303 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 4304 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 4305 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 4306 //MMVM_L2_BANK_SELECT_RESERVED_CID 4307 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4308 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4309 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 4310 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4311 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4312 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4313 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4314 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4315 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 4316 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4317 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4318 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4319 //MMVM_L2_BANK_SELECT_RESERVED_CID2 4320 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 4321 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 4322 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 4323 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 4324 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 4325 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 4326 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 4327 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 4328 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 4329 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 4330 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 4331 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 4332 //MMVM_L2_CACHE_PARITY_CNTL 4333 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 4334 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 4335 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 4336 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 4337 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 4338 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 4339 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 4340 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 4341 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 4342 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 4343 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 4344 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 4345 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 4346 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 4347 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 4348 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 4349 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 4350 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 4351 //MMVM_L2_CGTT_CLK_CTRL 4352 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4353 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4354 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4355 #define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 4356 #define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 4357 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4358 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4359 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4360 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4361 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 4362 #define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 4363 #define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 4364 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4365 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4366 //MMVM_L2_CNTL5 4367 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 4368 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 4369 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe 4370 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf 4371 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 4372 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 4373 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 4374 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 4375 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L 4376 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L 4377 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L 4378 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L 4379 //MMVM_L2_GCR_CNTL 4380 #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 4381 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 4382 #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 4383 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 4384 //MMVM_L2_CGTT_BUSY_CTRL 4385 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 4386 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 4387 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 4388 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 4389 //MMVM_L2_PTE_CACHE_DUMP_CNTL 4390 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 4391 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 4392 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 4393 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 4394 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 4395 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 4396 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 4397 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 4398 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 4399 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 4400 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 4401 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 4402 //MMVM_L2_PTE_CACHE_DUMP_READ 4403 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 4404 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 4405 //MMVM_L2_BANK_SELECT_MASKS 4406 #define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 4407 #define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 4408 #define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 4409 #define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc 4410 #define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL 4411 #define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L 4412 #define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L 4413 #define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L 4414 //MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 4415 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 4416 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa 4417 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL 4418 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L 4419 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 4420 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 4421 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa 4422 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL 4423 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L 4424 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 4425 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 4426 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa 4427 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL 4428 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L 4429 //MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 4430 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 4431 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa 4432 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL 4433 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L 4434 //MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 4435 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 4436 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa 4437 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 4438 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L 4439 4440 4441 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 4442 //MMVM_CONTEXT0_CNTL 4443 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4444 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4445 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4446 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4447 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4448 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4449 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4450 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4451 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4452 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4453 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4454 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4455 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4456 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4457 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4458 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4459 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4460 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4461 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4462 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4463 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4464 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4465 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4466 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4467 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4468 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4469 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4470 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4471 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4472 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4473 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4474 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4475 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4476 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4477 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4478 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4479 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4480 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4481 //MMVM_CONTEXT1_CNTL 4482 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4483 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4484 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4485 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4486 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4487 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4488 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4489 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4490 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4491 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4492 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4493 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4494 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4495 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4496 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4497 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4498 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4499 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4500 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4501 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4502 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4503 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4504 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4505 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4506 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4507 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4508 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4509 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4510 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4511 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4512 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4513 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4514 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4515 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4516 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4517 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4518 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4519 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4520 //MMVM_CONTEXT2_CNTL 4521 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4522 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4523 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4524 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4525 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4526 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4527 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4528 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4529 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4530 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4531 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4532 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4533 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4534 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4535 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4536 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4537 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4538 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4539 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4540 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4541 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4542 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4543 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4544 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4545 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4546 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4547 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4548 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4549 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4550 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4551 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4552 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4553 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4554 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4555 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4556 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4557 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4558 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4559 //MMVM_CONTEXT3_CNTL 4560 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4561 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4562 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4563 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4564 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4565 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4566 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4567 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4568 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4569 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4570 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4571 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4572 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4573 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4574 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4575 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4576 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4577 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4578 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4579 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4580 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4581 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4582 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4583 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4584 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4585 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4586 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4587 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4588 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4589 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4590 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4591 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4592 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4593 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4594 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4595 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4596 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4597 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4598 //MMVM_CONTEXT4_CNTL 4599 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4600 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4601 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4602 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4603 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4604 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4605 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4606 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4607 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4608 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4609 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4610 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4611 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4612 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4613 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4614 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4615 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4616 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4617 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4618 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4619 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4620 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4621 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4622 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4623 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4624 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4625 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4626 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4627 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4628 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4629 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4630 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4631 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4632 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4633 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4634 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4635 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4636 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4637 //MMVM_CONTEXT5_CNTL 4638 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4639 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4640 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4641 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4642 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4643 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4644 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4645 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4646 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4647 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4648 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4649 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4650 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4651 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4652 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4653 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4654 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4655 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4656 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4657 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4658 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4659 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4660 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4661 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4662 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4663 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4664 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4665 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4666 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4667 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4668 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4669 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4670 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4671 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4672 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4673 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4674 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4675 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4676 //MMVM_CONTEXT6_CNTL 4677 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4678 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4679 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4680 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4681 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4682 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4683 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4684 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4685 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4686 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4687 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4688 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4689 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4690 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4691 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4692 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4693 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4694 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4695 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4696 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4697 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4698 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4699 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4700 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4701 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4702 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4703 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4704 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4705 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4706 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4707 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4708 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4709 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4710 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4711 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4712 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4713 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4714 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4715 //MMVM_CONTEXT7_CNTL 4716 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4717 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4718 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4719 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4720 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4721 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4722 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4723 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4724 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4725 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4726 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4727 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4728 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4729 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4730 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4731 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4732 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4733 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4734 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4735 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4736 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4737 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4738 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4739 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4740 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4741 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4742 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4743 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4744 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4745 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4746 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4747 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4748 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4749 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4750 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4751 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4752 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4753 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4754 //MMVM_CONTEXT8_CNTL 4755 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4756 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4757 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4758 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4759 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4760 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4761 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4762 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4763 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4764 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4765 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4766 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4767 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4768 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4769 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4770 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4771 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4772 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4773 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4774 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4775 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4776 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4777 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4778 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4779 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4780 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4781 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4782 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4783 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4784 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4785 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4786 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4787 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4788 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4789 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4790 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4791 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4792 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4793 //MMVM_CONTEXT9_CNTL 4794 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4795 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4796 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4797 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4798 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4799 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4800 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4801 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4802 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4803 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4804 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4805 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4806 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4807 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4808 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4809 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4810 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4811 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4812 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4813 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4814 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4815 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4816 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4817 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4818 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4819 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4820 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4821 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4822 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4823 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4824 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4825 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4826 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4827 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4828 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4829 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4830 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4831 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4832 //MMVM_CONTEXT10_CNTL 4833 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4834 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4835 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4836 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4837 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4838 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4839 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4840 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4841 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4842 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4843 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4844 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4845 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4846 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4847 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4848 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4849 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4850 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4851 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4852 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4853 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4854 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4855 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4856 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4857 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4858 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4859 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4860 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4861 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4862 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4863 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4864 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4865 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4866 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4867 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4868 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4869 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4870 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4871 //MMVM_CONTEXT11_CNTL 4872 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4873 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4874 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4875 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4876 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4877 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4878 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4879 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4880 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4881 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4882 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4883 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4884 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4885 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4886 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4887 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4888 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4889 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4890 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4891 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4892 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4893 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4894 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4895 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4896 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4897 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4898 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4899 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4900 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4901 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4902 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4903 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4904 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4905 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4906 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4907 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4908 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4909 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4910 //MMVM_CONTEXT12_CNTL 4911 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4912 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4913 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4914 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4915 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4916 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4917 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4918 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4919 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4920 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4921 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4922 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4923 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4924 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4925 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4926 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4927 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4928 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4929 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4930 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4931 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4932 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4933 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4934 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4935 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4936 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4937 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4938 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4939 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4940 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4941 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4942 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4943 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4944 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4945 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4946 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4947 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4948 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4949 //MMVM_CONTEXT13_CNTL 4950 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4951 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4952 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4953 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4954 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4955 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4956 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4957 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4958 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4959 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4960 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 4961 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 4962 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 4963 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 4964 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 4965 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 4966 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 4967 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 4968 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 4969 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 4970 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 4971 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 4972 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 4973 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 4974 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 4975 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4976 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 4977 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4978 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 4979 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 4980 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 4981 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 4982 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 4983 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 4984 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 4985 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 4986 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 4987 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 4988 //MMVM_CONTEXT14_CNTL 4989 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 4990 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 4991 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 4992 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 4993 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 4994 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 4995 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4996 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 4997 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4998 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 4999 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5000 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5001 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5002 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5003 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5004 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5005 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5006 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5007 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5008 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5009 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5010 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5011 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5012 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5013 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5014 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5015 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5016 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5017 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5018 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5019 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5020 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5021 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5022 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5023 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5024 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5025 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5026 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5027 //MMVM_CONTEXT15_CNTL 5028 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5029 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5030 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5031 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5032 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5033 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5034 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5035 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5036 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5037 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5038 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5039 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5040 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5041 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5042 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5043 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5044 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5045 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5046 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5047 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5048 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5049 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5050 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5051 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5052 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5053 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5054 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5055 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5056 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5057 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5058 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5059 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5060 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5061 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5062 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5063 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5064 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5065 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5066 //MMVM_CONTEXTS_DISABLE 5067 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5068 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5069 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5070 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5071 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5072 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5073 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5074 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5075 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5076 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5077 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5078 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5079 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5080 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5081 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5082 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5083 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5084 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5085 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5086 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5087 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5088 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5089 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5090 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5091 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5092 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5093 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5094 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5095 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5096 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5097 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5098 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5099 //MMVM_INVALIDATE_ENG0_SEM 5100 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5101 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5102 //MMVM_INVALIDATE_ENG1_SEM 5103 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5104 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5105 //MMVM_INVALIDATE_ENG2_SEM 5106 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5107 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5108 //MMVM_INVALIDATE_ENG3_SEM 5109 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5110 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5111 //MMVM_INVALIDATE_ENG4_SEM 5112 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5113 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5114 //MMVM_INVALIDATE_ENG5_SEM 5115 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5116 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5117 //MMVM_INVALIDATE_ENG6_SEM 5118 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5119 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5120 //MMVM_INVALIDATE_ENG7_SEM 5121 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5122 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5123 //MMVM_INVALIDATE_ENG8_SEM 5124 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5125 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5126 //MMVM_INVALIDATE_ENG9_SEM 5127 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5128 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5129 //MMVM_INVALIDATE_ENG10_SEM 5130 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5131 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5132 //MMVM_INVALIDATE_ENG11_SEM 5133 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5134 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5135 //MMVM_INVALIDATE_ENG12_SEM 5136 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5137 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 5138 //MMVM_INVALIDATE_ENG13_SEM 5139 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 5140 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 5141 //MMVM_INVALIDATE_ENG14_SEM 5142 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 5143 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 5144 //MMVM_INVALIDATE_ENG15_SEM 5145 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 5146 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 5147 //MMVM_INVALIDATE_ENG16_SEM 5148 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 5149 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 5150 //MMVM_INVALIDATE_ENG17_SEM 5151 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 5152 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 5153 //MMVM_INVALIDATE_ENG0_REQ 5154 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5155 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 5156 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5157 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5158 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5159 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5160 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5161 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5162 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5163 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5164 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 5165 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5166 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5167 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5168 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5169 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5170 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5171 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5172 //MMVM_INVALIDATE_ENG1_REQ 5173 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5174 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 5175 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5176 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5177 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5178 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5179 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5180 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5181 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5182 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5183 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 5184 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5185 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5186 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5187 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5188 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5189 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5190 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5191 //MMVM_INVALIDATE_ENG2_REQ 5192 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5193 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 5194 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5195 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5196 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5197 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5198 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5199 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5200 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5201 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5202 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 5203 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5204 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5205 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5206 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5207 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5208 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5209 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5210 //MMVM_INVALIDATE_ENG3_REQ 5211 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5212 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 5213 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5214 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5215 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5216 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5217 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5218 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5219 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5220 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5221 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 5222 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5223 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5224 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5225 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5226 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5227 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5228 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5229 //MMVM_INVALIDATE_ENG4_REQ 5230 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5231 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 5232 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5233 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5234 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5235 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5236 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5237 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5238 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5239 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5240 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 5241 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5242 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5243 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5244 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5245 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5246 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5247 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5248 //MMVM_INVALIDATE_ENG5_REQ 5249 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5250 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 5251 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5252 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5253 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5254 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5255 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5256 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5257 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5258 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5259 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 5260 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5261 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5262 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5263 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5264 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5265 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5266 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5267 //MMVM_INVALIDATE_ENG6_REQ 5268 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5269 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 5270 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5271 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5272 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5273 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5274 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5275 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5276 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5277 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5278 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 5279 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5280 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5281 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5282 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5283 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5284 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5285 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5286 //MMVM_INVALIDATE_ENG7_REQ 5287 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5288 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 5289 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5290 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5291 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5292 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5293 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5294 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5295 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5296 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5297 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 5298 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5299 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5300 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5301 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5302 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5303 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5304 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5305 //MMVM_INVALIDATE_ENG8_REQ 5306 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5307 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 5308 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5309 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5310 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5311 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5312 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5313 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5314 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5315 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5316 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 5317 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5318 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5319 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5320 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5321 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5322 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5323 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5324 //MMVM_INVALIDATE_ENG9_REQ 5325 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5326 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 5327 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5328 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5329 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5330 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5331 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5332 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5333 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5334 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5335 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 5336 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5337 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5338 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5339 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5340 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5341 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5342 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5343 //MMVM_INVALIDATE_ENG10_REQ 5344 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5345 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 5346 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5347 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5348 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5349 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5350 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5351 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5352 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5353 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5354 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 5355 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5356 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5357 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5358 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5359 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5360 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5361 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5362 //MMVM_INVALIDATE_ENG11_REQ 5363 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5364 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 5365 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5366 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5367 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5368 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5369 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5370 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5371 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5372 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5373 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 5374 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5375 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5376 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5377 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5378 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5379 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5380 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5381 //MMVM_INVALIDATE_ENG12_REQ 5382 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5383 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 5384 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5385 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5386 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5387 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5388 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5389 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5390 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5391 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5392 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 5393 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5394 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5395 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5396 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5397 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5398 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5399 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5400 //MMVM_INVALIDATE_ENG13_REQ 5401 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5402 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 5403 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5404 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5405 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5406 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5407 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5408 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5409 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5410 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5411 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 5412 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5413 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5414 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5415 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5416 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5417 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5418 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5419 //MMVM_INVALIDATE_ENG14_REQ 5420 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5421 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 5422 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5423 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5424 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5425 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5426 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5427 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5428 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5429 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5430 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 5431 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5432 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5433 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5434 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5435 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5436 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5437 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5438 //MMVM_INVALIDATE_ENG15_REQ 5439 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5440 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 5441 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5442 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5443 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5444 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5445 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5446 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5447 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5448 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5449 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 5450 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5451 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5452 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5453 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5454 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5455 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5456 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5457 //MMVM_INVALIDATE_ENG16_REQ 5458 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5459 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 5460 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5461 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5462 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5463 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5464 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5465 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5466 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5467 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5468 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 5469 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5470 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5471 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5472 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5473 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5474 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5475 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5476 //MMVM_INVALIDATE_ENG17_REQ 5477 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5478 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 5479 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5480 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5481 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5482 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5483 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5484 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5485 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5486 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5487 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 5488 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5489 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5490 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5491 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5492 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5493 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5494 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5495 //MMVM_INVALIDATE_ENG0_ACK 5496 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5497 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 5498 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5499 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 5500 //MMVM_INVALIDATE_ENG1_ACK 5501 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5502 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 5503 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5504 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 5505 //MMVM_INVALIDATE_ENG2_ACK 5506 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5507 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 5508 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5509 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 5510 //MMVM_INVALIDATE_ENG3_ACK 5511 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5512 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 5513 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5514 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 5515 //MMVM_INVALIDATE_ENG4_ACK 5516 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5517 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 5518 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5519 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 5520 //MMVM_INVALIDATE_ENG5_ACK 5521 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5522 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 5523 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5524 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 5525 //MMVM_INVALIDATE_ENG6_ACK 5526 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5527 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 5528 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5529 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 5530 //MMVM_INVALIDATE_ENG7_ACK 5531 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5532 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 5533 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5534 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 5535 //MMVM_INVALIDATE_ENG8_ACK 5536 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5537 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 5538 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5539 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 5540 //MMVM_INVALIDATE_ENG9_ACK 5541 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5542 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 5543 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5544 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 5545 //MMVM_INVALIDATE_ENG10_ACK 5546 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5547 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 5548 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5549 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 5550 //MMVM_INVALIDATE_ENG11_ACK 5551 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5552 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 5553 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5554 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 5555 //MMVM_INVALIDATE_ENG12_ACK 5556 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5557 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 5558 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5559 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 5560 //MMVM_INVALIDATE_ENG13_ACK 5561 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5562 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 5563 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5564 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 5565 //MMVM_INVALIDATE_ENG14_ACK 5566 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5567 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 5568 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5569 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 5570 //MMVM_INVALIDATE_ENG15_ACK 5571 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5572 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 5573 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5574 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 5575 //MMVM_INVALIDATE_ENG16_ACK 5576 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5577 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 5578 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5579 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 5580 //MMVM_INVALIDATE_ENG17_ACK 5581 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 5582 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 5583 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 5584 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 5585 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 5586 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5587 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5588 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5589 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5590 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 5591 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5592 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5593 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 5594 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5595 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5596 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5597 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5598 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 5599 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5600 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5601 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 5602 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5603 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5604 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5605 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5606 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 5607 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5608 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5609 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 5610 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5611 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5612 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5613 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5614 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 5615 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5616 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5617 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 5618 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5619 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5620 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5621 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5622 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 5623 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5624 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5625 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 5626 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5627 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5628 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5629 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5630 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 5631 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5632 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5633 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 5634 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5635 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5636 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5637 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5638 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 5639 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5640 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5641 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 5642 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5643 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5644 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5645 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5646 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 5647 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5648 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5649 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 5650 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5651 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5652 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5653 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5654 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 5655 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5656 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5657 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 5658 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5659 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5660 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5661 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5662 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 5663 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5664 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5665 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 5666 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5667 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5668 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5669 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5670 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 5671 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5672 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5673 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 5674 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5675 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5676 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5677 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5678 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 5679 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5680 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5681 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 5682 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5683 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5684 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5685 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5686 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 5687 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5688 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5689 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 5690 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5691 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5692 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5693 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5694 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 5695 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5696 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5697 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 5698 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5699 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5700 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5701 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5702 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 5703 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5704 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5705 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 5706 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5707 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5708 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5709 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5710 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 5711 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5712 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5713 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 5714 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5715 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5716 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5717 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5718 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 5719 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5720 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5721 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 5722 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 5723 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 5724 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 5725 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 5726 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 5727 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 5728 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 5729 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 5730 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5731 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5732 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 5733 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5734 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5735 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 5736 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5737 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5738 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 5739 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5740 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5741 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 5742 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5743 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5744 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 5745 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5746 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5747 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 5748 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5749 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5750 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 5751 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5752 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5753 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 5754 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5755 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5756 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 5757 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5758 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5759 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 5760 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5761 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5762 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 5763 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5764 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5765 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 5766 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5767 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5768 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 5769 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5770 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5771 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 5772 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5773 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5774 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 5775 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5776 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5777 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 5778 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5779 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5780 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 5781 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5782 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5783 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 5784 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5785 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5786 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 5787 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5788 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5789 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 5790 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5791 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5792 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 5793 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5794 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5795 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 5796 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5797 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5798 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 5799 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5800 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5801 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 5802 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5803 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5804 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 5805 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5806 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5807 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 5808 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5809 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5810 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 5811 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5812 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5813 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 5814 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5815 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5816 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 5817 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5818 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5819 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 5820 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 5821 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 5822 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 5823 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 5824 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 5825 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 5826 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5827 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5828 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 5829 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5830 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5831 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 5832 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5833 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5834 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 5835 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5836 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5837 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 5838 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5839 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5840 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 5841 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5842 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5843 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 5844 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5845 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5846 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 5847 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5848 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5849 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 5850 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5851 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5852 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 5853 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5854 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5855 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 5856 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5857 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5858 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 5859 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5860 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5861 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 5862 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5863 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5864 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 5865 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5866 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5867 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 5868 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5869 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5870 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 5871 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5872 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5873 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 5874 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5875 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5876 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 5877 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5878 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5879 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 5880 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5881 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5882 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 5883 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5884 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5885 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 5886 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5887 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5888 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 5889 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5890 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5891 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 5892 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5893 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5894 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 5895 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5896 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5897 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 5898 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5899 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5900 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 5901 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5902 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5903 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 5904 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5905 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5906 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 5907 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5908 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5909 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 5910 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5911 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5912 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 5913 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5914 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5915 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 5916 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5917 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5918 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 5919 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5920 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5921 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 5922 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5923 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5924 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 5925 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5926 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5927 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 5928 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5929 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5930 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 5931 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5932 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5933 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 5934 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5935 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5936 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 5937 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5938 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5939 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 5940 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5941 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5942 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 5943 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5944 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5945 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 5946 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5947 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5948 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 5949 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5950 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5951 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 5952 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5953 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5954 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 5955 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5956 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5957 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 5958 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5959 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5960 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 5961 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5962 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5963 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 5964 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5965 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5966 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 5967 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5968 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5969 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 5970 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5971 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5972 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 5973 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5974 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5975 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 5976 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5977 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5978 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 5979 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5980 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5981 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 5982 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5983 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5984 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 5985 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5986 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5987 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 5988 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5989 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5990 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 5991 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5992 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5993 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 5994 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5995 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5996 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 5997 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5998 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5999 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6000 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6001 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6002 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6003 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6004 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6005 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6006 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6007 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6008 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6009 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6010 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6011 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6012 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6013 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6014 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6015 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6016 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6017 //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6018 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6019 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6020 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6021 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6022 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6023 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6024 //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6025 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6026 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6027 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6028 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6029 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6030 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6031 //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6032 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6033 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6034 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6035 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6036 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6037 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6038 //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6039 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6040 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6041 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6042 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6043 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6044 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6045 //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6046 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6047 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6048 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6049 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6050 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6051 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6052 //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6053 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6054 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6055 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6056 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6057 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6058 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6059 //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6060 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6061 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6062 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6063 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6064 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6065 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6066 //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6067 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6068 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6069 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6070 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6071 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6072 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6073 //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6074 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6075 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6076 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6077 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6078 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6079 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6080 //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6081 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6082 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6083 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6084 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6085 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6086 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6087 //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6088 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6089 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6090 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6091 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6092 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6093 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6094 //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6095 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6096 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6097 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6098 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6099 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6100 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6101 //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6102 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6103 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6104 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6105 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6106 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6107 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6108 //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6109 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6110 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6111 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6112 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6113 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6114 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6115 //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6116 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6117 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6118 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6119 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6120 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6121 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6122 //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6123 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6124 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6125 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6126 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6127 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6128 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6129 //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6130 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6131 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6132 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6133 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6134 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6135 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6136 6137 6138 // addressBlock: mmhub_mmutcl2_mmvml2pldec 6139 //MMMC_VM_L2_PERFCOUNTER0_CFG 6140 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6141 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6142 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6143 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6144 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6145 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6146 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6147 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6148 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6149 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6150 //MMMC_VM_L2_PERFCOUNTER1_CFG 6151 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6152 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6153 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6154 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6155 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6156 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6157 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6158 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6159 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6160 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6161 //MMMC_VM_L2_PERFCOUNTER2_CFG 6162 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6163 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6164 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6165 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6166 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6167 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6168 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6169 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6170 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6171 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6172 //MMMC_VM_L2_PERFCOUNTER3_CFG 6173 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6174 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6175 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6176 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6177 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6178 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6179 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6180 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6181 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6182 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6183 //MMMC_VM_L2_PERFCOUNTER4_CFG 6184 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6185 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6186 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6187 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6188 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6189 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6190 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6191 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6192 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6193 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6194 //MMMC_VM_L2_PERFCOUNTER5_CFG 6195 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6196 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6197 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6198 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6199 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6200 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6201 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6202 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6203 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6204 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6205 //MMMC_VM_L2_PERFCOUNTER6_CFG 6206 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6207 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6208 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6209 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6210 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6211 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6212 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6213 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6214 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6215 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6216 //MMMC_VM_L2_PERFCOUNTER7_CFG 6217 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 6218 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 6219 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 6220 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 6221 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 6222 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 6223 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 6224 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 6225 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 6226 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 6227 //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 6228 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6229 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6230 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6231 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6232 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6233 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6234 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6235 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6236 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6237 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6238 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6239 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6240 //MMUTCL2_PERFCOUNTER0_CFG 6241 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6242 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6243 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6244 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6245 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6246 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6247 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6248 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6249 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6250 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6251 //MMUTCL2_PERFCOUNTER1_CFG 6252 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6253 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6254 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6255 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6256 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6257 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6258 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6259 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6260 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6261 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6262 //MMUTCL2_PERFCOUNTER2_CFG 6263 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6264 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6265 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6266 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6267 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6268 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6269 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6270 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6271 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6272 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6273 //MMUTCL2_PERFCOUNTER3_CFG 6274 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6275 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6276 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6277 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6278 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6279 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6280 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6281 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6282 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6283 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6284 //MMUTCL2_PERFCOUNTER_RSLT_CNTL 6285 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6286 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6287 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6288 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6289 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6290 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6291 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6292 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6293 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6294 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6295 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6296 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6297 6298 6299 // addressBlock: mmhub_mmutcl2_mmvml2prdec 6300 //MMMC_VM_L2_PERFCOUNTER_LO 6301 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6302 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6303 //MMMC_VM_L2_PERFCOUNTER_HI 6304 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6305 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6306 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6307 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6308 //MMUTCL2_PERFCOUNTER_LO 6309 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6310 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6311 //MMUTCL2_PERFCOUNTER_HI 6312 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6313 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6314 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6315 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6316 6317 6318 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 6319 //MMVM_PCIE_ATS_CNTL 6320 #define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 6321 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 6322 #define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 6323 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 6324 6325 6326 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 6327 //MMMC_VM_NB_MMIOBASE 6328 #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 6329 #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 6330 //MMMC_VM_NB_MMIOLIMIT 6331 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 6332 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 6333 //MMMC_VM_NB_PCI_CTRL 6334 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 6335 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 6336 //MMMC_VM_NB_PCI_ARB 6337 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 6338 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 6339 //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 6340 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 6341 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 6342 //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 6343 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 6344 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 6345 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 6346 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 6347 //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 6348 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 6349 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 6350 //MMMC_VM_FB_OFFSET 6351 #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 6352 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 6353 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 6354 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 6355 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 6356 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 6357 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 6358 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 6359 //MMMC_VM_STEERING 6360 #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 6361 #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 6362 //MMMC_SHARED_VIRT_RESET_REQ 6363 #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 6364 #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 6365 #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 6366 #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 6367 //MMMC_MEM_POWER_LS 6368 #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 6369 #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 6370 #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 6371 #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 6372 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 6373 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 6374 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 6375 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 6376 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 6377 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 6378 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_START 6379 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 6380 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 6381 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_END 6382 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 6383 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 6384 //MMMC_VM_APT_CNTL 6385 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 6386 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 6387 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 6388 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 6389 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 6390 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 6391 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 6392 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 6393 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 6394 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L 6395 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L 6396 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L 6397 //MMMC_VM_LOCAL_FB_ADDRESS_START 6398 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 6399 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 6400 //MMMC_VM_LOCAL_FB_ADDRESS_END 6401 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 6402 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 6403 //MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 6404 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 6405 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 6406 //MMUTCL2_CGTT_CLK_CTRL 6407 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6408 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 6409 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 6410 #define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a 6411 #define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d 6412 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 6413 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 6414 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 6415 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 6416 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L 6417 #define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L 6418 #define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L 6419 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 6420 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 6421 //MMMC_SHARED_ACTIVE_FCN_ID 6422 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 6423 #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1e 6424 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 6425 #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x40000000L 6426 //MMUTCL2_CGTT_BUSY_CTRL 6427 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 6428 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 6429 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 6430 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 6431 //MMMC_VM_FB_NOALLOC_CNTL 6432 #define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 6433 #define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 6434 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x2 6435 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x3 6436 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x4 6437 #define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L 6438 #define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L 6439 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000004L 6440 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000008L 6441 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000010L 6442 //MMUTCL2_HARVEST_BYPASS_GROUPS 6443 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 6444 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 6445 //MMUTCL2_GROUP_RET_FAULT_STATUS 6446 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 6447 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL 6448 6449 6450 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 6451 //MMMC_VM_FB_LOCATION_BASE 6452 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 6453 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 6454 //MMMC_VM_FB_LOCATION_TOP 6455 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 6456 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 6457 //MMMC_VM_AGP_TOP 6458 #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 6459 #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 6460 //MMMC_VM_AGP_BOT 6461 #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 6462 #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 6463 //MMMC_VM_AGP_BASE 6464 #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 6465 #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 6466 //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 6467 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 6468 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 6469 //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 6470 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 6471 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 6472 //MMMC_VM_MX_L1_TLB_CNTL 6473 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 6474 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 6475 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 6476 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 6477 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 6478 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 6479 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 6480 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 6481 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 6482 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 6483 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 6484 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 6485 6486 6487 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 6488 //MM_ATC_L2_PERFCOUNTER_LO 6489 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6490 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6491 //MM_ATC_L2_PERFCOUNTER_HI 6492 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6493 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6494 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6495 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6496 6497 6498 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 6499 //MM_ATC_L2_PERFCOUNTER0_CFG 6500 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6501 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6502 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6503 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6504 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6505 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6506 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6507 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6508 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6509 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6510 //MM_ATC_L2_PERFCOUNTER1_CFG 6511 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6512 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6513 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6514 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6515 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6516 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6517 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6518 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6519 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6520 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6521 //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 6522 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6523 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6524 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6525 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6526 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6527 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6528 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6529 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6530 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6531 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6532 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6533 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6534 6535 6536 // addressBlock: mmhub_mmutcl2_mmvml2pspdec 6537 //MMUTCL2_TRANSLATION_BYPASS_BY_VMID 6538 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 6539 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 6540 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL 6541 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L 6542 //MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 6543 #define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 6544 #define MMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L 6545 //MMVM_IOMMU_CONTROL_REGISTER 6546 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 6547 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 6548 //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 6549 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 6550 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 6551 //MMUTC_TRANSLATION_FAULT_CNTL0 6552 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 6553 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL 6554 //MMUTC_TRANSLATION_FAULT_CNTL1 6555 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 6556 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 6557 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 6558 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 6559 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL 6560 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L 6561 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L 6562 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L 6563 //MMUTCL2_VSCH_POWER_STATUS 6564 #define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN__SHIFT 0x0 6565 #define MMUTCL2_VSCH_POWER_STATUS__POWERED_DOWN_MASK 0x00000001L 6566 6567 6568 // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 6569 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 6570 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 6571 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L 6572 6573 6574 // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 6575 //MM_ATC_L2_IOV_MODE_CNTL 6576 #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0 6577 #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L 6578 6579 6580 // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 6581 //MML2TLB_TLB0_STATUS 6582 #define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 6583 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 6584 #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 6585 #define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L 6586 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 6587 #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 6588 //MML2TLB_TMZ_CNTL 6589 #define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 6590 #define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L 6591 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 6592 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 6593 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL 6594 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 6595 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 6596 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 6597 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 6598 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc 6599 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd 6600 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf 6601 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 6602 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 6603 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 6604 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e 6605 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL 6606 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L 6607 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L 6608 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L 6609 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L 6610 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L 6611 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L 6612 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L 6613 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L 6614 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L 6615 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 6616 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 6617 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL 6618 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 6619 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 6620 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 6621 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 6622 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd 6623 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe 6624 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf 6625 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 6626 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 6627 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 6628 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 6629 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 6630 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 6631 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f 6632 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL 6633 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L 6634 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L 6635 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L 6636 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L 6637 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L 6638 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L 6639 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L 6640 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L 6641 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L 6642 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L 6643 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L 6644 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L 6645 //MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 6646 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 6647 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa 6648 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 6649 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L 6650 6651 6652 // addressBlock: mmhub_mmutcl2_mml2tlbpldec 6653 //MML2TLB_PERFCOUNTER0_CFG 6654 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6655 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6656 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6657 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6658 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6659 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6660 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6661 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6662 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6663 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6664 //MML2TLB_PERFCOUNTER1_CFG 6665 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6666 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6667 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6668 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6669 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6670 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6671 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6672 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6673 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6674 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6675 //MML2TLB_PERFCOUNTER2_CFG 6676 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6677 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6678 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6679 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6680 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6681 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6682 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6683 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6684 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6685 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6686 //MML2TLB_PERFCOUNTER3_CFG 6687 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6688 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6689 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6690 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6691 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6692 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6693 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6694 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6695 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6696 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6697 //MML2TLB_PERFCOUNTER_RSLT_CNTL 6698 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6699 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6700 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6701 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6702 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6703 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6704 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6705 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6706 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6707 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6708 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6709 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6710 6711 6712 // addressBlock: mmhub_mmutcl2_mml2tlbprdec 6713 //MML2TLB_PERFCOUNTER_LO 6714 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6715 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6716 //MML2TLB_PERFCOUNTER_HI 6717 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6718 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6719 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6720 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6721 6722 #endif 6723