1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44 #include "lib/devcom.h"
45
46 extern uint mlx5_core_debug_mask;
47
48 #define mlx5_core_dbg(__dev, format, ...) \
49 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
50 __func__, __LINE__, current->pid, \
51 ##__VA_ARGS__)
52
53 #define mlx5_core_dbg_once(__dev, format, ...) \
54 dev_dbg_once((__dev)->device, \
55 "%s:%d:(pid %d): " format, \
56 __func__, __LINE__, current->pid, \
57 ##__VA_ARGS__)
58
59 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
60 do { \
61 if ((mask) & mlx5_core_debug_mask) \
62 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
63 } while (0)
64
65 #define mlx5_core_err(__dev, format, ...) \
66 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
67 __func__, __LINE__, current->pid, \
68 ##__VA_ARGS__)
69
70 #define mlx5_core_err_rl(__dev, format, ...) \
71 dev_err_ratelimited((__dev)->device, \
72 "%s:%d:(pid %d): " format, \
73 __func__, __LINE__, current->pid, \
74 ##__VA_ARGS__)
75
76 #define mlx5_core_warn(__dev, format, ...) \
77 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
78 __func__, __LINE__, current->pid, \
79 ##__VA_ARGS__)
80
81 #define mlx5_core_warn_once(__dev, format, ...) \
82 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
83 __func__, __LINE__, current->pid, \
84 ##__VA_ARGS__)
85
86 #define mlx5_core_warn_rl(__dev, format, ...) \
87 dev_warn_ratelimited((__dev)->device, \
88 "%s:%d:(pid %d): " format, \
89 __func__, __LINE__, current->pid, \
90 ##__VA_ARGS__)
91
92 #define mlx5_core_info(__dev, format, ...) \
93 dev_info((__dev)->device, format, ##__VA_ARGS__)
94
95 #define mlx5_core_info_rl(__dev, format, ...) \
96 dev_info_ratelimited((__dev)->device, \
97 "%s:%d:(pid %d): " format, \
98 __func__, __LINE__, current->pid, \
99 ##__VA_ARGS__)
100
101 #define ACCESS_KEY_LEN 32
102 #define FT_ID_FT_TYPE_OFFSET 24
103
104 struct mlx5_cmd_allow_other_vhca_access_attr {
105 u16 obj_type;
106 u32 obj_id;
107 u8 access_key[ACCESS_KEY_LEN];
108 };
109
110 struct mlx5_cmd_alias_obj_create_attr {
111 u32 obj_id;
112 u16 vhca_id;
113 u16 obj_type;
114 u8 access_key[ACCESS_KEY_LEN];
115 };
116
mlx5_printk(struct mlx5_core_dev * dev,int level,const char * format,...)117 static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...)
118 {
119 struct device *device = dev->device;
120 struct va_format vaf;
121 va_list args;
122
123 if (WARN_ONCE(level < LOGLEVEL_EMERG || level > LOGLEVEL_DEBUG,
124 "Level %d is out of range, set to default level\n", level))
125 level = LOGLEVEL_DEFAULT;
126
127 va_start(args, format);
128 vaf.fmt = format;
129 vaf.va = &args;
130
131 dev_printk_emit(level, device, "%s %s: %pV", dev_driver_string(device), dev_name(device),
132 &vaf);
133 va_end(args);
134 }
135
136 #define mlx5_log(__dev, level, format, ...) \
137 mlx5_printk(__dev, level, "%s:%d:(pid %d): " format, \
138 __func__, __LINE__, current->pid, \
139 ##__VA_ARGS__)
140
mlx5_core_dma_dev(struct mlx5_core_dev * dev)141 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
142 {
143 return &dev->pdev->dev;
144 }
145
146 enum {
147 MLX5_CMD_DATA, /* print command payload only */
148 MLX5_CMD_TIME, /* print command execution time */
149 };
150
151 enum {
152 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
153 MLX5_DRIVER_SYND = 0xbadd00de,
154 };
155
156 enum mlx5_semaphore_space_address {
157 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
158 MLX5_SEMAPHORE_SW_RESET = 0x20,
159 };
160
161 #define MLX5_DEFAULT_PROF 2
162 #define MLX5_SF_PROF 3
163 #define MLX5_NUM_FW_CMD_THREADS 8
164 #define MLX5_DEV_MAX_WQS MLX5_NUM_FW_CMD_THREADS
165
mlx5_flexible_inlen(struct mlx5_core_dev * dev,size_t fixed,size_t item_size,size_t num_items,const char * func,int line)166 static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed,
167 size_t item_size, size_t num_items,
168 const char *func, int line)
169 {
170 int inlen;
171
172 if (fixed > INT_MAX || item_size > INT_MAX || num_items > INT_MAX) {
173 mlx5_core_err(dev, "%s: %s:%d: input values too big: %zu + %zu * %zu\n",
174 __func__, func, line, fixed, item_size, num_items);
175 return -ENOMEM;
176 }
177
178 if (check_mul_overflow((int)item_size, (int)num_items, &inlen)) {
179 mlx5_core_err(dev, "%s: %s:%d: multiplication overflow: %zu + %zu * %zu\n",
180 __func__, func, line, fixed, item_size, num_items);
181 return -ENOMEM;
182 }
183
184 if (check_add_overflow((int)fixed, inlen, &inlen)) {
185 mlx5_core_err(dev, "%s: %s:%d: addition overflow: %zu + %zu * %zu\n",
186 __func__, func, line, fixed, item_size, num_items);
187 return -ENOMEM;
188 }
189
190 return inlen;
191 }
192
193 #define MLX5_FLEXIBLE_INLEN(dev, fixed, item_size, num_items) \
194 mlx5_flexible_inlen(dev, fixed, item_size, num_items, __func__, __LINE__)
195
196 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
197 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
198 enum mlx5_cap_mode cap_mode);
199 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
200 int mlx5_query_board_id(struct mlx5_core_dev *dev);
201 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
202 int mlx5_cmd_init(struct mlx5_core_dev *dev);
203 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
204 int mlx5_cmd_enable(struct mlx5_core_dev *dev);
205 void mlx5_cmd_disable(struct mlx5_core_dev *dev);
206 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
207 enum mlx5_cmdif_state cmdif_state);
208 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id);
209 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
210 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
211 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
212 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
213 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
214 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
215 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
216 void mlx5_disable_device(struct mlx5_core_dev *dev);
217 int mlx5_recover_device(struct mlx5_core_dev *dev);
218 int mlx5_sriov_init(struct mlx5_core_dev *dev);
219 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
220 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
221 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
222 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
223 void mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change);
224 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
225 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
226 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
227 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
228 void *context, u32 *element_id);
229 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
230 void *context, u32 element_id,
231 u32 modify_bitmask);
232 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
233 u32 element_id);
234 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
235
236 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
237 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
238 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
239
240 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
241 u8 access_reg_group);
242 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
243 u8 access_reg_group);
244 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
245 u8 feature_group, u8 access_reg_group);
246 int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir);
247
248 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
249 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
250 void mlx5_lag_add_mdev(struct mlx5_core_dev *dev);
251 void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev);
252 void mlx5_lag_disable_change(struct mlx5_core_dev *dev);
253 void mlx5_lag_enable_change(struct mlx5_core_dev *dev);
254
255 int mlx5_events_init(struct mlx5_core_dev *dev);
256 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
257 void mlx5_events_start(struct mlx5_core_dev *dev);
258 void mlx5_events_stop(struct mlx5_core_dev *dev);
259
260 int mlx5_adev_idx_alloc(void);
261 void mlx5_adev_idx_free(int idx);
262 void mlx5_adev_cleanup(struct mlx5_core_dev *dev);
263 int mlx5_adev_init(struct mlx5_core_dev *dev);
264
265 int mlx5_attach_device(struct mlx5_core_dev *dev);
266 void mlx5_detach_device(struct mlx5_core_dev *dev, bool suspend);
267 int mlx5_register_device(struct mlx5_core_dev *dev);
268 void mlx5_unregister_device(struct mlx5_core_dev *dev);
269 void mlx5_dev_set_lightweight(struct mlx5_core_dev *dev);
270 bool mlx5_dev_is_lightweight(struct mlx5_core_dev *dev);
271
272 void mlx5_fw_reporters_create(struct mlx5_core_dev *dev);
273 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
274 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
275 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
276 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
277
278 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
279 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
280
281 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
282 MLX5_CAP_GEN((mdev), pps_modify) && \
283 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
284 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
285
286 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
287 struct netlink_ext_ack *extack);
288 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
289 u32 *running_ver, u32 *stored_ver);
290
291 #ifdef CONFIG_MLX5_CORE_EN
292 int mlx5e_init(void);
293 void mlx5e_cleanup(void);
294 #else
mlx5e_init(void)295 static inline int mlx5e_init(void){ return 0; }
mlx5e_cleanup(void)296 static inline void mlx5e_cleanup(void){}
297 #endif
298
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)299 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
300 {
301 return pci_num_vf(dev->pdev) ? true : false;
302 }
303
304 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev);
mlx5_rescan_drivers(struct mlx5_core_dev * dev)305 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev)
306 {
307 int ret;
308
309 mlx5_devcom_comp_lock(dev->priv.hca_devcom_comp);
310 ret = mlx5_rescan_drivers_locked(dev);
311 mlx5_devcom_comp_unlock(dev->priv.hca_devcom_comp);
312 return ret;
313 }
314
315 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
316 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
317
mlx5_core_is_sf(const struct mlx5_core_dev * dev)318 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev)
319 {
320 return dev->coredev_type == MLX5_COREDEV_SF;
321 }
322
323 static inline struct auxiliary_device *
mlx5_sf_coredev_to_adev(struct mlx5_core_dev * mdev)324 mlx5_sf_coredev_to_adev(struct mlx5_core_dev *mdev)
325 {
326 return container_of(mdev->device, struct auxiliary_device, dev);
327 }
328
329 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx);
330 void mlx5_mdev_uninit(struct mlx5_core_dev *dev);
331 int mlx5_init_one(struct mlx5_core_dev *dev);
332 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev);
333 void mlx5_uninit_one(struct mlx5_core_dev *dev);
334 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend);
335 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend);
336 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery);
337 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery);
338 int mlx5_init_one_light(struct mlx5_core_dev *dev);
339 void mlx5_uninit_one_light(struct mlx5_core_dev *dev);
340 void mlx5_unload_one_light(struct mlx5_core_dev *dev);
341
342 int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *hca_cap, u16 vport,
343 u16 opmod);
344 #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \
345 mlx5_vport_get_other_func_cap(dev, vport, out, MLX5_CAP_GENERAL)
346
mlx5_sriov_get_vf_total_msix(struct pci_dev * pdev)347 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev)
348 {
349 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
350
351 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
352 }
353
354 bool mlx5_eth_supported(struct mlx5_core_dev *dev);
355 bool mlx5_rdma_supported(struct mlx5_core_dev *dev);
356 bool mlx5_vnet_supported(struct mlx5_core_dev *dev);
357 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev);
358 int mlx5_cmd_allow_other_vhca_access(struct mlx5_core_dev *dev,
359 struct mlx5_cmd_allow_other_vhca_access_attr *attr);
360 int mlx5_cmd_alias_obj_create(struct mlx5_core_dev *dev,
361 struct mlx5_cmd_alias_obj_create_attr *alias_attr,
362 u32 *obj_id);
363 int mlx5_cmd_alias_obj_destroy(struct mlx5_core_dev *dev, u32 obj_id, u16 obj_type);
364
mlx5_core_ec_vf_vport_base(const struct mlx5_core_dev * dev)365 static inline u16 mlx5_core_ec_vf_vport_base(const struct mlx5_core_dev *dev)
366 {
367 return MLX5_CAP_GEN_2(dev, ec_vf_vport_base);
368 }
369
mlx5_core_ec_sriov_enabled(const struct mlx5_core_dev * dev)370 static inline u16 mlx5_core_ec_sriov_enabled(const struct mlx5_core_dev *dev)
371 {
372 return mlx5_core_is_ecpf(dev) && mlx5_core_ec_vf_vport_base(dev);
373 }
374
mlx5_core_is_ec_vf_vport(const struct mlx5_core_dev * dev,u16 vport_num)375 static inline bool mlx5_core_is_ec_vf_vport(const struct mlx5_core_dev *dev, u16 vport_num)
376 {
377 int base_vport = mlx5_core_ec_vf_vport_base(dev);
378 int max_vport = base_vport + mlx5_core_max_ec_vfs(dev);
379
380 if (!mlx5_core_ec_sriov_enabled(dev))
381 return false;
382
383 return (vport_num >= base_vport && vport_num < max_vport);
384 }
385
mlx5_vport_to_func_id(const struct mlx5_core_dev * dev,u16 vport,bool ec_vf_func)386 static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vport, bool ec_vf_func)
387 {
388 return ec_vf_func ? vport - mlx5_core_ec_vf_vport_base(dev) + 1
389 : vport;
390 }
391
mlx5_max_eq_cap_get(const struct mlx5_core_dev * dev)392 static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev)
393 {
394 if (MLX5_CAP_GEN_2(dev, max_num_eqs_24b))
395 return MLX5_CAP_GEN_2(dev, max_num_eqs_24b);
396
397 if (MLX5_CAP_GEN(dev, max_num_eqs))
398 return MLX5_CAP_GEN(dev, max_num_eqs);
399
400 return 1 << MLX5_CAP_GEN(dev, log_max_eq);
401 }
402 #endif /* __MLX5_CORE_H__ */
403