xref: /linux/arch/arm/boot/dts/amlogic/meson8b.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include <dt-bindings/clock/meson8-ddr-clkc.h>
8#include <dt-bindings/clock/meson8b-clkc.h>
9#include <dt-bindings/gpio/meson8b-gpio.h>
10#include <dt-bindings/power/meson8-power.h>
11#include <dt-bindings/reset/amlogic,meson8b-reset.h>
12#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13#include <dt-bindings/thermal/thermal.h>
14#include "meson.dtsi"
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@200 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a5";
24			next-level-cache = <&L2>;
25			reg = <0x200>;
26			enable-method = "amlogic,meson8b-smp";
27			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
28			operating-points-v2 = <&cpu_opp_table>;
29			clocks = <&clkc CLKID_CPUCLK>;
30			#cooling-cells = <2>; /* min followed by max */
31		};
32
33		cpu1: cpu@201 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a5";
36			next-level-cache = <&L2>;
37			reg = <0x201>;
38			enable-method = "amlogic,meson8b-smp";
39			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
40			operating-points-v2 = <&cpu_opp_table>;
41			clocks = <&clkc CLKID_CPUCLK>;
42			#cooling-cells = <2>; /* min followed by max */
43		};
44
45		cpu2: cpu@202 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a5";
48			next-level-cache = <&L2>;
49			reg = <0x202>;
50			enable-method = "amlogic,meson8b-smp";
51			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52			operating-points-v2 = <&cpu_opp_table>;
53			clocks = <&clkc CLKID_CPUCLK>;
54			#cooling-cells = <2>; /* min followed by max */
55		};
56
57		cpu3: cpu@203 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a5";
60			next-level-cache = <&L2>;
61			reg = <0x203>;
62			enable-method = "amlogic,meson8b-smp";
63			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
64			operating-points-v2 = <&cpu_opp_table>;
65			clocks = <&clkc CLKID_CPUCLK>;
66			#cooling-cells = <2>; /* min followed by max */
67		};
68	};
69
70	cpu_opp_table: opp-table {
71		compatible = "operating-points-v2";
72		opp-shared;
73
74		opp-96000000 {
75			opp-hz = /bits/ 64 <96000000>;
76			opp-microvolt = <860000>;
77		};
78		opp-192000000 {
79			opp-hz = /bits/ 64 <192000000>;
80			opp-microvolt = <860000>;
81		};
82		opp-312000000 {
83			opp-hz = /bits/ 64 <312000000>;
84			opp-microvolt = <860000>;
85		};
86		opp-408000000 {
87			opp-hz = /bits/ 64 <408000000>;
88			opp-microvolt = <860000>;
89		};
90		opp-504000000 {
91			opp-hz = /bits/ 64 <504000000>;
92			opp-microvolt = <860000>;
93		};
94		opp-600000000 {
95			opp-hz = /bits/ 64 <600000000>;
96			opp-microvolt = <860000>;
97		};
98		opp-720000000 {
99			opp-hz = /bits/ 64 <720000000>;
100			opp-microvolt = <860000>;
101		};
102		opp-816000000 {
103			opp-hz = /bits/ 64 <816000000>;
104			opp-microvolt = <900000>;
105		};
106		opp-1008000000 {
107			opp-hz = /bits/ 64 <1008000000>;
108			opp-microvolt = <1140000>;
109		};
110		opp-1200000000 {
111			opp-hz = /bits/ 64 <1200000000>;
112			opp-microvolt = <1140000>;
113		};
114		opp-1320000000 {
115			opp-hz = /bits/ 64 <1320000000>;
116			opp-microvolt = <1140000>;
117		};
118		opp-1488000000 {
119			opp-hz = /bits/ 64 <1488000000>;
120			opp-microvolt = <1140000>;
121		};
122		opp-1536000000 {
123			opp-hz = /bits/ 64 <1536000000>;
124			opp-microvolt = <1140000>;
125		};
126	};
127
128	gpu_opp_table: opp-table-gpu {
129		compatible = "operating-points-v2";
130
131		opp-255000000 {
132			opp-hz = /bits/ 64 <255000000>;
133			opp-microvolt = <1100000>;
134		};
135		opp-364285714 {
136			opp-hz = /bits/ 64 <364285714>;
137			opp-microvolt = <1100000>;
138		};
139		opp-425000000 {
140			opp-hz = /bits/ 64 <425000000>;
141			opp-microvolt = <1100000>;
142		};
143		opp-510000000 {
144			opp-hz = /bits/ 64 <510000000>;
145			opp-microvolt = <1100000>;
146		};
147		opp-637500000 {
148			opp-hz = /bits/ 64 <637500000>;
149			opp-microvolt = <1100000>;
150			turbo-mode;
151		};
152	};
153
154	pmu {
155		compatible = "arm,cortex-a5-pmu";
156		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
157			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
158			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
159			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
160		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
161	};
162
163	reserved-memory {
164		#address-cells = <1>;
165		#size-cells = <1>;
166		ranges;
167
168		/* 2 MiB reserved for Hardware ROM Firmware? */
169		hwrom@0 {
170			reg = <0x0 0x200000>;
171			no-map;
172		};
173	};
174
175	thermal-zones {
176		soc-thermal {
177			polling-delay-passive = <250>; /* milliseconds */
178			polling-delay = <1000>; /* milliseconds */
179			thermal-sensors = <&thermal_sensor>;
180
181			cooling-maps {
182				map0 {
183					trip = <&soc_passive>;
184					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189				};
190
191				map1 {
192					trip = <&soc_hot>;
193					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
195							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
198				};
199			};
200
201			trips {
202				soc_passive: soc-passive {
203					temperature = <80000>; /* millicelsius */
204					hysteresis = <2000>; /* millicelsius */
205					type = "passive";
206				};
207
208				soc_hot: soc-hot {
209					temperature = <90000>; /* millicelsius */
210					hysteresis = <2000>; /* millicelsius */
211					type = "hot";
212				};
213
214				soc_critical: soc-critical {
215					temperature = <110000>; /* millicelsius */
216					hysteresis = <2000>; /* millicelsius */
217					type = "critical";
218				};
219			};
220		};
221	};
222
223	mmcbus: bus@c8000000 {
224		compatible = "simple-bus";
225		reg = <0xc8000000 0x8000>;
226		#address-cells = <1>;
227		#size-cells = <1>;
228		ranges = <0x0 0xc8000000 0x8000>;
229
230		ddr_clkc: clock-controller@400 {
231			compatible = "amlogic,meson8b-ddr-clkc";
232			reg = <0x400 0x20>;
233			clocks = <&xtal>;
234			clock-names = "xtal";
235			#clock-cells = <1>;
236		};
237
238		dmcbus: bus@6000 {
239			compatible = "simple-bus";
240			reg = <0x6000 0x400>;
241			#address-cells = <1>;
242			#size-cells = <1>;
243			ranges = <0x0 0x6000 0x400>;
244
245			canvas: video-lut@48 {
246				compatible = "amlogic,meson8b-canvas",
247					     "amlogic,canvas";
248				reg = <0x48 0x14>;
249			};
250		};
251	};
252
253	apb: bus@d0000000 {
254		compatible = "simple-bus";
255		reg = <0xd0000000 0x200000>;
256		#address-cells = <1>;
257		#size-cells = <1>;
258		ranges = <0x0 0xd0000000 0x200000>;
259
260		mali: gpu@c0000 {
261			compatible = "amlogic,meson8b-mali", "arm,mali-450";
262			reg = <0xc0000 0x40000>;
263			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
264				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
265				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
266				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
267				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
268				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
269				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
270				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
271			interrupt-names = "gp", "gpmmu", "pp", "pmu",
272					  "pp0", "ppmmu0", "pp1", "ppmmu1";
273			resets = <&reset RESET_MALI>;
274			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
275			clock-names = "bus", "core";
276			operating-points-v2 = <&gpu_opp_table>;
277			#cooling-cells = <2>; /* min followed by max */
278		};
279	};
280}; /* end of / */
281
282&aiu {
283	compatible = "amlogic,aiu-meson8b", "amlogic,aiu";
284	clocks = <&clkc CLKID_AIU_GLUE>,
285		 <&clkc CLKID_I2S_OUT>,
286		 <&clkc CLKID_AOCLK_GATE>,
287		 <&clkc CLKID_CTS_AMCLK>,
288		 <&clkc CLKID_MIXER_IFACE>,
289		 <&clkc CLKID_IEC958>,
290		 <&clkc CLKID_IEC958_GATE>,
291		 <&clkc CLKID_CTS_MCLK_I958>,
292		 <&clkc CLKID_CTS_I958>;
293	clock-names = "pclk",
294		      "i2s_pclk",
295		      "i2s_aoclk",
296		      "i2s_mclk",
297		      "i2s_mixer",
298		      "spdif_pclk",
299		      "spdif_aoclk",
300		      "spdif_mclk",
301		      "spdif_mclk_sel";
302	resets = <&reset RESET_AIU>;
303};
304
305&aobus {
306	pmu: pmu@e0 {
307		compatible = "amlogic,meson8b-pmu", "syscon";
308		reg = <0xe0 0x18>;
309	};
310
311	pinctrl_aobus: pinctrl@14 {
312		compatible = "amlogic,meson8b-aobus-pinctrl";
313		#address-cells = <1>;
314		#size-cells = <1>;
315		ranges = <0x0 0x14 0x1c>;
316
317		gpio_ao: bank@0 {
318			reg = <0x0 0x4>,
319			      <0x18 0x4>,
320			      <0x10 0x8>;
321			reg-names = "mux", "pull", "gpio";
322			gpio-controller;
323			#gpio-cells = <2>;
324			gpio-ranges = <&pinctrl_aobus 0 0 16>;
325		};
326
327		i2s_am_clk_pins: i2s-am-clk-out {
328			mux {
329				groups = "i2s_am_clk_out";
330				function = "i2s";
331				bias-disable;
332			};
333		};
334
335		i2s_out_ao_clk_pins: i2s-ao-clk-out {
336			mux {
337				groups = "i2s_ao_clk_out";
338				function = "i2s";
339				bias-disable;
340			};
341		};
342
343		i2s_out_lr_clk_pins: i2s-lr-clk-out {
344			mux {
345				groups = "i2s_lr_clk_out";
346				function = "i2s";
347				bias-disable;
348			};
349		};
350
351		i2s_out_ch01_ao_pins: i2s-out-ch01 {
352			mux {
353				groups = "i2s_out_01";
354				function = "i2s";
355				bias-disable;
356			};
357		};
358
359		spdif_out_1_pins: spdif-out-1 {
360			mux {
361				groups = "spdif_out_1";
362				function = "spdif_1";
363				bias-disable;
364			};
365		};
366
367		uart_ao_a_pins: uart_ao_a {
368			mux {
369				groups = "uart_tx_ao_a", "uart_rx_ao_a";
370				function = "uart_ao";
371				bias-pull-up;
372			};
373		};
374
375		ir_recv_pins: remote {
376			mux {
377				groups = "remote_input";
378				function = "remote";
379				bias-disable;
380			};
381		};
382	};
383};
384
385&ao_arc_rproc {
386	compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
387	amlogic,secbus2 = <&secbus2>;
388	sram = <&ao_arc_sram>;
389	resets = <&reset RESET_MEDIA_CPU>;
390	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
391};
392
393&cbus {
394	reset: reset-controller@4404 {
395		compatible = "amlogic,meson8b-reset";
396		reg = <0x4404 0x9c>;
397		#reset-cells = <1>;
398	};
399
400	analog_top: analog-top@81a8 {
401		compatible = "amlogic,meson8b-analog-top", "syscon";
402		reg = <0x81a8 0x14>;
403	};
404
405	pwm_ef: pwm@86c0 {
406		compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
407		reg = <0x86c0 0x10>;
408		clocks = <&xtal>,
409			 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
410			 <&clkc CLKID_FCLK_DIV4>,
411			 <&clkc CLKID_FCLK_DIV3>;
412		#pwm-cells = <3>;
413		status = "disabled";
414	};
415
416	clock-measure@8758 {
417		compatible = "amlogic,meson8b-clk-measure";
418		reg = <0x8758 0x1c>;
419	};
420
421	pinctrl_cbus: pinctrl@8030 {
422		compatible = "amlogic,meson8b-cbus-pinctrl";
423		#address-cells = <1>;
424		#size-cells = <1>;
425		ranges = <0x0 0x8030 0x108>;
426
427		gpio: bank@80 {
428			reg = <0x80 0x28>,
429			      <0xb8 0x18>,
430			      <0xf0 0x18>,
431			      <0x00 0x38>;
432			reg-names = "mux", "pull", "pull-enable", "gpio";
433			gpio-controller;
434			#gpio-cells = <2>;
435			gpio-ranges = <&pinctrl_cbus 0 0 83>;
436		};
437
438		eth_rgmii_pins: eth-rgmii {
439			mux {
440				groups = "eth_tx_clk",
441					 "eth_tx_en",
442					 "eth_txd1_0",
443					 "eth_txd0_0",
444					 "eth_rx_clk",
445					 "eth_rx_dv",
446					 "eth_rxd1",
447					 "eth_rxd0",
448					 "eth_mdio_en",
449					 "eth_mdc",
450					 "eth_ref_clk",
451					 "eth_txd2",
452					 "eth_txd3",
453					 "eth_rxd3",
454					 "eth_rxd2";
455				function = "ethernet";
456				bias-disable;
457			};
458		};
459
460		eth_rmii_pins: eth-rmii {
461			mux {
462				groups = "eth_tx_en",
463					 "eth_txd1_0",
464					 "eth_txd0_0",
465					 "eth_rx_clk",
466					 "eth_rx_dv",
467					 "eth_rxd1",
468					 "eth_rxd0",
469					 "eth_mdio_en",
470					 "eth_mdc";
471				function = "ethernet";
472				bias-disable;
473			};
474		};
475
476		i2c_a_pins: i2c-a {
477			mux {
478				groups = "i2c_sda_a", "i2c_sck_a";
479				function = "i2c_a";
480				bias-disable;
481			};
482		};
483
484		sd_b_pins: sd-b {
485			mux {
486				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
487					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
488				function = "sd_b";
489				bias-disable;
490			};
491		};
492
493		sdxc_c_pins: sdxc-c {
494			mux {
495				groups = "sdxc_d0_c", "sdxc_d13_c",
496					 "sdxc_d47_c", "sdxc_clk_c",
497					 "sdxc_cmd_c";
498				function = "sdxc_c";
499				bias-pull-up;
500			};
501		};
502
503		pwm_c1_pins: pwm-c1 {
504			mux {
505				groups = "pwm_c1";
506				function = "pwm_c";
507				bias-disable;
508			};
509		};
510
511		pwm_d_pins: pwm-d {
512			mux {
513				groups = "pwm_d";
514				function = "pwm_d";
515				bias-disable;
516			};
517		};
518
519		uart_b0_pins: uart-b0 {
520			mux {
521				groups = "uart_tx_b0",
522				       "uart_rx_b0";
523				function = "uart_b";
524				bias-pull-up;
525			};
526		};
527
528		uart_b0_cts_rts_pins: uart-b0-cts-rts {
529			mux {
530				groups = "uart_cts_b0",
531				       "uart_rts_b0";
532				function = "uart_b";
533				bias-disable;
534			};
535		};
536	};
537};
538
539&ahb_sram {
540	ao_arc_sram: aoarc-sram@0 {
541		compatible = "amlogic,meson8b-ao-arc-sram";
542		reg = <0x0 0x8000>;
543		pool;
544	};
545
546	smp-sram@1ff80 {
547		compatible = "amlogic,meson8b-smp-sram";
548		reg = <0x1ff80 0x8>;
549	};
550};
551
552
553&efuse {
554	compatible = "amlogic,meson8b-efuse";
555	clocks = <&clkc CLKID_EFUSE>;
556	clock-names = "core";
557
558	temperature_calib: calib@1f4 {
559		/* only the upper two bytes are relevant */
560		reg = <0x1f4 0x4>;
561	};
562};
563
564&ethmac {
565	compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
566
567	reg = <0xc9410000 0x10000
568	       0xc1108140 0x4>;
569
570	clocks = <&clkc CLKID_ETH>,
571		 <&clkc CLKID_MPLL2>,
572		 <&clkc CLKID_MPLL2>,
573		 <&clkc CLKID_FCLK_DIV2>;
574	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
575	rx-fifo-depth = <4096>;
576	tx-fifo-depth = <2048>;
577
578	resets = <&reset RESET_ETHERNET>;
579	reset-names = "stmmaceth";
580
581	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
582};
583
584&gpio_intc {
585	compatible = "amlogic,meson8b-gpio-intc",
586		     "amlogic,meson-gpio-intc";
587	status = "okay";
588};
589
590&hhi {
591	clkc: clock-controller {
592		compatible = "amlogic,meson8b-clkc";
593		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
594		clock-names = "xtal", "ddr_pll";
595		#clock-cells = <1>;
596		#reset-cells = <1>;
597	};
598
599	pwrc: power-controller {
600		compatible = "amlogic,meson8b-pwrc";
601		#power-domain-cells = <1>;
602		amlogic,ao-sysctrl = <&pmu>;
603		resets = <&reset RESET_DBLK>,
604			 <&reset RESET_PIC_DC>,
605			 <&reset RESET_HDMI_APB>,
606			 <&reset RESET_HDMI_SYSTEM_RESET>,
607			 <&reset RESET_VENCI>,
608			 <&reset RESET_VENCP>,
609			 <&reset RESET_VDAC_4>,
610			 <&reset RESET_VENCL>,
611			 <&reset RESET_VIU>,
612			 <&reset RESET_VENC>,
613			 <&reset RESET_RDMA>;
614		reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
615			      "venci", "vencp", "vdac", "vencl", "viu",
616			      "venc", "rdma";
617		clocks = <&clkc CLKID_VPU>;
618		clock-names = "vpu";
619		assigned-clocks = <&clkc CLKID_VPU>;
620		assigned-clock-rates = <182142857>;
621	};
622};
623
624&hwrng {
625	clocks = <&clkc CLKID_RNG0>;
626	clock-names = "core";
627};
628
629&i2c_AO {
630	clocks = <&clkc CLKID_CLK81>;
631};
632
633&i2c_A {
634	clocks = <&clkc CLKID_I2C>;
635};
636
637&i2c_B {
638	clocks = <&clkc CLKID_I2C>;
639};
640
641&L2 {
642	arm,data-latency = <3 3 3>;
643	arm,tag-latency = <2 2 2>;
644	arm,filter-ranges = <0x100000 0xc0000000>;
645	prefetch-data = <1>;
646	prefetch-instr = <1>;
647	arm,prefetch-offset = <7>;
648	arm,double-linefill = <1>;
649	arm,prefetch-drop = <1>;
650	arm,shared-override;
651};
652
653&periph {
654	scu@0 {
655		compatible = "arm,cortex-a5-scu";
656		reg = <0x0 0x100>;
657	};
658
659	timer@200 {
660		compatible = "arm,cortex-a5-global-timer";
661		reg = <0x200 0x20>;
662		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
663		clocks = <&clkc CLKID_PERIPH>;
664
665		/*
666		 * the arm_global_timer driver currently does not handle clock
667		 * rate changes. Keep it disabled for now.
668		 */
669		status = "disabled";
670	};
671
672	timer@600 {
673		compatible = "arm,cortex-a5-twd-timer";
674		reg = <0x600 0x20>;
675		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
676		clocks = <&clkc CLKID_PERIPH>;
677	};
678};
679
680&pwm_ab {
681	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
682	clocks = <&xtal>,
683		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
684		 <&clkc CLKID_FCLK_DIV4>,
685		 <&clkc CLKID_FCLK_DIV3>;
686};
687
688&pwm_cd {
689	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
690	clocks = <&xtal>,
691		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
692		 <&clkc CLKID_FCLK_DIV4>,
693		 <&clkc CLKID_FCLK_DIV3>;
694};
695
696&rtc {
697	compatible = "amlogic,meson8b-rtc";
698	resets = <&reset RESET_RTC>;
699};
700
701&saradc {
702	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
703	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
704	clock-names = "clkin", "core";
705	amlogic,hhi-sysctrl = <&hhi>;
706	nvmem-cells = <&temperature_calib>;
707	nvmem-cell-names = "temperature_calib";
708};
709
710&sdhc {
711	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
712	clocks = <&xtal>,
713		 <&clkc CLKID_FCLK_DIV4>,
714		 <&clkc CLKID_FCLK_DIV3>,
715		 <&clkc CLKID_FCLK_DIV5>,
716		 <&clkc CLKID_SDHC>;
717	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
718};
719
720&secbus {
721	secbus2: system-controller@4000 {
722		compatible = "amlogic,meson8b-secbus2", "syscon";
723		reg = <0x4000 0x2000>;
724	};
725};
726
727&sdio {
728	compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
729	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
730	clock-names = "core", "clkin";
731};
732
733&timer_abcde {
734	clocks = <&xtal>, <&clkc CLKID_CLK81>;
735	clock-names = "xtal", "pclk";
736};
737
738&uart_AO {
739	compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
740	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
741	clock-names = "xtal", "pclk", "baud";
742};
743
744&uart_A {
745	compatible = "amlogic,meson8b-uart";
746	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
747	clock-names = "xtal", "pclk", "baud";
748};
749
750&uart_B {
751	compatible = "amlogic,meson8b-uart";
752	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
753	clock-names = "xtal", "pclk", "baud";
754};
755
756&uart_C {
757	compatible = "amlogic,meson8b-uart";
758	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
759	clock-names = "xtal", "pclk", "baud";
760};
761
762&usb0 {
763	compatible = "amlogic,meson8b-usb", "snps,dwc2";
764	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
765	clock-names = "otg";
766};
767
768&usb1 {
769	compatible = "amlogic,meson8b-usb", "snps,dwc2";
770	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
771	clock-names = "otg";
772};
773
774&usb0_phy {
775	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
776	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
777	clock-names = "usb_general", "usb";
778	resets = <&reset RESET_USB_OTG>;
779};
780
781&usb1_phy {
782	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
783	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
784	clock-names = "usb_general", "usb";
785	resets = <&reset RESET_USB_OTG>;
786};
787
788&wdt {
789	compatible = "amlogic,meson8b-wdt";
790};
791