1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h> 13#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sd_emmc_b; /* SD card */ 23 mmc1 = &sd_emmc_c; /* eMMC */ 24 mmc2 = &sd_emmc_a; /* SDIO */ 25 }; 26 27 chosen { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 simplefb_cvbs: framebuffer-cvbs { 33 compatible = "amlogic,simple-framebuffer", 34 "simple-framebuffer"; 35 amlogic,pipeline = "vpu-cvbs"; 36 clocks = <&clkc CLKID_HDMI>, 37 <&clkc CLKID_HTX_PCLK>, 38 <&clkc CLKID_VPU_INTR>; 39 status = "disabled"; 40 }; 41 42 simplefb_hdmi: framebuffer-hdmi { 43 compatible = "amlogic,simple-framebuffer", 44 "simple-framebuffer"; 45 amlogic,pipeline = "vpu-hdmi"; 46 clocks = <&clkc CLKID_HDMI>, 47 <&clkc CLKID_HTX_PCLK>, 48 <&clkc CLKID_VPU_INTR>; 49 status = "disabled"; 50 }; 51 }; 52 53 efuse: efuse { 54 compatible = "amlogic,meson-gxbb-efuse"; 55 clocks = <&clkc CLKID_EFUSE>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 read-only; 59 secure-monitor = <&sm>; 60 }; 61 62 gpu_opp_table: opp-table-gpu { 63 compatible = "operating-points-v2"; 64 65 opp-124999998 { 66 opp-hz = /bits/ 64 <124999998>; 67 opp-microvolt = <800000>; 68 }; 69 opp-249999996 { 70 opp-hz = /bits/ 64 <249999996>; 71 opp-microvolt = <800000>; 72 }; 73 opp-285714281 { 74 opp-hz = /bits/ 64 <285714281>; 75 opp-microvolt = <800000>; 76 }; 77 opp-399999994 { 78 opp-hz = /bits/ 64 <399999994>; 79 opp-microvolt = <800000>; 80 }; 81 opp-499999992 { 82 opp-hz = /bits/ 64 <499999992>; 83 opp-microvolt = <800000>; 84 }; 85 opp-666666656 { 86 opp-hz = /bits/ 64 <666666656>; 87 opp-microvolt = <800000>; 88 }; 89 opp-799999987 { 90 opp-hz = /bits/ 64 <799999987>; 91 opp-microvolt = <800000>; 92 }; 93 }; 94 95 psci { 96 compatible = "arm,psci-1.0"; 97 method = "smc"; 98 }; 99 100 reserved-memory { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 106 secmon_reserved: secmon@5000000 { 107 reg = <0x0 0x05000000 0x0 0x300000>; 108 no-map; 109 }; 110 111 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 112 secmon_reserved_bl32: secmon@5300000 { 113 reg = <0x0 0x05300000 0x0 0x2000000>; 114 no-map; 115 }; 116 117 linux,cma { 118 compatible = "shared-dma-pool"; 119 reusable; 120 size = <0x0 0x10000000>; 121 alignment = <0x0 0x400000>; 122 linux,cma-default; 123 }; 124 }; 125 126 sm: secure-monitor { 127 compatible = "amlogic,meson-gxbb-sm"; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 pcie: pcie@fc000000 { 137 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 138 reg = <0x0 0xfc000000 0x0 0x400000>, 139 <0x0 0xff648000 0x0 0x2000>, 140 <0x0 0xfc400000 0x0 0x200000>; 141 reg-names = "elbi", "cfg", "config"; 142 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 143 #interrupt-cells = <1>; 144 interrupt-map-mask = <0 0 0 0>; 145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146 bus-range = <0x0 0xff>; 147 #address-cells = <3>; 148 #size-cells = <2>; 149 device_type = "pci"; 150 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 151 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 152 153 clocks = <&clkc CLKID_PCIE_PHY 154 &clkc CLKID_PCIE_COMB 155 &clkc CLKID_PCIE_PLL>; 156 clock-names = "general", 157 "pclk", 158 "port"; 159 resets = <&reset RESET_PCIE_CTRL_A>, 160 <&reset RESET_PCIE_APB>; 161 reset-names = "port", 162 "apb"; 163 num-lanes = <1>; 164 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 165 phy-names = "pcie"; 166 status = "disabled"; 167 }; 168 169 ethmac: ethernet@ff3f0000 { 170 compatible = "amlogic,meson-g12a-dwmac", 171 "snps,dwmac-3.70a", 172 "snps,dwmac"; 173 reg = <0x0 0xff3f0000 0x0 0x10000>, 174 <0x0 0xff634540 0x0 0x8>; 175 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "macirq"; 177 clocks = <&clkc CLKID_ETH>, 178 <&clkc CLKID_FCLK_DIV2>, 179 <&clkc CLKID_MPLL2>, 180 <&clkc CLKID_FCLK_DIV2>; 181 clock-names = "stmmaceth", "clkin0", "clkin1", 182 "timing-adjustment"; 183 rx-fifo-depth = <4096>; 184 tx-fifo-depth = <2048>; 185 status = "disabled"; 186 187 mdio0: mdio { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 compatible = "snps,dwmac-mdio"; 191 }; 192 }; 193 194 apb: bus@ff600000 { 195 compatible = "simple-bus"; 196 reg = <0x0 0xff600000 0x0 0x200000>; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 200 201 hdmi_tx: hdmi-tx@0 { 202 compatible = "amlogic,meson-g12a-dw-hdmi"; 203 reg = <0x0 0x0 0x0 0x10000>; 204 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 205 resets = <&reset RESET_HDMITX_CAPB3>, 206 <&reset RESET_HDMITX_PHY>, 207 <&reset RESET_HDMITX>; 208 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 209 clocks = <&clkc CLKID_HDMI>, 210 <&clkc CLKID_HTX_PCLK>, 211 <&clkc CLKID_VPU_INTR>; 212 clock-names = "isfr", "iahb", "venci"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 #sound-dai-cells = <0>; 216 status = "disabled"; 217 218 assigned-clocks = <&clkc CLKID_HDMI_SEL>, 219 <&clkc CLKID_HDMI>; 220 assigned-clock-parents = <&xtal>, <0>; 221 assigned-clock-rates = <0>, <24000000>; 222 223 /* VPU VENC Input */ 224 hdmi_tx_venc_port: port@0 { 225 reg = <0>; 226 227 hdmi_tx_in: endpoint { 228 remote-endpoint = <&hdmi_tx_out>; 229 }; 230 }; 231 232 /* TMDS Output */ 233 hdmi_tx_tmds_port: port@1 { 234 reg = <1>; 235 }; 236 }; 237 238 apb_efuse: bus@30000 { 239 compatible = "simple-bus"; 240 reg = <0x0 0x30000 0x0 0x2000>; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 244 245 hwrng: rng@218 { 246 compatible = "amlogic,meson-rng"; 247 reg = <0x0 0x218 0x0 0x4>; 248 clocks = <&clkc CLKID_RNG0>; 249 clock-names = "core"; 250 }; 251 }; 252 253 acodec: audio-controller@32000 { 254 compatible = "amlogic,t9015"; 255 reg = <0x0 0x32000 0x0 0x14>; 256 #sound-dai-cells = <0>; 257 sound-name-prefix = "ACODEC"; 258 clocks = <&clkc CLKID_AUDIO_CODEC>; 259 clock-names = "pclk"; 260 resets = <&reset RESET_AUDIO_CODEC>; 261 status = "disabled"; 262 }; 263 264 periphs: bus@34400 { 265 compatible = "simple-bus"; 266 reg = <0x0 0x34400 0x0 0x400>; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 270 271 periphs_pinctrl: pinctrl@40 { 272 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 gpio: bank@40 { 278 reg = <0x0 0x40 0x0 0x4c>, 279 <0x0 0xe8 0x0 0x18>, 280 <0x0 0x120 0x0 0x18>, 281 <0x0 0x2c0 0x0 0x40>, 282 <0x0 0x340 0x0 0x1c>; 283 reg-names = "gpio", 284 "pull", 285 "pull-enable", 286 "mux", 287 "ds"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 gpio-ranges = <&periphs_pinctrl 0 0 86>; 291 }; 292 293 cec_ao_a_h_pins: cec_ao_a_h { 294 mux { 295 groups = "cec_ao_a_h"; 296 function = "cec_ao_a_h"; 297 bias-disable; 298 }; 299 }; 300 301 cec_ao_b_h_pins: cec_ao_b_h { 302 mux { 303 groups = "cec_ao_b_h"; 304 function = "cec_ao_b_h"; 305 bias-disable; 306 }; 307 }; 308 309 emmc_ctrl_pins: emmc-ctrl { 310 mux-0 { 311 groups = "emmc_cmd"; 312 function = "emmc"; 313 bias-pull-up; 314 drive-strength-microamp = <4000>; 315 }; 316 317 mux-1 { 318 groups = "emmc_clk"; 319 function = "emmc"; 320 bias-disable; 321 drive-strength-microamp = <4000>; 322 }; 323 }; 324 325 emmc_data_4b_pins: emmc-data-4b { 326 mux-0 { 327 groups = "emmc_nand_d0", 328 "emmc_nand_d1", 329 "emmc_nand_d2", 330 "emmc_nand_d3"; 331 function = "emmc"; 332 bias-pull-up; 333 drive-strength-microamp = <4000>; 334 }; 335 }; 336 337 emmc_data_8b_pins: emmc-data-8b { 338 mux-0 { 339 groups = "emmc_nand_d0", 340 "emmc_nand_d1", 341 "emmc_nand_d2", 342 "emmc_nand_d3", 343 "emmc_nand_d4", 344 "emmc_nand_d5", 345 "emmc_nand_d6", 346 "emmc_nand_d7"; 347 function = "emmc"; 348 bias-pull-up; 349 drive-strength-microamp = <4000>; 350 }; 351 }; 352 353 emmc_ds_pins: emmc-ds { 354 mux { 355 groups = "emmc_nand_ds"; 356 function = "emmc"; 357 bias-pull-down; 358 drive-strength-microamp = <4000>; 359 }; 360 }; 361 362 emmc_clk_gate_pins: emmc_clk_gate { 363 mux { 364 groups = "BOOT_8"; 365 function = "gpio_periphs"; 366 bias-pull-down; 367 drive-strength-microamp = <4000>; 368 }; 369 }; 370 371 hdmitx_ddc_pins: hdmitx_ddc { 372 mux { 373 groups = "hdmitx_sda", 374 "hdmitx_sck"; 375 function = "hdmitx"; 376 bias-disable; 377 drive-strength-microamp = <4000>; 378 }; 379 }; 380 381 hdmitx_hpd_pins: hdmitx_hpd { 382 mux { 383 groups = "hdmitx_hpd_in"; 384 function = "hdmitx"; 385 bias-disable; 386 }; 387 }; 388 389 390 i2c0_sda_c_pins: i2c0-sda-c { 391 mux { 392 groups = "i2c0_sda_c"; 393 function = "i2c0"; 394 bias-disable; 395 drive-strength-microamp = <3000>; 396 397 }; 398 }; 399 400 i2c0_sck_c_pins: i2c0-sck-c { 401 mux { 402 groups = "i2c0_sck_c"; 403 function = "i2c0"; 404 bias-disable; 405 drive-strength-microamp = <3000>; 406 }; 407 }; 408 409 i2c0_sda_z0_pins: i2c0-sda-z0 { 410 mux { 411 groups = "i2c0_sda_z0"; 412 function = "i2c0"; 413 bias-disable; 414 drive-strength-microamp = <3000>; 415 }; 416 }; 417 418 i2c0_sck_z1_pins: i2c0-sck-z1 { 419 mux { 420 groups = "i2c0_sck_z1"; 421 function = "i2c0"; 422 bias-disable; 423 drive-strength-microamp = <3000>; 424 }; 425 }; 426 427 i2c0_sda_z7_pins: i2c0-sda-z7 { 428 mux { 429 groups = "i2c0_sda_z7"; 430 function = "i2c0"; 431 bias-disable; 432 drive-strength-microamp = <3000>; 433 }; 434 }; 435 436 i2c0_sda_z8_pins: i2c0-sda-z8 { 437 mux { 438 groups = "i2c0_sda_z8"; 439 function = "i2c0"; 440 bias-disable; 441 drive-strength-microamp = <3000>; 442 }; 443 }; 444 445 i2c1_sda_x_pins: i2c1-sda-x { 446 mux { 447 groups = "i2c1_sda_x"; 448 function = "i2c1"; 449 bias-disable; 450 drive-strength-microamp = <3000>; 451 }; 452 }; 453 454 i2c1_sck_x_pins: i2c1-sck-x { 455 mux { 456 groups = "i2c1_sck_x"; 457 function = "i2c1"; 458 bias-disable; 459 drive-strength-microamp = <3000>; 460 }; 461 }; 462 463 i2c1_sda_h2_pins: i2c1-sda-h2 { 464 mux { 465 groups = "i2c1_sda_h2"; 466 function = "i2c1"; 467 bias-disable; 468 drive-strength-microamp = <3000>; 469 }; 470 }; 471 472 i2c1_sck_h3_pins: i2c1-sck-h3 { 473 mux { 474 groups = "i2c1_sck_h3"; 475 function = "i2c1"; 476 bias-disable; 477 drive-strength-microamp = <3000>; 478 }; 479 }; 480 481 i2c1_sda_h6_pins: i2c1-sda-h6 { 482 mux { 483 groups = "i2c1_sda_h6"; 484 function = "i2c1"; 485 bias-disable; 486 drive-strength-microamp = <3000>; 487 }; 488 }; 489 490 i2c1_sck_h7_pins: i2c1-sck-h7 { 491 mux { 492 groups = "i2c1_sck_h7"; 493 function = "i2c1"; 494 bias-disable; 495 drive-strength-microamp = <3000>; 496 }; 497 }; 498 499 i2c2_sda_x_pins: i2c2-sda-x { 500 mux { 501 groups = "i2c2_sda_x"; 502 function = "i2c2"; 503 bias-disable; 504 drive-strength-microamp = <3000>; 505 }; 506 }; 507 508 i2c2_sck_x_pins: i2c2-sck-x { 509 mux { 510 groups = "i2c2_sck_x"; 511 function = "i2c2"; 512 bias-disable; 513 drive-strength-microamp = <3000>; 514 }; 515 }; 516 517 i2c2_sda_z_pins: i2c2-sda-z { 518 mux { 519 groups = "i2c2_sda_z"; 520 function = "i2c2"; 521 bias-disable; 522 drive-strength-microamp = <3000>; 523 }; 524 }; 525 526 i2c2_sck_z_pins: i2c2-sck-z { 527 mux { 528 groups = "i2c2_sck_z"; 529 function = "i2c2"; 530 bias-disable; 531 drive-strength-microamp = <3000>; 532 }; 533 }; 534 535 i2c3_sda_h_pins: i2c3-sda-h { 536 mux { 537 groups = "i2c3_sda_h"; 538 function = "i2c3"; 539 bias-disable; 540 drive-strength-microamp = <3000>; 541 }; 542 }; 543 544 i2c3_sck_h_pins: i2c3-sck-h { 545 mux { 546 groups = "i2c3_sck_h"; 547 function = "i2c3"; 548 bias-disable; 549 drive-strength-microamp = <3000>; 550 }; 551 }; 552 553 i2c3_sda_a_pins: i2c3-sda-a { 554 mux { 555 groups = "i2c3_sda_a"; 556 function = "i2c3"; 557 bias-disable; 558 drive-strength-microamp = <3000>; 559 }; 560 }; 561 562 i2c3_sck_a_pins: i2c3-sck-a { 563 mux { 564 groups = "i2c3_sck_a"; 565 function = "i2c3"; 566 bias-disable; 567 drive-strength-microamp = <3000>; 568 }; 569 }; 570 571 mclk0_a_pins: mclk0-a { 572 mux { 573 groups = "mclk0_a"; 574 function = "mclk0"; 575 bias-disable; 576 drive-strength-microamp = <3000>; 577 }; 578 }; 579 580 mclk1_a_pins: mclk1-a { 581 mux { 582 groups = "mclk1_a"; 583 function = "mclk1"; 584 bias-disable; 585 drive-strength-microamp = <3000>; 586 }; 587 }; 588 589 mclk1_x_pins: mclk1-x { 590 mux { 591 groups = "mclk1_x"; 592 function = "mclk1"; 593 bias-disable; 594 drive-strength-microamp = <3000>; 595 }; 596 }; 597 598 mclk1_z_pins: mclk1-z { 599 mux { 600 groups = "mclk1_z"; 601 function = "mclk1"; 602 bias-disable; 603 drive-strength-microamp = <3000>; 604 }; 605 }; 606 607 nor_pins: nor { 608 mux { 609 groups = "nor_d", 610 "nor_q", 611 "nor_c", 612 "nor_cs"; 613 function = "nor"; 614 bias-disable; 615 }; 616 }; 617 618 pdm_din0_a_pins: pdm-din0-a { 619 mux { 620 groups = "pdm_din0_a"; 621 function = "pdm"; 622 bias-disable; 623 }; 624 }; 625 626 pdm_din0_c_pins: pdm-din0-c { 627 mux { 628 groups = "pdm_din0_c"; 629 function = "pdm"; 630 bias-disable; 631 }; 632 }; 633 634 pdm_din0_x_pins: pdm-din0-x { 635 mux { 636 groups = "pdm_din0_x"; 637 function = "pdm"; 638 bias-disable; 639 }; 640 }; 641 642 pdm_din0_z_pins: pdm-din0-z { 643 mux { 644 groups = "pdm_din0_z"; 645 function = "pdm"; 646 bias-disable; 647 }; 648 }; 649 650 pdm_din1_a_pins: pdm-din1-a { 651 mux { 652 groups = "pdm_din1_a"; 653 function = "pdm"; 654 bias-disable; 655 }; 656 }; 657 658 pdm_din1_c_pins: pdm-din1-c { 659 mux { 660 groups = "pdm_din1_c"; 661 function = "pdm"; 662 bias-disable; 663 }; 664 }; 665 666 pdm_din1_x_pins: pdm-din1-x { 667 mux { 668 groups = "pdm_din1_x"; 669 function = "pdm"; 670 bias-disable; 671 }; 672 }; 673 674 pdm_din1_z_pins: pdm-din1-z { 675 mux { 676 groups = "pdm_din1_z"; 677 function = "pdm"; 678 bias-disable; 679 }; 680 }; 681 682 pdm_din2_a_pins: pdm-din2-a { 683 mux { 684 groups = "pdm_din2_a"; 685 function = "pdm"; 686 bias-disable; 687 }; 688 }; 689 690 pdm_din2_c_pins: pdm-din2-c { 691 mux { 692 groups = "pdm_din2_c"; 693 function = "pdm"; 694 bias-disable; 695 }; 696 }; 697 698 pdm_din2_x_pins: pdm-din2-x { 699 mux { 700 groups = "pdm_din2_x"; 701 function = "pdm"; 702 bias-disable; 703 }; 704 }; 705 706 pdm_din2_z_pins: pdm-din2-z { 707 mux { 708 groups = "pdm_din2_z"; 709 function = "pdm"; 710 bias-disable; 711 }; 712 }; 713 714 pdm_din3_a_pins: pdm-din3-a { 715 mux { 716 groups = "pdm_din3_a"; 717 function = "pdm"; 718 bias-disable; 719 }; 720 }; 721 722 pdm_din3_c_pins: pdm-din3-c { 723 mux { 724 groups = "pdm_din3_c"; 725 function = "pdm"; 726 bias-disable; 727 }; 728 }; 729 730 pdm_din3_x_pins: pdm-din3-x { 731 mux { 732 groups = "pdm_din3_x"; 733 function = "pdm"; 734 bias-disable; 735 }; 736 }; 737 738 pdm_din3_z_pins: pdm-din3-z { 739 mux { 740 groups = "pdm_din3_z"; 741 function = "pdm"; 742 bias-disable; 743 }; 744 }; 745 746 pdm_dclk_a_pins: pdm-dclk-a { 747 mux { 748 groups = "pdm_dclk_a"; 749 function = "pdm"; 750 bias-disable; 751 drive-strength-microamp = <500>; 752 }; 753 }; 754 755 pdm_dclk_c_pins: pdm-dclk-c { 756 mux { 757 groups = "pdm_dclk_c"; 758 function = "pdm"; 759 bias-disable; 760 drive-strength-microamp = <500>; 761 }; 762 }; 763 764 pdm_dclk_x_pins: pdm-dclk-x { 765 mux { 766 groups = "pdm_dclk_x"; 767 function = "pdm"; 768 bias-disable; 769 drive-strength-microamp = <500>; 770 }; 771 }; 772 773 pdm_dclk_z_pins: pdm-dclk-z { 774 mux { 775 groups = "pdm_dclk_z"; 776 function = "pdm"; 777 bias-disable; 778 drive-strength-microamp = <500>; 779 }; 780 }; 781 782 pwm_a_pins: pwm-a { 783 mux { 784 groups = "pwm_a"; 785 function = "pwm_a"; 786 bias-disable; 787 }; 788 }; 789 790 pwm_b_x7_pins: pwm-b-x7 { 791 mux { 792 groups = "pwm_b_x7"; 793 function = "pwm_b"; 794 bias-disable; 795 }; 796 }; 797 798 pwm_b_x19_pins: pwm-b-x19 { 799 mux { 800 groups = "pwm_b_x19"; 801 function = "pwm_b"; 802 bias-disable; 803 }; 804 }; 805 806 pwm_c_c_pins: pwm-c-c { 807 mux { 808 groups = "pwm_c_c"; 809 function = "pwm_c"; 810 bias-disable; 811 }; 812 }; 813 814 pwm_c_x5_pins: pwm-c-x5 { 815 mux { 816 groups = "pwm_c_x5"; 817 function = "pwm_c"; 818 bias-disable; 819 }; 820 }; 821 822 pwm_c_x8_pins: pwm-c-x8 { 823 mux { 824 groups = "pwm_c_x8"; 825 function = "pwm_c"; 826 bias-disable; 827 }; 828 }; 829 830 pwm_d_x3_pins: pwm-d-x3 { 831 mux { 832 groups = "pwm_d_x3"; 833 function = "pwm_d"; 834 bias-disable; 835 }; 836 }; 837 838 pwm_d_x6_pins: pwm-d-x6 { 839 mux { 840 groups = "pwm_d_x6"; 841 function = "pwm_d"; 842 bias-disable; 843 }; 844 }; 845 846 pwm_e_pins: pwm-e { 847 mux { 848 groups = "pwm_e"; 849 function = "pwm_e"; 850 bias-disable; 851 }; 852 }; 853 854 pwm_f_z_pins: pwm-f-z { 855 mux { 856 groups = "pwm_f_z"; 857 function = "pwm_f"; 858 bias-disable; 859 }; 860 }; 861 862 pwm_f_a_pins: pwm-f-a { 863 mux { 864 groups = "pwm_f_a"; 865 function = "pwm_f"; 866 bias-disable; 867 }; 868 }; 869 870 pwm_f_x_pins: pwm-f-x { 871 mux { 872 groups = "pwm_f_x"; 873 function = "pwm_f"; 874 bias-disable; 875 }; 876 }; 877 878 pwm_f_h_pins: pwm-f-h { 879 mux { 880 groups = "pwm_f_h"; 881 function = "pwm_f"; 882 bias-disable; 883 }; 884 }; 885 886 sdcard_c_pins: sdcard_c { 887 mux-0 { 888 groups = "sdcard_d0_c", 889 "sdcard_d1_c", 890 "sdcard_d2_c", 891 "sdcard_d3_c", 892 "sdcard_cmd_c"; 893 function = "sdcard"; 894 bias-pull-up; 895 drive-strength-microamp = <4000>; 896 }; 897 898 mux-1 { 899 groups = "sdcard_clk_c"; 900 function = "sdcard"; 901 bias-disable; 902 drive-strength-microamp = <4000>; 903 }; 904 }; 905 906 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 907 mux { 908 groups = "GPIOC_4"; 909 function = "gpio_periphs"; 910 bias-pull-down; 911 drive-strength-microamp = <4000>; 912 }; 913 }; 914 915 sdcard_z_pins: sdcard_z { 916 mux-0 { 917 groups = "sdcard_d0_z", 918 "sdcard_d1_z", 919 "sdcard_d2_z", 920 "sdcard_d3_z", 921 "sdcard_cmd_z"; 922 function = "sdcard"; 923 bias-pull-up; 924 drive-strength-microamp = <4000>; 925 }; 926 927 mux-1 { 928 groups = "sdcard_clk_z"; 929 function = "sdcard"; 930 bias-disable; 931 drive-strength-microamp = <4000>; 932 }; 933 }; 934 935 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 936 mux { 937 groups = "GPIOZ_6"; 938 function = "gpio_periphs"; 939 bias-pull-down; 940 drive-strength-microamp = <4000>; 941 }; 942 }; 943 944 sdio_pins: sdio { 945 mux { 946 groups = "sdio_d0", 947 "sdio_d1", 948 "sdio_d2", 949 "sdio_d3", 950 "sdio_clk", 951 "sdio_cmd"; 952 function = "sdio"; 953 bias-disable; 954 drive-strength-microamp = <4000>; 955 }; 956 }; 957 958 sdio_clk_gate_pins: sdio_clk_gate { 959 mux { 960 groups = "GPIOX_4"; 961 function = "gpio_periphs"; 962 bias-pull-down; 963 drive-strength-microamp = <4000>; 964 }; 965 }; 966 967 spdif_in_a10_pins: spdif-in-a10 { 968 mux { 969 groups = "spdif_in_a10"; 970 function = "spdif_in"; 971 bias-disable; 972 }; 973 }; 974 975 spdif_in_a12_pins: spdif-in-a12 { 976 mux { 977 groups = "spdif_in_a12"; 978 function = "spdif_in"; 979 bias-disable; 980 }; 981 }; 982 983 spdif_in_h_pins: spdif-in-h { 984 mux { 985 groups = "spdif_in_h"; 986 function = "spdif_in"; 987 bias-disable; 988 }; 989 }; 990 991 spdif_out_h_pins: spdif-out-h { 992 mux { 993 groups = "spdif_out_h"; 994 function = "spdif_out"; 995 drive-strength-microamp = <3000>; 996 bias-disable; 997 }; 998 }; 999 1000 spdif_out_a11_pins: spdif-out-a11 { 1001 mux { 1002 groups = "spdif_out_a11"; 1003 function = "spdif_out"; 1004 drive-strength-microamp = <3000>; 1005 bias-disable; 1006 }; 1007 }; 1008 1009 spdif_out_a13_pins: spdif-out-a13 { 1010 mux { 1011 groups = "spdif_out_a13"; 1012 function = "spdif_out"; 1013 drive-strength-microamp = <3000>; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 spicc0_x_pins: spicc0-x { 1019 mux { 1020 groups = "spi0_mosi_x", 1021 "spi0_miso_x", 1022 "spi0_clk_x"; 1023 function = "spi0"; 1024 drive-strength-microamp = <4000>; 1025 bias-disable; 1026 }; 1027 }; 1028 1029 spicc0_ss0_x_pins: spicc0-ss0-x { 1030 mux { 1031 groups = "spi0_ss0_x"; 1032 function = "spi0"; 1033 drive-strength-microamp = <4000>; 1034 bias-disable; 1035 }; 1036 }; 1037 1038 spicc0_c_pins: spicc0-c { 1039 mux { 1040 groups = "spi0_mosi_c", 1041 "spi0_miso_c", 1042 "spi0_ss0_c", 1043 "spi0_clk_c"; 1044 function = "spi0"; 1045 drive-strength-microamp = <4000>; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 spicc1_pins: spicc1 { 1051 mux { 1052 groups = "spi1_mosi", 1053 "spi1_miso", 1054 "spi1_clk"; 1055 function = "spi1"; 1056 drive-strength-microamp = <4000>; 1057 }; 1058 }; 1059 1060 spicc1_ss0_pins: spicc1-ss0 { 1061 mux { 1062 groups = "spi1_ss0"; 1063 function = "spi1"; 1064 drive-strength-microamp = <4000>; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 tdm_a_din0_pins: tdm-a-din0 { 1070 mux { 1071 groups = "tdm_a_din0"; 1072 function = "tdm_a"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 1078 tdm_a_din1_pins: tdm-a-din1 { 1079 mux { 1080 groups = "tdm_a_din1"; 1081 function = "tdm_a"; 1082 bias-disable; 1083 }; 1084 }; 1085 1086 tdm_a_dout0_pins: tdm-a-dout0 { 1087 mux { 1088 groups = "tdm_a_dout0"; 1089 function = "tdm_a"; 1090 bias-disable; 1091 drive-strength-microamp = <3000>; 1092 }; 1093 }; 1094 1095 tdm_a_dout1_pins: tdm-a-dout1 { 1096 mux { 1097 groups = "tdm_a_dout1"; 1098 function = "tdm_a"; 1099 bias-disable; 1100 drive-strength-microamp = <3000>; 1101 }; 1102 }; 1103 1104 tdm_a_fs_pins: tdm-a-fs { 1105 mux { 1106 groups = "tdm_a_fs"; 1107 function = "tdm_a"; 1108 bias-disable; 1109 drive-strength-microamp = <3000>; 1110 }; 1111 }; 1112 1113 tdm_a_sclk_pins: tdm-a-sclk { 1114 mux { 1115 groups = "tdm_a_sclk"; 1116 function = "tdm_a"; 1117 bias-disable; 1118 drive-strength-microamp = <3000>; 1119 }; 1120 }; 1121 1122 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1123 mux { 1124 groups = "tdm_a_slv_fs"; 1125 function = "tdm_a"; 1126 bias-disable; 1127 }; 1128 }; 1129 1130 1131 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1132 mux { 1133 groups = "tdm_a_slv_sclk"; 1134 function = "tdm_a"; 1135 bias-disable; 1136 }; 1137 }; 1138 1139 tdm_b_din0_pins: tdm-b-din0 { 1140 mux { 1141 groups = "tdm_b_din0"; 1142 function = "tdm_b"; 1143 bias-disable; 1144 }; 1145 }; 1146 1147 tdm_b_din1_pins: tdm-b-din1 { 1148 mux { 1149 groups = "tdm_b_din1"; 1150 function = "tdm_b"; 1151 bias-disable; 1152 }; 1153 }; 1154 1155 tdm_b_din2_pins: tdm-b-din2 { 1156 mux { 1157 groups = "tdm_b_din2"; 1158 function = "tdm_b"; 1159 bias-disable; 1160 }; 1161 }; 1162 1163 tdm_b_din3_a_pins: tdm-b-din3-a { 1164 mux { 1165 groups = "tdm_b_din3_a"; 1166 function = "tdm_b"; 1167 bias-disable; 1168 }; 1169 }; 1170 1171 tdm_b_din3_h_pins: tdm-b-din3-h { 1172 mux { 1173 groups = "tdm_b_din3_h"; 1174 function = "tdm_b"; 1175 bias-disable; 1176 }; 1177 }; 1178 1179 tdm_b_dout0_pins: tdm-b-dout0 { 1180 mux { 1181 groups = "tdm_b_dout0"; 1182 function = "tdm_b"; 1183 bias-disable; 1184 drive-strength-microamp = <3000>; 1185 }; 1186 }; 1187 1188 tdm_b_dout1_pins: tdm-b-dout1 { 1189 mux { 1190 groups = "tdm_b_dout1"; 1191 function = "tdm_b"; 1192 bias-disable; 1193 drive-strength-microamp = <3000>; 1194 }; 1195 }; 1196 1197 tdm_b_dout2_pins: tdm-b-dout2 { 1198 mux { 1199 groups = "tdm_b_dout2"; 1200 function = "tdm_b"; 1201 bias-disable; 1202 drive-strength-microamp = <3000>; 1203 }; 1204 }; 1205 1206 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1207 mux { 1208 groups = "tdm_b_dout3_a"; 1209 function = "tdm_b"; 1210 bias-disable; 1211 drive-strength-microamp = <3000>; 1212 }; 1213 }; 1214 1215 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1216 mux { 1217 groups = "tdm_b_dout3_h"; 1218 function = "tdm_b"; 1219 bias-disable; 1220 drive-strength-microamp = <3000>; 1221 }; 1222 }; 1223 1224 tdm_b_fs_pins: tdm-b-fs { 1225 mux { 1226 groups = "tdm_b_fs"; 1227 function = "tdm_b"; 1228 bias-disable; 1229 drive-strength-microamp = <3000>; 1230 }; 1231 }; 1232 1233 tdm_b_sclk_pins: tdm-b-sclk { 1234 mux { 1235 groups = "tdm_b_sclk"; 1236 function = "tdm_b"; 1237 bias-disable; 1238 drive-strength-microamp = <3000>; 1239 }; 1240 }; 1241 1242 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1243 mux { 1244 groups = "tdm_b_slv_fs"; 1245 function = "tdm_b"; 1246 bias-disable; 1247 }; 1248 }; 1249 1250 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1251 mux { 1252 groups = "tdm_b_slv_sclk"; 1253 function = "tdm_b"; 1254 bias-disable; 1255 }; 1256 }; 1257 1258 tdm_c_din0_a_pins: tdm-c-din0-a { 1259 mux { 1260 groups = "tdm_c_din0_a"; 1261 function = "tdm_c"; 1262 bias-disable; 1263 }; 1264 }; 1265 1266 tdm_c_din0_z_pins: tdm-c-din0-z { 1267 mux { 1268 groups = "tdm_c_din0_z"; 1269 function = "tdm_c"; 1270 bias-disable; 1271 }; 1272 }; 1273 1274 tdm_c_din1_a_pins: tdm-c-din1-a { 1275 mux { 1276 groups = "tdm_c_din1_a"; 1277 function = "tdm_c"; 1278 bias-disable; 1279 }; 1280 }; 1281 1282 tdm_c_din1_z_pins: tdm-c-din1-z { 1283 mux { 1284 groups = "tdm_c_din1_z"; 1285 function = "tdm_c"; 1286 bias-disable; 1287 }; 1288 }; 1289 1290 tdm_c_din2_a_pins: tdm-c-din2-a { 1291 mux { 1292 groups = "tdm_c_din2_a"; 1293 function = "tdm_c"; 1294 bias-disable; 1295 }; 1296 }; 1297 1298 eth_leds_pins: eth-leds { 1299 mux { 1300 groups = "eth_link_led", 1301 "eth_act_led"; 1302 function = "eth"; 1303 bias-disable; 1304 }; 1305 }; 1306 1307 eth_pins: eth { 1308 mux { 1309 groups = "eth_mdio", 1310 "eth_mdc", 1311 "eth_rgmii_rx_clk", 1312 "eth_rx_dv", 1313 "eth_rxd0", 1314 "eth_rxd1", 1315 "eth_txen", 1316 "eth_txd0", 1317 "eth_txd1"; 1318 function = "eth"; 1319 drive-strength-microamp = <4000>; 1320 bias-disable; 1321 }; 1322 }; 1323 1324 eth_rgmii_pins: eth-rgmii { 1325 mux { 1326 groups = "eth_rxd2_rgmii", 1327 "eth_rxd3_rgmii", 1328 "eth_rgmii_tx_clk", 1329 "eth_txd2_rgmii", 1330 "eth_txd3_rgmii"; 1331 function = "eth"; 1332 drive-strength-microamp = <4000>; 1333 bias-disable; 1334 }; 1335 }; 1336 1337 tdm_c_din2_z_pins: tdm-c-din2-z { 1338 mux { 1339 groups = "tdm_c_din2_z"; 1340 function = "tdm_c"; 1341 bias-disable; 1342 }; 1343 }; 1344 1345 tdm_c_din3_a_pins: tdm-c-din3-a { 1346 mux { 1347 groups = "tdm_c_din3_a"; 1348 function = "tdm_c"; 1349 bias-disable; 1350 }; 1351 }; 1352 1353 tdm_c_din3_z_pins: tdm-c-din3-z { 1354 mux { 1355 groups = "tdm_c_din3_z"; 1356 function = "tdm_c"; 1357 bias-disable; 1358 }; 1359 }; 1360 1361 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1362 mux { 1363 groups = "tdm_c_dout0_a"; 1364 function = "tdm_c"; 1365 bias-disable; 1366 drive-strength-microamp = <3000>; 1367 }; 1368 }; 1369 1370 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1371 mux { 1372 groups = "tdm_c_dout0_z"; 1373 function = "tdm_c"; 1374 bias-disable; 1375 drive-strength-microamp = <3000>; 1376 }; 1377 }; 1378 1379 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1380 mux { 1381 groups = "tdm_c_dout1_a"; 1382 function = "tdm_c"; 1383 bias-disable; 1384 drive-strength-microamp = <3000>; 1385 }; 1386 }; 1387 1388 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1389 mux { 1390 groups = "tdm_c_dout1_z"; 1391 function = "tdm_c"; 1392 bias-disable; 1393 drive-strength-microamp = <3000>; 1394 }; 1395 }; 1396 1397 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1398 mux { 1399 groups = "tdm_c_dout2_a"; 1400 function = "tdm_c"; 1401 bias-disable; 1402 drive-strength-microamp = <3000>; 1403 }; 1404 }; 1405 1406 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1407 mux { 1408 groups = "tdm_c_dout2_z"; 1409 function = "tdm_c"; 1410 bias-disable; 1411 drive-strength-microamp = <3000>; 1412 }; 1413 }; 1414 1415 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1416 mux { 1417 groups = "tdm_c_dout3_a"; 1418 function = "tdm_c"; 1419 bias-disable; 1420 drive-strength-microamp = <3000>; 1421 }; 1422 }; 1423 1424 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1425 mux { 1426 groups = "tdm_c_dout3_z"; 1427 function = "tdm_c"; 1428 bias-disable; 1429 drive-strength-microamp = <3000>; 1430 }; 1431 }; 1432 1433 tdm_c_fs_a_pins: tdm-c-fs-a { 1434 mux { 1435 groups = "tdm_c_fs_a"; 1436 function = "tdm_c"; 1437 bias-disable; 1438 drive-strength-microamp = <3000>; 1439 }; 1440 }; 1441 1442 tdm_c_fs_z_pins: tdm-c-fs-z { 1443 mux { 1444 groups = "tdm_c_fs_z"; 1445 function = "tdm_c"; 1446 bias-disable; 1447 drive-strength-microamp = <3000>; 1448 }; 1449 }; 1450 1451 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1452 mux { 1453 groups = "tdm_c_sclk_a"; 1454 function = "tdm_c"; 1455 bias-disable; 1456 drive-strength-microamp = <3000>; 1457 }; 1458 }; 1459 1460 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1461 mux { 1462 groups = "tdm_c_sclk_z"; 1463 function = "tdm_c"; 1464 bias-disable; 1465 drive-strength-microamp = <3000>; 1466 }; 1467 }; 1468 1469 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1470 mux { 1471 groups = "tdm_c_slv_fs_a"; 1472 function = "tdm_c"; 1473 bias-disable; 1474 }; 1475 }; 1476 1477 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1478 mux { 1479 groups = "tdm_c_slv_fs_z"; 1480 function = "tdm_c"; 1481 bias-disable; 1482 }; 1483 }; 1484 1485 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1486 mux { 1487 groups = "tdm_c_slv_sclk_a"; 1488 function = "tdm_c"; 1489 bias-disable; 1490 }; 1491 }; 1492 1493 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1494 mux { 1495 groups = "tdm_c_slv_sclk_z"; 1496 function = "tdm_c"; 1497 bias-disable; 1498 }; 1499 }; 1500 1501 uart_a_pins: uart-a { 1502 mux { 1503 groups = "uart_a_tx", 1504 "uart_a_rx"; 1505 function = "uart_a"; 1506 bias-disable; 1507 }; 1508 }; 1509 1510 uart_a_cts_rts_pins: uart-a-cts-rts { 1511 mux { 1512 groups = "uart_a_cts", 1513 "uart_a_rts"; 1514 function = "uart_a"; 1515 bias-disable; 1516 }; 1517 }; 1518 1519 uart_b_pins: uart-b { 1520 mux { 1521 groups = "uart_b_tx", 1522 "uart_b_rx"; 1523 function = "uart_b"; 1524 bias-disable; 1525 }; 1526 }; 1527 1528 uart_c_pins: uart-c { 1529 mux { 1530 groups = "uart_c_tx", 1531 "uart_c_rx"; 1532 function = "uart_c"; 1533 bias-disable; 1534 }; 1535 }; 1536 1537 uart_c_cts_rts_pins: uart-c-cts-rts { 1538 mux { 1539 groups = "uart_c_cts", 1540 "uart_c_rts"; 1541 function = "uart_c"; 1542 bias-disable; 1543 }; 1544 }; 1545 }; 1546 }; 1547 1548 cpu_temp: temperature-sensor@34800 { 1549 compatible = "amlogic,g12a-cpu-thermal", 1550 "amlogic,g12a-thermal"; 1551 reg = <0x0 0x34800 0x0 0x50>; 1552 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1553 clocks = <&clkc CLKID_TS>; 1554 #thermal-sensor-cells = <0>; 1555 amlogic,ao-secure = <&sec_AO>; 1556 }; 1557 1558 ddr_temp: temperature-sensor@34c00 { 1559 compatible = "amlogic,g12a-ddr-thermal", 1560 "amlogic,g12a-thermal"; 1561 reg = <0x0 0x34c00 0x0 0x50>; 1562 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1563 clocks = <&clkc CLKID_TS>; 1564 #thermal-sensor-cells = <0>; 1565 amlogic,ao-secure = <&sec_AO>; 1566 }; 1567 1568 usb2_phy0: phy@36000 { 1569 compatible = "amlogic,g12a-usb2-phy"; 1570 reg = <0x0 0x36000 0x0 0x2000>; 1571 clocks = <&xtal>; 1572 clock-names = "xtal"; 1573 resets = <&reset RESET_USB_PHY20>; 1574 reset-names = "phy"; 1575 #phy-cells = <0>; 1576 }; 1577 1578 dmc: bus@38000 { 1579 compatible = "simple-bus"; 1580 #address-cells = <2>; 1581 #size-cells = <2>; 1582 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>; 1583 1584 canvas: video-lut@48 { 1585 compatible = "amlogic,canvas"; 1586 reg = <0x0 0x48 0x0 0x14>; 1587 }; 1588 1589 pmu: pmu@80 { 1590 reg = <0x0 0x80 0x0 0x40>, 1591 <0x0 0xc00 0x0 0x40>; 1592 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1593 }; 1594 }; 1595 1596 usb2_phy1: phy@3a000 { 1597 compatible = "amlogic,g12a-usb2-phy"; 1598 reg = <0x0 0x3a000 0x0 0x2000>; 1599 clocks = <&xtal>; 1600 clock-names = "xtal"; 1601 resets = <&reset RESET_USB_PHY21>; 1602 reset-names = "phy"; 1603 #phy-cells = <0>; 1604 }; 1605 1606 hiu: bus@3c000 { 1607 compatible = "simple-bus"; 1608 reg = <0x0 0x3c000 0x0 0x1400>; 1609 #address-cells = <2>; 1610 #size-cells = <2>; 1611 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1612 1613 hhi: system-controller@0 { 1614 compatible = "amlogic,meson-gx-hhi-sysctrl", 1615 "simple-mfd", "syscon"; 1616 reg = <0 0 0 0x400>; 1617 1618 clkc: clock-controller { 1619 compatible = "amlogic,g12a-clkc"; 1620 #clock-cells = <1>; 1621 clocks = <&xtal>; 1622 clock-names = "xtal"; 1623 }; 1624 1625 pwrc: power-controller { 1626 compatible = "amlogic,meson-g12a-pwrc"; 1627 #power-domain-cells = <1>; 1628 amlogic,ao-sysctrl = <&rti>; 1629 resets = <&reset RESET_VIU>, 1630 <&reset RESET_VENC>, 1631 <&reset RESET_VCBUS>, 1632 <&reset RESET_BT656>, 1633 <&reset RESET_RDMA>, 1634 <&reset RESET_VENCI>, 1635 <&reset RESET_VENCP>, 1636 <&reset RESET_VDAC>, 1637 <&reset RESET_VDI6>, 1638 <&reset RESET_VENCL>, 1639 <&reset RESET_VID_LOCK>; 1640 reset-names = "viu", "venc", "vcbus", "bt656", 1641 "rdma", "venci", "vencp", "vdac", 1642 "vdi6", "vencl", "vid_lock"; 1643 clocks = <&clkc CLKID_VPU>, 1644 <&clkc CLKID_VAPB>; 1645 clock-names = "vpu", "vapb"; 1646 /* 1647 * VPU clocking is provided by two identical clock paths 1648 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1649 * free mux to safely change frequency while running. 1650 * Same for VAPB but with a final gate after the glitch free mux. 1651 */ 1652 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1653 <&clkc CLKID_VPU_0>, 1654 <&clkc CLKID_VPU>, /* Glitch free mux */ 1655 <&clkc CLKID_VAPB_0_SEL>, 1656 <&clkc CLKID_VAPB_0>, 1657 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1658 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1659 <0>, /* Do Nothing */ 1660 <&clkc CLKID_VPU_0>, 1661 <&clkc CLKID_FCLK_DIV4>, 1662 <0>, /* Do Nothing */ 1663 <&clkc CLKID_VAPB_0>; 1664 assigned-clock-rates = <0>, /* Do Nothing */ 1665 <666666666>, 1666 <0>, /* Do Nothing */ 1667 <0>, /* Do Nothing */ 1668 <250000000>, 1669 <0>; /* Do Nothing */ 1670 }; 1671 1672 mipi_analog_dphy: phy { 1673 compatible = "amlogic,g12a-mipi-dphy-analog"; 1674 #phy-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 }; 1678 }; 1679 1680 mipi_dphy: phy@44000 { 1681 compatible = "amlogic,axg-mipi-dphy"; 1682 reg = <0x0 0x44000 0x0 0x2000>; 1683 clocks = <&clkc CLKID_MIPI_DSI_PHY>; 1684 clock-names = "pclk"; 1685 resets = <&reset RESET_MIPI_DSI_PHY>; 1686 reset-names = "phy"; 1687 phys = <&mipi_analog_dphy>; 1688 phy-names = "analog"; 1689 #phy-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 usb3_pcie_phy: phy@46000 { 1694 compatible = "amlogic,g12a-usb3-pcie-phy"; 1695 reg = <0x0 0x46000 0x0 0x2000>; 1696 clocks = <&clkc CLKID_PCIE_PLL>; 1697 clock-names = "ref_clk"; 1698 resets = <&reset RESET_PCIE_PHY>; 1699 reset-names = "phy"; 1700 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1701 assigned-clock-rates = <100000000>; 1702 #phy-cells = <1>; 1703 }; 1704 1705 eth_phy: mdio-multiplexer@4c000 { 1706 compatible = "amlogic,g12a-mdio-mux"; 1707 reg = <0x0 0x4c000 0x0 0xa4>; 1708 clocks = <&clkc CLKID_ETH_PHY>, 1709 <&xtal>, 1710 <&clkc CLKID_MPLL_50M>; 1711 clock-names = "pclk", "clkin0", "clkin1"; 1712 mdio-parent-bus = <&mdio0>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 ext_mdio: mdio@0 { 1717 reg = <0>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 }; 1721 1722 int_mdio: mdio@1 { 1723 reg = <1>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 1727 internal_ephy: ethernet-phy@8 { 1728 compatible = "ethernet-phy-id0180.3301", 1729 "ethernet-phy-ieee802.3-c22"; 1730 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1731 reg = <8>; 1732 max-speed = <100>; 1733 }; 1734 }; 1735 }; 1736 }; 1737 1738 aobus: bus@ff800000 { 1739 compatible = "simple-bus"; 1740 reg = <0x0 0xff800000 0x0 0x100000>; 1741 #address-cells = <2>; 1742 #size-cells = <2>; 1743 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1744 1745 rti: sys-ctrl@0 { 1746 compatible = "amlogic,meson-gx-ao-sysctrl", 1747 "simple-mfd", "syscon"; 1748 reg = <0x0 0x0 0x0 0x100>; 1749 1750 clkc_AO: clock-controller { 1751 compatible = "amlogic,meson-g12a-aoclkc"; 1752 #clock-cells = <1>; 1753 #reset-cells = <1>; 1754 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1755 clock-names = "xtal", "mpeg-clk"; 1756 }; 1757 }; 1758 1759 ao_pinctrl: pinctrl@14 { 1760 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1761 #address-cells = <2>; 1762 #size-cells = <2>; 1763 ranges; 1764 1765 gpio_ao: bank@14 { 1766 reg = <0x0 0x14 0x0 0x8>, 1767 <0x0 0x1c 0x0 0x8>, 1768 <0x0 0x24 0x0 0x14>; 1769 reg-names = "mux", 1770 "ds", 1771 "gpio"; 1772 gpio-controller; 1773 #gpio-cells = <2>; 1774 gpio-ranges = <&ao_pinctrl 0 0 15>; 1775 }; 1776 1777 i2c_ao_sck_pins: i2c_ao_sck_pins { 1778 mux { 1779 groups = "i2c_ao_sck"; 1780 function = "i2c_ao"; 1781 bias-disable; 1782 drive-strength-microamp = <3000>; 1783 }; 1784 }; 1785 1786 i2c_ao_sda_pins: i2c_ao_sda { 1787 mux { 1788 groups = "i2c_ao_sda"; 1789 function = "i2c_ao"; 1790 bias-disable; 1791 drive-strength-microamp = <3000>; 1792 }; 1793 }; 1794 1795 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1796 mux { 1797 groups = "i2c_ao_sck_e"; 1798 function = "i2c_ao"; 1799 bias-disable; 1800 drive-strength-microamp = <3000>; 1801 }; 1802 }; 1803 1804 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1805 mux { 1806 groups = "i2c_ao_sda_e"; 1807 function = "i2c_ao"; 1808 bias-disable; 1809 drive-strength-microamp = <3000>; 1810 }; 1811 }; 1812 1813 mclk0_ao_pins: mclk0-ao { 1814 mux { 1815 groups = "mclk0_ao"; 1816 function = "mclk0_ao"; 1817 bias-disable; 1818 drive-strength-microamp = <3000>; 1819 }; 1820 }; 1821 1822 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1823 mux { 1824 groups = "tdm_ao_b_din0"; 1825 function = "tdm_ao_b"; 1826 bias-disable; 1827 }; 1828 }; 1829 1830 spdif_ao_out_pins: spdif-ao-out { 1831 mux { 1832 groups = "spdif_ao_out"; 1833 function = "spdif_ao_out"; 1834 drive-strength-microamp = <3000>; 1835 bias-disable; 1836 }; 1837 }; 1838 1839 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1840 mux { 1841 groups = "tdm_ao_b_din1"; 1842 function = "tdm_ao_b"; 1843 bias-disable; 1844 }; 1845 }; 1846 1847 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1848 mux { 1849 groups = "tdm_ao_b_din2"; 1850 function = "tdm_ao_b"; 1851 bias-disable; 1852 }; 1853 }; 1854 1855 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1856 mux { 1857 groups = "tdm_ao_b_dout0"; 1858 function = "tdm_ao_b"; 1859 bias-disable; 1860 drive-strength-microamp = <3000>; 1861 }; 1862 }; 1863 1864 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1865 mux { 1866 groups = "tdm_ao_b_dout1"; 1867 function = "tdm_ao_b"; 1868 bias-disable; 1869 drive-strength-microamp = <3000>; 1870 }; 1871 }; 1872 1873 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1874 mux { 1875 groups = "tdm_ao_b_dout2"; 1876 function = "tdm_ao_b"; 1877 bias-disable; 1878 drive-strength-microamp = <3000>; 1879 }; 1880 }; 1881 1882 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1883 mux { 1884 groups = "tdm_ao_b_fs"; 1885 function = "tdm_ao_b"; 1886 bias-disable; 1887 drive-strength-microamp = <3000>; 1888 }; 1889 }; 1890 1891 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1892 mux { 1893 groups = "tdm_ao_b_sclk"; 1894 function = "tdm_ao_b"; 1895 bias-disable; 1896 drive-strength-microamp = <3000>; 1897 }; 1898 }; 1899 1900 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1901 mux { 1902 groups = "tdm_ao_b_slv_fs"; 1903 function = "tdm_ao_b"; 1904 bias-disable; 1905 }; 1906 }; 1907 1908 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1909 mux { 1910 groups = "tdm_ao_b_slv_sclk"; 1911 function = "tdm_ao_b"; 1912 bias-disable; 1913 }; 1914 }; 1915 1916 uart_ao_a_pins: uart-a-ao { 1917 mux { 1918 groups = "uart_ao_a_tx", 1919 "uart_ao_a_rx"; 1920 function = "uart_ao_a"; 1921 bias-disable; 1922 }; 1923 }; 1924 1925 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1926 mux { 1927 groups = "uart_ao_a_cts", 1928 "uart_ao_a_rts"; 1929 function = "uart_ao_a"; 1930 bias-disable; 1931 }; 1932 }; 1933 1934 uart_ao_b_2_3_pins: uart-ao-b-2-3 { 1935 mux { 1936 groups = "uart_ao_b_tx_2", 1937 "uart_ao_b_rx_3"; 1938 function = "uart_ao_b"; 1939 bias-disable; 1940 }; 1941 }; 1942 1943 uart_ao_b_8_9_pins: uart-ao-b-8-9 { 1944 mux { 1945 groups = "uart_ao_b_tx_8", 1946 "uart_ao_b_rx_9"; 1947 function = "uart_ao_b"; 1948 bias-disable; 1949 }; 1950 }; 1951 1952 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { 1953 mux { 1954 groups = "uart_ao_b_cts", 1955 "uart_ao_b_rts"; 1956 function = "uart_ao_b"; 1957 bias-disable; 1958 }; 1959 }; 1960 1961 pwm_a_e_pins: pwm-a-e { 1962 mux { 1963 groups = "pwm_a_e"; 1964 function = "pwm_a_e"; 1965 bias-disable; 1966 }; 1967 }; 1968 1969 pwm_ao_a_pins: pwm-ao-a { 1970 mux { 1971 groups = "pwm_ao_a"; 1972 function = "pwm_ao_a"; 1973 bias-disable; 1974 }; 1975 }; 1976 1977 pwm_ao_b_pins: pwm-ao-b { 1978 mux { 1979 groups = "pwm_ao_b"; 1980 function = "pwm_ao_b"; 1981 bias-disable; 1982 }; 1983 }; 1984 1985 pwm_ao_c_4_pins: pwm-ao-c-4 { 1986 mux { 1987 groups = "pwm_ao_c_4"; 1988 function = "pwm_ao_c"; 1989 bias-disable; 1990 }; 1991 }; 1992 1993 pwm_ao_c_6_pins: pwm-ao-c-6 { 1994 mux { 1995 groups = "pwm_ao_c_6"; 1996 function = "pwm_ao_c"; 1997 bias-disable; 1998 }; 1999 }; 2000 2001 pwm_ao_d_5_pins: pwm-ao-d-5 { 2002 mux { 2003 groups = "pwm_ao_d_5"; 2004 function = "pwm_ao_d"; 2005 bias-disable; 2006 }; 2007 }; 2008 2009 pwm_ao_d_10_pins: pwm-ao-d-10 { 2010 mux { 2011 groups = "pwm_ao_d_10"; 2012 function = "pwm_ao_d"; 2013 bias-disable; 2014 }; 2015 }; 2016 2017 pwm_ao_d_e_pins: pwm-ao-d-e { 2018 mux { 2019 groups = "pwm_ao_d_e"; 2020 function = "pwm_ao_d"; 2021 }; 2022 }; 2023 2024 remote_input_ao_pins: remote-input-ao { 2025 mux { 2026 groups = "remote_ao_input"; 2027 function = "remote_ao_input"; 2028 bias-disable; 2029 }; 2030 }; 2031 }; 2032 2033 vrtc: rtc@a8 { 2034 compatible = "amlogic,meson-vrtc"; 2035 reg = <0x0 0x000a8 0x0 0x4>; 2036 }; 2037 2038 cec_AO: cec@100 { 2039 compatible = "amlogic,meson-gx-ao-cec"; 2040 reg = <0x0 0x00100 0x0 0x14>; 2041 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2042 clocks = <&clkc_AO CLKID_AO_CEC>; 2043 clock-names = "core"; 2044 status = "disabled"; 2045 }; 2046 2047 sec_AO: ao-secure@140 { 2048 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2049 reg = <0x0 0x140 0x0 0x140>; 2050 amlogic,has-chip-id; 2051 }; 2052 2053 cecb_AO: cec@280 { 2054 compatible = "amlogic,meson-g12a-ao-cec"; 2055 reg = <0x0 0x00280 0x0 0x1c>; 2056 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2057 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2058 clock-names = "oscin"; 2059 status = "disabled"; 2060 }; 2061 2062 pwm_AO_cd: pwm@2000 { 2063 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2064 reg = <0x0 0x2000 0x0 0x20>; 2065 #pwm-cells = <3>; 2066 status = "disabled"; 2067 }; 2068 2069 uart_AO: serial@3000 { 2070 compatible = "amlogic,meson-g12a-uart", 2071 "amlogic,meson-gx-uart", 2072 "amlogic,meson-ao-uart"; 2073 reg = <0x0 0x3000 0x0 0x18>; 2074 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2075 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2076 clock-names = "xtal", "pclk", "baud"; 2077 status = "disabled"; 2078 }; 2079 2080 uart_AO_B: serial@4000 { 2081 compatible = "amlogic,meson-g12a-uart", 2082 "amlogic,meson-gx-uart", 2083 "amlogic,meson-ao-uart"; 2084 reg = <0x0 0x4000 0x0 0x18>; 2085 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2086 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2087 clock-names = "xtal", "pclk", "baud"; 2088 status = "disabled"; 2089 }; 2090 2091 i2c_AO: i2c@5000 { 2092 compatible = "amlogic,meson-axg-i2c"; 2093 status = "disabled"; 2094 reg = <0x0 0x05000 0x0 0x20>; 2095 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2096 #address-cells = <1>; 2097 #size-cells = <0>; 2098 clocks = <&clkc CLKID_I2C>; 2099 }; 2100 2101 pwm_AO_ab: pwm@7000 { 2102 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2103 reg = <0x0 0x7000 0x0 0x20>; 2104 #pwm-cells = <3>; 2105 status = "disabled"; 2106 }; 2107 2108 ir: ir@8000 { 2109 compatible = "amlogic,meson-gxbb-ir"; 2110 reg = <0x0 0x8000 0x0 0x20>; 2111 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2112 status = "disabled"; 2113 }; 2114 2115 saradc: adc@9000 { 2116 compatible = "amlogic,meson-g12a-saradc", 2117 "amlogic,meson-saradc"; 2118 reg = <0x0 0x9000 0x0 0x48>; 2119 #io-channel-cells = <1>; 2120 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2121 clocks = <&xtal>, 2122 <&clkc_AO CLKID_AO_SAR_ADC>, 2123 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2124 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2125 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2126 status = "disabled"; 2127 }; 2128 }; 2129 2130 vdec: video-decoder@ff620000 { 2131 compatible = "amlogic,g12a-vdec"; 2132 reg = <0x0 0xff620000 0x0 0x10000>, 2133 <0x0 0xffd0e180 0x0 0xe4>; 2134 reg-names = "dos", "esparser"; 2135 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2136 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2137 interrupt-names = "vdec", "esparser"; 2138 2139 amlogic,ao-sysctrl = <&rti>; 2140 amlogic,canvas = <&canvas>; 2141 2142 clocks = <&clkc CLKID_PARSER>, 2143 <&clkc CLKID_DOS>, 2144 <&clkc CLKID_VDEC_1>, 2145 <&clkc CLKID_VDEC_HEVC>, 2146 <&clkc CLKID_VDEC_HEVCF>; 2147 clock-names = "dos_parser", "dos", "vdec_1", 2148 "vdec_hevc", "vdec_hevcf"; 2149 resets = <&reset RESET_PARSER>; 2150 reset-names = "esparser"; 2151 }; 2152 2153 vpu: vpu@ff900000 { 2154 compatible = "amlogic,meson-g12a-vpu"; 2155 reg = <0x0 0xff900000 0x0 0x100000>, 2156 <0x0 0xff63c000 0x0 0x1000>; 2157 reg-names = "vpu", "hhi"; 2158 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 amlogic,canvas = <&canvas>; 2162 2163 /* CVBS VDAC output port */ 2164 cvbs_vdac_port: port@0 { 2165 reg = <0>; 2166 }; 2167 2168 /* HDMI-TX output port */ 2169 hdmi_tx_port: port@1 { 2170 reg = <1>; 2171 2172 hdmi_tx_out: endpoint { 2173 remote-endpoint = <&hdmi_tx_in>; 2174 }; 2175 }; 2176 2177 /* DPI output port */ 2178 dpi_port: port@2 { 2179 reg = <2>; 2180 2181 dpi_out: endpoint { 2182 remote-endpoint = <&mipi_dsi_in>; 2183 }; 2184 }; 2185 }; 2186 2187 gic: interrupt-controller@ffc01000 { 2188 compatible = "arm,gic-400"; 2189 reg = <0x0 0xffc01000 0 0x1000>, 2190 <0x0 0xffc02000 0 0x2000>, 2191 <0x0 0xffc04000 0 0x2000>, 2192 <0x0 0xffc06000 0 0x2000>; 2193 interrupt-controller; 2194 interrupts = <GIC_PPI 9 2195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2196 #interrupt-cells = <3>; 2197 #address-cells = <0>; 2198 }; 2199 2200 cbus: bus@ffd00000 { 2201 compatible = "simple-bus"; 2202 reg = <0x0 0xffd00000 0x0 0x100000>; 2203 #address-cells = <2>; 2204 #size-cells = <2>; 2205 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2206 2207 reset: reset-controller@1004 { 2208 compatible = "amlogic,meson-axg-reset"; 2209 reg = <0x0 0x1004 0x0 0x9c>; 2210 #reset-cells = <1>; 2211 }; 2212 2213 gpio_intc: interrupt-controller@f080 { 2214 compatible = "amlogic,meson-g12a-gpio-intc", 2215 "amlogic,meson-gpio-intc"; 2216 reg = <0x0 0xf080 0x0 0x10>; 2217 interrupt-controller; 2218 #interrupt-cells = <2>; 2219 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2220 }; 2221 2222 mipi_dsi: dsi@7000 { 2223 compatible = "amlogic,meson-g12a-dw-mipi-dsi"; 2224 reg = <0x0 0x7000 0x0 0x1000>; 2225 resets = <&reset RESET_MIPI_DSI_HOST>; 2226 reset-names = "top"; 2227 clocks = <&clkc CLKID_MIPI_DSI_HOST>, 2228 <&clkc CLKID_MIPI_DSI_PXCLK>, 2229 <&clkc CLKID_CTS_ENCL>; 2230 clock-names = "pclk", "bit", "px"; 2231 phys = <&mipi_dphy>; 2232 phy-names = "dphy"; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 status = "disabled"; 2236 2237 assigned-clocks = <&clkc CLKID_MIPI_DSI_PXCLK_SEL>, 2238 <&clkc CLKID_CTS_ENCL_SEL>, 2239 <&clkc CLKID_VCLK2_SEL>; 2240 assigned-clock-parents = <&clkc CLKID_GP0_PLL>, 2241 <&clkc CLKID_VCLK2_DIV1>, 2242 <&clkc CLKID_GP0_PLL>; 2243 2244 ports { 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 2248 /* VPU VENC Input */ 2249 mipi_dsi_venc_port: port@0 { 2250 reg = <0>; 2251 2252 mipi_dsi_in: endpoint { 2253 remote-endpoint = <&dpi_out>; 2254 }; 2255 }; 2256 2257 /* DSI Output */ 2258 mipi_dsi_panel_port: port@1 { 2259 reg = <1>; 2260 }; 2261 }; 2262 }; 2263 2264 watchdog: watchdog@f0d0 { 2265 compatible = "amlogic,meson-gxbb-wdt"; 2266 reg = <0x0 0xf0d0 0x0 0x10>; 2267 clocks = <&xtal>; 2268 }; 2269 2270 spicc0: spi@13000 { 2271 compatible = "amlogic,meson-g12a-spicc"; 2272 reg = <0x0 0x13000 0x0 0x44>; 2273 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2274 clocks = <&clkc CLKID_SPICC0>, 2275 <&clkc CLKID_SPICC0_SCLK>; 2276 clock-names = "core", "pclk"; 2277 #address-cells = <1>; 2278 #size-cells = <0>; 2279 status = "disabled"; 2280 }; 2281 2282 spicc1: spi@15000 { 2283 compatible = "amlogic,meson-g12a-spicc"; 2284 reg = <0x0 0x15000 0x0 0x44>; 2285 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2286 clocks = <&clkc CLKID_SPICC1>, 2287 <&clkc CLKID_SPICC1_SCLK>; 2288 clock-names = "core", "pclk"; 2289 #address-cells = <1>; 2290 #size-cells = <0>; 2291 status = "disabled"; 2292 }; 2293 2294 spifc: spi@14000 { 2295 compatible = "amlogic,meson-gxbb-spifc"; 2296 status = "disabled"; 2297 reg = <0x0 0x14000 0x0 0x80>; 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 clocks = <&clkc CLKID_CLK81>; 2301 }; 2302 2303 pwm_ef: pwm@19000 { 2304 compatible = "amlogic,meson-g12a-ee-pwm"; 2305 reg = <0x0 0x19000 0x0 0x20>; 2306 #pwm-cells = <3>; 2307 status = "disabled"; 2308 }; 2309 2310 pwm_cd: pwm@1a000 { 2311 compatible = "amlogic,meson-g12a-ee-pwm"; 2312 reg = <0x0 0x1a000 0x0 0x20>; 2313 #pwm-cells = <3>; 2314 status = "disabled"; 2315 }; 2316 2317 pwm_ab: pwm@1b000 { 2318 compatible = "amlogic,meson-g12a-ee-pwm"; 2319 reg = <0x0 0x1b000 0x0 0x20>; 2320 #pwm-cells = <3>; 2321 status = "disabled"; 2322 }; 2323 2324 i2c3: i2c@1c000 { 2325 compatible = "amlogic,meson-axg-i2c"; 2326 status = "disabled"; 2327 reg = <0x0 0x1c000 0x0 0x20>; 2328 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 clocks = <&clkc CLKID_I2C>; 2332 }; 2333 2334 i2c2: i2c@1d000 { 2335 compatible = "amlogic,meson-axg-i2c"; 2336 status = "disabled"; 2337 reg = <0x0 0x1d000 0x0 0x20>; 2338 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 clocks = <&clkc CLKID_I2C>; 2342 }; 2343 2344 i2c1: i2c@1e000 { 2345 compatible = "amlogic,meson-axg-i2c"; 2346 status = "disabled"; 2347 reg = <0x0 0x1e000 0x0 0x20>; 2348 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 clocks = <&clkc CLKID_I2C>; 2352 }; 2353 2354 i2c0: i2c@1f000 { 2355 compatible = "amlogic,meson-axg-i2c"; 2356 status = "disabled"; 2357 reg = <0x0 0x1f000 0x0 0x20>; 2358 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2359 #address-cells = <1>; 2360 #size-cells = <0>; 2361 clocks = <&clkc CLKID_I2C>; 2362 }; 2363 2364 clk_msr: clock-measure@18000 { 2365 compatible = "amlogic,meson-g12a-clk-measure"; 2366 reg = <0x0 0x18000 0x0 0x10>; 2367 }; 2368 2369 uart_C: serial@22000 { 2370 compatible = "amlogic,meson-g12a-uart", 2371 "amlogic,meson-gx-uart"; 2372 reg = <0x0 0x22000 0x0 0x18>; 2373 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2374 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2375 clock-names = "xtal", "pclk", "baud"; 2376 status = "disabled"; 2377 }; 2378 2379 uart_B: serial@23000 { 2380 compatible = "amlogic,meson-g12a-uart", 2381 "amlogic,meson-gx-uart"; 2382 reg = <0x0 0x23000 0x0 0x18>; 2383 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2384 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2385 clock-names = "xtal", "pclk", "baud"; 2386 status = "disabled"; 2387 }; 2388 2389 uart_A: serial@24000 { 2390 compatible = "amlogic,meson-g12a-uart", 2391 "amlogic,meson-gx-uart"; 2392 reg = <0x0 0x24000 0x0 0x18>; 2393 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2394 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2395 clock-names = "xtal", "pclk", "baud"; 2396 status = "disabled"; 2397 fifo-size = <128>; 2398 }; 2399 }; 2400 2401 sd_emmc_a: mmc@ffe03000 { 2402 compatible = "amlogic,meson-axg-mmc"; 2403 reg = <0x0 0xffe03000 0x0 0x800>; 2404 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2405 status = "disabled"; 2406 clocks = <&clkc CLKID_SD_EMMC_A>, 2407 <&clkc CLKID_SD_EMMC_A_CLK0>, 2408 <&clkc CLKID_FCLK_DIV2>; 2409 clock-names = "core", "clkin0", "clkin1"; 2410 resets = <&reset RESET_SD_EMMC_A>; 2411 }; 2412 2413 sd_emmc_b: mmc@ffe05000 { 2414 compatible = "amlogic,meson-axg-mmc"; 2415 reg = <0x0 0xffe05000 0x0 0x800>; 2416 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2417 status = "disabled"; 2418 clocks = <&clkc CLKID_SD_EMMC_B>, 2419 <&clkc CLKID_SD_EMMC_B_CLK0>, 2420 <&clkc CLKID_FCLK_DIV2>; 2421 clock-names = "core", "clkin0", "clkin1"; 2422 resets = <&reset RESET_SD_EMMC_B>; 2423 }; 2424 2425 sd_emmc_c: mmc@ffe07000 { 2426 compatible = "amlogic,meson-axg-mmc"; 2427 reg = <0x0 0xffe07000 0x0 0x800>; 2428 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2429 status = "disabled"; 2430 clocks = <&clkc CLKID_SD_EMMC_C>, 2431 <&clkc CLKID_SD_EMMC_C_CLK0>, 2432 <&clkc CLKID_FCLK_DIV2>; 2433 clock-names = "core", "clkin0", "clkin1"; 2434 resets = <&reset RESET_SD_EMMC_C>; 2435 }; 2436 2437 usb: usb@ffe09000 { 2438 status = "disabled"; 2439 compatible = "amlogic,meson-g12a-usb-ctrl"; 2440 reg = <0x0 0xffe09000 0x0 0xa0>; 2441 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2442 #address-cells = <2>; 2443 #size-cells = <2>; 2444 ranges; 2445 2446 clocks = <&clkc CLKID_USB>; 2447 resets = <&reset RESET_USB>; 2448 2449 dr_mode = "otg"; 2450 2451 phys = <&usb2_phy0>, <&usb2_phy1>, 2452 <&usb3_pcie_phy PHY_TYPE_USB3>; 2453 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2454 2455 dwc2: usb@ff400000 { 2456 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2457 reg = <0x0 0xff400000 0x0 0x40000>; 2458 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2459 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2460 clock-names = "otg"; 2461 phys = <&usb2_phy1>; 2462 phy-names = "usb2-phy"; 2463 dr_mode = "peripheral"; 2464 g-rx-fifo-size = <192>; 2465 g-np-tx-fifo-size = <128>; 2466 g-tx-fifo-size = <128 128 16 16 16>; 2467 }; 2468 2469 dwc3: usb@ff500000 { 2470 compatible = "snps,dwc3"; 2471 reg = <0x0 0xff500000 0x0 0x100000>; 2472 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2473 dr_mode = "host"; 2474 snps,dis_u2_susphy_quirk; 2475 snps,quirk-frame-length-adjustment = <0x20>; 2476 snps,parkmode-disable-ss-quirk; 2477 }; 2478 }; 2479 2480 mali: gpu@ffe40000 { 2481 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2482 reg = <0x0 0xffe40000 0x0 0x40000>; 2483 interrupt-parent = <&gic>; 2484 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2487 interrupt-names = "job", "mmu", "gpu"; 2488 clocks = <&clkc CLKID_MALI>; 2489 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2490 operating-points-v2 = <&gpu_opp_table>; 2491 #cooling-cells = <2>; 2492 }; 2493 }; 2494 2495 thermal-zones { 2496 cpu_thermal: cpu-thermal { 2497 polling-delay = <1000>; 2498 polling-delay-passive = <100>; 2499 thermal-sensors = <&cpu_temp>; 2500 2501 trips { 2502 cpu_passive: cpu-passive { 2503 temperature = <85000>; /* millicelsius */ 2504 hysteresis = <2000>; /* millicelsius */ 2505 type = "passive"; 2506 }; 2507 2508 cpu_hot: cpu-hot { 2509 temperature = <95000>; /* millicelsius */ 2510 hysteresis = <2000>; /* millicelsius */ 2511 type = "hot"; 2512 }; 2513 2514 cpu_critical: cpu-critical { 2515 temperature = <110000>; /* millicelsius */ 2516 hysteresis = <2000>; /* millicelsius */ 2517 type = "critical"; 2518 }; 2519 }; 2520 }; 2521 2522 ddr_thermal: ddr-thermal { 2523 polling-delay = <1000>; 2524 polling-delay-passive = <100>; 2525 thermal-sensors = <&ddr_temp>; 2526 2527 trips { 2528 ddr_passive: ddr-passive { 2529 temperature = <85000>; /* millicelsius */ 2530 hysteresis = <2000>; /* millicelsius */ 2531 type = "passive"; 2532 }; 2533 2534 ddr_critical: ddr-critical { 2535 temperature = <110000>; /* millicelsius */ 2536 hysteresis = <2000>; /* millicelsius */ 2537 type = "critical"; 2538 }; 2539 }; 2540 2541 cooling-maps { 2542 map { 2543 trip = <&ddr_passive>; 2544 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2545 }; 2546 }; 2547 }; 2548 }; 2549 2550 timer { 2551 compatible = "arm,armv8-timer"; 2552 interrupts = <GIC_PPI 13 2553 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2554 <GIC_PPI 14 2555 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2556 <GIC_PPI 11 2557 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2558 <GIC_PPI 10 2559 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2560 arm,no-tick-in-suspend; 2561 }; 2562 2563 xtal: xtal-clk { 2564 compatible = "fixed-clock"; 2565 clock-frequency = <24000000>; 2566 clock-output-names = "xtal"; 2567 #clock-cells = <0>; 2568 }; 2569 2570 npu: npu@ff100000 { 2571 compatible = "vivante,gc"; 2572 reg = <0x0 0xff100000 0x0 0x20000>; 2573 interrupts = <0 147 4>; 2574 clocks = <&clkc CLKID_NNA_CORE_CLK>, 2575 <&clkc CLKID_NNA_AXI_CLK>; 2576 clock-names = "core", "bus"; 2577 assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>, 2578 <&clkc CLKID_NNA_AXI_CLK>; 2579 assigned-clock-rates = <800000000>, <800000000>; 2580 resets = <&reset RESET_NNA>; 2581 status = "disabled"; 2582 }; 2583}; 2584