1// SPDX-License-Identifier: GPL-2.0+ 2(* 3 * Copyright (C) 2015 Jade Alglave <j.alglave@ucl.ac.uk>, 4 * Copyright (C) 2016 Luc Maranget <luc.maranget@inria.fr> for Inria 5 * Copyright (C) 2017 Alan Stern <stern@rowland.harvard.edu>, 6 * Andrea Parri <parri.andrea@gmail.com> 7 * 8 * An earlier version of this file appeared in the companion webpage for 9 * "Frightening small children and disconcerting grown-ups: Concurrency 10 * in the Linux kernel" by Alglave, Maranget, McKenney, Parri, and Stern, 11 * which appeared in ASPLOS 2018. 12 *) 13 14"Linux-kernel memory consistency model" 15 16(* 17 * File "lock.cat" handles locks and is experimental. 18 * It can be replaced by include "cos.cat" for tests that do not use locks. 19 *) 20 21include "lock.cat" 22 23(*******************) 24(* Basic relations *) 25(*******************) 26 27(* Release Acquire *) 28let acq-po = [Acquire] ; po ; [M] 29let po-rel = [M] ; po ; [Release] 30let po-unlock-lock-po = po ; [UL] ; (po|rf) ; [LKR] ; po 31 32(* Fences *) 33let R4rmb = R \ Noreturn (* Reads for which rmb works *) 34let rmb = [R4rmb] ; fencerel(Rmb) ; [R4rmb] 35let wmb = [W] ; fencerel(Wmb) ; [W] 36let mb = ([M] ; fencerel(Mb) ; [M]) | 37 (* 38 * full-barrier RMWs (successful cmpxchg(), xchg(), etc.) act as 39 * though there were enclosed by smp_mb(). 40 * The effect of these virtual smp_mb() is formalized by adding 41 * Mb tags to the read and write of the operation, and providing 42 * the same ordering as though there were additional po edges 43 * between the Mb tag and the read resp. write. 44 *) 45 ([M] ; po ; [Mb & R]) | 46 ([Mb & W] ; po ; [M]) | 47 ([M] ; fencerel(Before-atomic) ; [RMW] ; po? ; [M]) | 48 ([M] ; po? ; [RMW] ; fencerel(After-atomic) ; [M]) | 49 ([M] ; po? ; [LKW] ; fencerel(After-spinlock) ; [M]) | 50(* 51 * Note: The po-unlock-lock-po relation only passes the lock to the direct 52 * successor, perhaps giving the impression that the ordering of the 53 * smp_mb__after_unlock_lock() fence only affects a single lock handover. 54 * However, in a longer sequence of lock handovers, the implicit 55 * A-cumulative release fences of lock-release ensure that any stores that 56 * propagate to one of the involved CPUs before it hands over the lock to 57 * the next CPU will also propagate to the final CPU handing over the lock 58 * to the CPU that executes the fence. Therefore, all those stores are 59 * also affected by the fence. 60 *) 61 ([M] ; po-unlock-lock-po ; 62 [After-unlock-lock] ; po ; [M]) | 63 ([M] ; po? ; [Srcu-unlock] ; fencerel(After-srcu-read-unlock) ; [M]) 64let gp = po ; [Sync-rcu | Sync-srcu] ; po? 65let strong-fence = mb | gp 66 67let nonrw-fence = strong-fence | po-rel | acq-po 68let fence = nonrw-fence | wmb | rmb 69let barrier = fencerel(Barrier | Rmb | Wmb | Mb | Sync-rcu | Sync-srcu | 70 Before-atomic | After-atomic | Acquire | Release | 71 Rcu-lock | Rcu-unlock | Srcu-lock | Srcu-unlock) | 72 (po ; [Release]) | ([Acquire] ; po) 73 74(**********************************) 75(* Fundamental coherence ordering *) 76(**********************************) 77 78(* Sequential Consistency Per Variable *) 79let com = rf | co | fr 80acyclic po-loc | com as coherence 81 82(* Atomic Read-Modify-Write *) 83empty rmw & (fre ; coe) as atomic 84 85(**********************************) 86(* Instruction execution ordering *) 87(**********************************) 88 89(* Preserved Program Order *) 90let dep = addr | data 91let rwdep = (dep | ctrl) ; [W] 92let overwrite = co | fr 93let to-w = rwdep | (overwrite & int) | (addr ; [Plain] ; wmb) 94let to-r = (addr ; [R]) | (dep ; [Marked] ; rfi) 95let ppo = to-r | to-w | (fence & int) | (po-unlock-lock-po & int) 96 97(* Propagation: Ordering from release operations and strong fences. *) 98let A-cumul(r) = (rfe ; [Marked])? ; r 99let rmw-sequence = (rf ; rmw)* 100let cumul-fence = [Marked] ; (A-cumul(strong-fence | po-rel) | wmb | 101 po-unlock-lock-po) ; [Marked] ; rmw-sequence 102let prop = [Marked] ; (overwrite & ext)? ; cumul-fence* ; 103 [Marked] ; rfe? ; [Marked] 104 105(* 106 * Happens Before: Ordering from the passage of time. 107 * No fences needed here for prop because relation confined to one process. 108 *) 109let hb = [Marked] ; (ppo | rfe | ((prop \ id) & int)) ; [Marked] 110acyclic hb as happens-before 111 112(****************************************) 113(* Write and fence propagation ordering *) 114(****************************************) 115 116(* Propagation: Each non-rf link needs a strong fence. *) 117let pb = prop ; strong-fence ; hb* ; [Marked] 118acyclic pb as propagation 119 120(*******) 121(* RCU *) 122(*******) 123 124(* 125 * Effects of read-side critical sections proceed from the rcu_read_unlock() 126 * or srcu_read_unlock() backwards on the one hand, and from the 127 * rcu_read_lock() or srcu_read_lock() forwards on the other hand. 128 * 129 * In the definition of rcu-fence below, the po term at the left-hand side 130 * of each disjunct and the po? term at the right-hand end have been factored 131 * out. They have been moved into the definitions of rcu-link and rb. 132 * This was necessary in order to apply the "& loc" tests correctly. 133 *) 134let rcu-gp = [Sync-rcu] (* Compare with gp *) 135let srcu-gp = [Sync-srcu] 136let rcu-rscsi = rcu-rscs^-1 137let srcu-rscsi = srcu-rscs^-1 138 139(* 140 * The synchronize_rcu() strong fence is special in that it can order not 141 * one but two non-rf relations, but only in conjunction with an RCU 142 * read-side critical section. 143 *) 144let rcu-link = po? ; hb* ; pb* ; prop ; po 145 146(* 147 * Any sequence containing at least as many grace periods as RCU read-side 148 * critical sections (joined by rcu-link) induces order like a generalized 149 * inter-CPU strong fence. 150 * Likewise for SRCU grace periods and read-side critical sections, provided 151 * the synchronize_srcu() and srcu_read_[un]lock() calls refer to the same 152 * struct srcu_struct location. 153 *) 154let rec rcu-order = rcu-gp | srcu-gp | 155 (rcu-gp ; rcu-link ; rcu-rscsi) | 156 ((srcu-gp ; rcu-link ; srcu-rscsi) & loc) | 157 (rcu-rscsi ; rcu-link ; rcu-gp) | 158 ((srcu-rscsi ; rcu-link ; srcu-gp) & loc) | 159 (rcu-gp ; rcu-link ; rcu-order ; rcu-link ; rcu-rscsi) | 160 ((srcu-gp ; rcu-link ; rcu-order ; rcu-link ; srcu-rscsi) & loc) | 161 (rcu-rscsi ; rcu-link ; rcu-order ; rcu-link ; rcu-gp) | 162 ((srcu-rscsi ; rcu-link ; rcu-order ; rcu-link ; srcu-gp) & loc) | 163 (rcu-order ; rcu-link ; rcu-order) 164let rcu-fence = po ; rcu-order ; po? 165let fence = fence | rcu-fence 166let strong-fence = strong-fence | rcu-fence 167 168(* rb orders instructions just as pb does *) 169let rb = prop ; rcu-fence ; hb* ; pb* ; [Marked] 170 171irreflexive rb as rcu 172 173(* 174 * The happens-before, propagation, and rcu constraints are all 175 * expressions of temporal ordering. They could be replaced by 176 * a single constraint on an "executes-before" relation, xb: 177 * 178 * let xb = hb | pb | rb 179 * acyclic xb as executes-before 180 *) 181 182(*********************************) 183(* Plain accesses and data races *) 184(*********************************) 185 186(* Warn about plain writes and marked accesses in the same region *) 187let mixed-accesses = ([Plain & W] ; (po-loc \ barrier) ; [Marked]) | 188 ([Marked] ; (po-loc \ barrier) ; [Plain & W]) 189flag ~empty mixed-accesses as mixed-accesses 190 191(* Executes-before and visibility *) 192let xbstar = (hb | pb | rb)* 193let vis = cumul-fence* ; rfe? ; [Marked] ; 194 ((strong-fence ; [Marked] ; xbstar) | (xbstar & int)) 195 196(* Boundaries for lifetimes of plain accesses *) 197let w-pre-bounded = [Marked] ; (addr | fence)? 198let r-pre-bounded = [Marked] ; (addr | nonrw-fence | 199 ([R4rmb] ; fencerel(Rmb) ; [~Noreturn]))? 200let w-post-bounded = fence? ; [Marked] ; rmw-sequence 201let r-post-bounded = (nonrw-fence | ([~Noreturn] ; fencerel(Rmb) ; [R4rmb]))? ; 202 [Marked] 203 204(* Visibility and executes-before for plain accesses *) 205let ww-vis = fence | (strong-fence ; xbstar ; w-pre-bounded) | 206 (w-post-bounded ; vis ; w-pre-bounded) 207let wr-vis = fence | (strong-fence ; xbstar ; r-pre-bounded) | 208 (w-post-bounded ; vis ; r-pre-bounded) 209let rw-xbstar = fence | (r-post-bounded ; xbstar ; w-pre-bounded) 210 211(* Potential races *) 212let pre-race = ext & ((Plain * M) | ((M \ IW) * Plain)) 213 214(* Coherence requirements for plain accesses *) 215let wr-incoh = pre-race & rf & rw-xbstar^-1 216let rw-incoh = pre-race & fr & wr-vis^-1 217let ww-incoh = pre-race & co & ww-vis^-1 218empty (wr-incoh | rw-incoh | ww-incoh) as plain-coherence 219 220(* Actual races *) 221let ww-nonrace = ww-vis & ((Marked * W) | rw-xbstar) & ((W * Marked) | wr-vis) 222let ww-race = (pre-race & co) \ ww-nonrace 223let wr-race = (pre-race & (co? ; rf)) \ wr-vis \ rw-xbstar^-1 224let rw-race = (pre-race & fr) \ rw-xbstar 225 226flag ~empty (ww-race | wr-race | rw-race) as data-race 227