1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #include <asm/cpufeature.h> 3 4 extern struct xor_block_template xor_block_pII_mmx; 5 extern struct xor_block_template xor_block_p5_mmx; 6 extern struct xor_block_template xor_block_sse; 7 extern struct xor_block_template xor_block_sse_pf64; 8 extern struct xor_block_template xor_block_avx; 9 extern struct xor_block_template xor_block_avx512; 10 arch_xor_init(void)11static __always_inline void __init arch_xor_init(void) 12 { 13 if (IS_ENABLED(CONFIG_X86_64) && boot_cpu_has(X86_FEATURE_AVX512F) && 14 !boot_cpu_has(X86_FEATURE_PREFER_YMM)) { 15 /* 16 * Use the AVX-512 code on CPUs that support AVX-512 without 17 * overly-eager downclocking. On such CPUs the AVX-512 code 18 * should always work at least as well as the AVX code, so 19 * runtime selection is unnecessary. 20 * 21 * The AVX-512 code can work on X86_32. However, due to lack of 22 * use case for that, for now it's built only for X86_64. 23 */ 24 xor_force(&xor_block_avx512); 25 } else if (boot_cpu_has(X86_FEATURE_AVX)) { 26 /* AVX will be the best; no need to try others. */ 27 xor_force(&xor_block_avx); 28 } else if (IS_ENABLED(CONFIG_X86_64) || boot_cpu_has(X86_FEATURE_XMM)) { 29 /* 30 * When SSE is available, use it as it can write around L2. We 31 * may also be able to load into the L1 only depending on how 32 * the cpu deals with a load to a line that is being prefetched. 33 */ 34 xor_register(&xor_block_sse); 35 xor_register(&xor_block_sse_pf64); 36 } else if (boot_cpu_has(X86_FEATURE_MMX)) { 37 xor_register(&xor_block_pII_mmx); 38 xor_register(&xor_block_p5_mmx); 39 } else { 40 xor_register(&xor_block_8regs); 41 xor_register(&xor_block_8regs_p); 42 xor_register(&xor_block_32regs); 43 xor_register(&xor_block_32regs_p); 44 } 45 } 46