1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * PCI standard defines 4 * Copyright 1994, Drew Eckhardt 5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 6 * 7 * For more information, please consult the following manuals (look at 8 * http://www.pcisig.com/ for how to get them): 9 * 10 * PCI BIOS Specification 11 * PCI Local Bus Specification 12 * PCI to PCI Bridge Specification 13 * PCI System Design Guide 14 * 15 * For HyperTransport information, please consult the following manuals 16 * from http://www.hypertransport.org : 17 * 18 * The HyperTransport I/O Link Specification 19 */ 20 21 #ifndef LINUX_PCI_REGS_H 22 #define LINUX_PCI_REGS_H 23 24 /* 25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of 26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of 27 * configuration space. 28 */ 29 #define PCI_CFG_SPACE_SIZE 256 30 #define PCI_CFG_SPACE_EXP_SIZE 4096 31 32 /* 33 * Under PCI, each device has 256 bytes of configuration address space, 34 * of which the first 64 bytes are standardized as follows: 35 */ 36 #define PCI_STD_HEADER_SIZEOF 64 37 #define PCI_STD_NUM_BARS 6 /* Number of standard BARs */ 38 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 39 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 40 #define PCI_COMMAND 0x04 /* 16 bits */ 41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 48 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 49 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 52 53 #define PCI_STATUS 0x06 /* 16 bits */ 54 #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ 55 #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ 56 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 57 #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ 58 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 60 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 61 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 62 #define PCI_STATUS_DEVSEL_FAST 0x000 63 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 64 #define PCI_STATUS_DEVSEL_SLOW 0x400 65 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 66 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 67 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 68 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 69 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 70 71 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 72 #define PCI_REVISION_ID 0x08 /* Revision ID */ 73 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 74 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 75 76 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 77 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 78 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 79 #define PCI_HEADER_TYPE_MASK 0x7f 80 #define PCI_HEADER_TYPE_NORMAL 0 81 #define PCI_HEADER_TYPE_BRIDGE 1 82 #define PCI_HEADER_TYPE_CARDBUS 2 83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */ 84 85 #define PCI_BIST 0x0f /* 8 bits */ 86 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 87 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 88 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 89 90 /* 91 * Base addresses specify locations in memory or I/O space. 92 * Decoded size can be determined by writing a value of 93 * 0xffffffff to the register, and reading it back. Only 94 * 1 bits are decoded. 95 */ 96 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 97 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 98 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 99 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 100 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 101 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 102 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 103 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 104 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 105 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 106 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 107 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 108 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 109 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 110 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 111 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 112 /* bit 1 is reserved if address_space = 1 */ 113 114 /* Header type 0 (normal devices) */ 115 #define PCI_CARDBUS_CIS 0x28 116 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 117 #define PCI_SUBSYSTEM_ID 0x2e 118 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 119 #define PCI_ROM_ADDRESS_ENABLE 0x01 120 #define PCI_ROM_ADDRESS_MASK (~0x7ffU) 121 122 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 123 124 /* 0x35-0x3b are reserved */ 125 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 126 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 127 #define PCI_MIN_GNT 0x3e /* 8 bits */ 128 #define PCI_MAX_LAT 0x3f /* 8 bits */ 129 130 /* Header type 1 (PCI-to-PCI bridges) */ 131 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 132 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 133 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 134 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 135 /* Masks for dword-sized processing of Bus Number and Sec Latency Timer fields */ 136 #define PCI_PRIMARY_BUS_MASK 0x000000ff 137 #define PCI_SECONDARY_BUS_MASK 0x0000ff00 138 #define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 139 #define PCI_SEC_LATENCY_TIMER_MASK 0xff000000 140 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 141 #define PCI_IO_LIMIT 0x1d 142 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 143 #define PCI_IO_RANGE_TYPE_16 0x00 144 #define PCI_IO_RANGE_TYPE_32 0x01 145 #define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ 146 #define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ 147 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 148 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 149 #define PCI_MEMORY_LIMIT 0x22 150 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 151 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 152 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 153 #define PCI_PREF_MEMORY_LIMIT 0x26 154 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 155 #define PCI_PREF_RANGE_TYPE_32 0x00 156 #define PCI_PREF_RANGE_TYPE_64 0x01 157 #define PCI_PREF_RANGE_MASK (~0x0fUL) 158 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 159 #define PCI_PREF_LIMIT_UPPER32 0x2c 160 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 161 #define PCI_IO_LIMIT_UPPER16 0x32 162 /* 0x34 same as for htype 0 */ 163 /* 0x35-0x3b is reserved */ 164 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 165 /* 0x3c-0x3d are same as for htype 0 */ 166 #define PCI_BRIDGE_CONTROL 0x3e 167 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 168 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 169 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ 170 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 171 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 172 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 173 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 174 175 /* Header type 2 (CardBus bridges) */ 176 #define PCI_CB_CAPABILITY_LIST 0x14 177 /* 0x15 reserved */ 178 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 179 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 180 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 181 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 182 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 183 #define PCI_CB_MEMORY_BASE_0 0x1c 184 #define PCI_CB_MEMORY_LIMIT_0 0x20 185 #define PCI_CB_MEMORY_BASE_1 0x24 186 #define PCI_CB_MEMORY_LIMIT_1 0x28 187 #define PCI_CB_IO_BASE_0 0x2c 188 #define PCI_CB_IO_BASE_0_HI 0x2e 189 #define PCI_CB_IO_LIMIT_0 0x30 190 #define PCI_CB_IO_LIMIT_0_HI 0x32 191 #define PCI_CB_IO_BASE_1 0x34 192 #define PCI_CB_IO_BASE_1_HI 0x36 193 #define PCI_CB_IO_LIMIT_1 0x38 194 #define PCI_CB_IO_LIMIT_1_HI 0x3a 195 #define PCI_CB_IO_RANGE_MASK (~0x03UL) 196 /* 0x3c-0x3d are same as for htype 0 */ 197 #define PCI_CB_BRIDGE_CONTROL 0x3e 198 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 199 #define PCI_CB_BRIDGE_CTL_SERR 0x02 200 #define PCI_CB_BRIDGE_CTL_ISA 0x04 201 #define PCI_CB_BRIDGE_CTL_VGA 0x08 202 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 203 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 204 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 205 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 206 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 207 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 208 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 209 #define PCI_CB_SUBSYSTEM_ID 0x42 210 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 211 /* 0x48-0x7f reserved */ 212 213 /* Capability lists */ 214 215 #define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */ 216 #define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */ 217 218 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 219 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 220 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 221 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 222 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 223 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 224 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 225 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 226 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 227 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 228 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 229 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 230 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 231 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 232 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 233 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 234 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 235 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 236 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 237 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 238 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 239 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 240 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 241 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 242 #define PCI_CAP_SIZEOF 4 243 244 /* Power Management Registers */ 245 246 #define PCI_PM_PMC 2 /* PM Capabilities Register */ 247 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 248 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 249 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 250 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 251 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ 252 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 253 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 254 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 255 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 256 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 257 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 258 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 259 #define PCI_PM_CAP_PME_D3hot 0x4000 /* PME# from D3 (hot) */ 260 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 261 #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ 262 #define PCI_PM_CTRL 4 /* PM control and status register */ 263 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 264 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ 265 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 266 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 267 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 268 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 269 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 270 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 271 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 272 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 273 #define PCI_PM_SIZEOF 8 274 275 /* AGP registers */ 276 277 #define PCI_AGP_VERSION 2 /* BCD version number */ 278 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 279 #define PCI_AGP_STATUS 4 /* Status register */ 280 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 281 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 282 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 283 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 284 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 285 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 286 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 287 #define PCI_AGP_COMMAND 8 /* Control register */ 288 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 289 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 290 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 291 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 292 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 293 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 294 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 295 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 296 #define PCI_AGP_SIZEOF 12 297 298 /* Vital Product Data */ 299 300 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 301 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 302 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 303 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 304 #define PCI_CAP_VPD_SIZEOF 8 305 306 /* Slot Identification */ 307 308 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 309 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 310 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 311 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 312 313 /* Message Signaled Interrupt registers */ 314 315 #define PCI_MSI_FLAGS 0x02 /* Message Control */ 316 #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 317 #define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ 318 #define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ 319 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 320 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ 321 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 322 #define PCI_MSI_ADDRESS_LO 0x04 /* Lower 32 bits */ 323 #define PCI_MSI_ADDRESS_HI 0x08 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 324 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */ 325 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */ 326 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */ 327 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */ 328 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */ 329 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */ 330 331 /* MSI-X registers (in MSI-X capability) */ 332 #define PCI_MSIX_FLAGS 2 /* Message Control */ 333 #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ 334 #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 335 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ 336 #define PCI_MSIX_TABLE 4 /* Table offset */ 337 #define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ 338 #define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ 339 #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ 340 #define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ 341 #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ 342 #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ 343 #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 344 345 /* MSI-X Table entry format (in memory mapped by a BAR) */ 346 #define PCI_MSIX_ENTRY_SIZE 16 347 #define PCI_MSIX_ENTRY_LOWER_ADDR 0x0 /* Message Address */ 348 #define PCI_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */ 349 #define PCI_MSIX_ENTRY_DATA 0x8 /* Message Data */ 350 #define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */ 351 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* Mask Bit */ 352 #define PCI_MSIX_ENTRY_CTRL_ST 0xffff0000 /* Steering Tag */ 353 354 /* CompactPCI Hotswap Register */ 355 356 #define PCI_CHSWP_CSR 2 /* Control and Status Register */ 357 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 358 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 359 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 360 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 361 #define PCI_CHSWP_PI 0x30 /* Programming Interface */ 362 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 363 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 364 365 /* PCI Advanced Feature registers */ 366 367 #define PCI_AF_LENGTH 2 368 #define PCI_AF_CAP 3 369 #define PCI_AF_CAP_TP 0x01 370 #define PCI_AF_CAP_FLR 0x02 371 #define PCI_AF_CTRL 4 372 #define PCI_AF_CTRL_FLR 0x01 373 #define PCI_AF_STATUS 5 374 #define PCI_AF_STATUS_TP 0x01 375 #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ 376 377 /* PCI Enhanced Allocation registers */ 378 379 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ 380 #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 381 #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ 382 #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 383 #define PCI_EA_ES 0x00000007 /* Entry Size */ 384 #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 385 386 /* EA fixed Secondary and Subordinate bus numbers for Bridge */ 387 #define PCI_EA_SEC_BUS_MASK 0xff 388 #define PCI_EA_SUB_BUS_MASK 0xff00 389 #define PCI_EA_SUB_BUS_SHIFT 8 390 391 /* 0-5 map to BARs 0-5 respectively */ 392 #define PCI_EA_BEI_BAR0 0 393 #define PCI_EA_BEI_BAR5 5 394 #define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */ 395 #define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */ 396 #define PCI_EA_BEI_ROM 8 /* Expansion ROM */ 397 /* 9-14 map to VF BARs 0-5 respectively */ 398 #define PCI_EA_BEI_VF_BAR0 9 399 #define PCI_EA_BEI_VF_BAR5 14 400 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */ 401 #define PCI_EA_PP 0x0000ff00 /* Primary Properties */ 402 #define PCI_EA_SP 0x00ff0000 /* Secondary Properties */ 403 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 404 #define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 405 #define PCI_EA_P_IO 0x02 /* I/O Space */ 406 #define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 407 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 408 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 409 #define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 410 #define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 411 /* 0x08-0xfc reserved */ 412 #define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 413 #define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 414 #define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 415 #define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 416 #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */ 417 #define PCI_EA_BASE 4 /* Base Address Offset */ 418 #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 419 /* bit 0 is reserved */ 420 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ 421 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 422 423 /* PCI-X registers (Type 0 (non-bridge) devices) */ 424 425 #define PCI_X_CMD 2 /* Modes & Features */ 426 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 427 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 428 #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ 429 #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ 430 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ 431 #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ 432 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 433 /* Max # of outstanding split transactions */ 434 #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ 435 #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ 436 #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ 437 #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ 438 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ 439 #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ 440 #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 441 #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 442 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 443 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 444 #define PCI_X_STATUS 4 /* PCI-X capabilities */ 445 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 446 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 447 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 448 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 449 #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 450 #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 451 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 452 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 453 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 454 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 455 #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 456 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 457 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 458 #define PCI_X_ECC_CSR 8 /* ECC control and status */ 459 #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ 460 #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ 461 #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ 462 463 /* PCI-X registers (Type 1 (bridge) devices) */ 464 465 #define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ 466 #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ 467 #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ 468 #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ 469 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ 470 #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ 471 #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ 472 #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ 473 #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ 474 #define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ 475 476 /* PCI Bridge Subsystem ID registers */ 477 478 #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ 479 #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ 480 481 /* PCI Express capability registers */ 482 483 #define PCI_EXP_FLAGS 0x02 /* Capabilities register */ 484 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 485 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 486 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 487 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 488 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 489 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 490 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 491 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ 492 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 493 #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ 494 #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 495 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 496 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 497 #define PCI_EXP_FLAGS_FLIT 0x8000 /* Flit Mode Supported */ 498 #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ 499 #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ 500 #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ 501 #define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ 502 #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ 503 #define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ 504 #define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ 505 #define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ 506 #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ 507 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ 508 #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ 509 #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ 510 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 511 #define PCI_EXP_DEVCAP_TEE 0x40000000 /* TEE I/O (TDISP) Support */ 512 #define PCI_EXP_DEVCTL 0x08 /* Device Control */ 513 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 514 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 515 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 516 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 517 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 518 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 519 #define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ 520 #define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ 521 #define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ 522 #define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ 523 #define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ 524 #define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ 525 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 526 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 527 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 528 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 529 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 530 #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ 531 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ 532 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ 533 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ 534 #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ 535 #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ 536 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 537 #define PCI_EXP_DEVSTA 0x0a /* Device Status */ 538 #define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ 539 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ 540 #define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ 541 #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ 542 #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ 543 #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ 544 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */ 545 #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ 546 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Max Link Speed (prior to PCIe r3.0: Supported Link Speeds) */ 547 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ 548 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ 549 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ 550 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ 551 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ 552 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ 553 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 554 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 555 #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ 556 #define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */ 557 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 558 #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 559 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ 560 #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ 561 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 562 #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 563 #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 564 #define PCI_EXP_LNKCTL 0x10 /* Link Control */ 565 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 566 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ 567 #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ 568 #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 569 #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 570 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 571 #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ 572 #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ 573 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ 574 #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 575 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 576 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ 577 #define PCI_EXP_LNKSTA 0x12 /* Link Status */ 578 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 579 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 580 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 581 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 582 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ 583 #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ 584 #define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */ 585 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 586 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 587 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ 588 #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ 589 #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ 590 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 591 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 592 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 593 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 594 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 595 #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 596 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */ 597 #define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */ 598 #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 599 #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 600 #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ 601 #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ 602 #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ 603 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ 604 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ 605 #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ 606 #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ 607 #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ 608 #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ 609 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 610 #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ 611 #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ 612 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ 613 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ 614 #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ 615 #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ 616 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ 617 #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ 618 #define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */ 619 #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ 620 #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ 621 #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ 622 #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ 623 #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ 624 #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ 625 #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ 626 #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ 627 #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ 628 #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ 629 #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ 630 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ 631 #define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */ 632 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */ 633 #define PCI_EXP_SLTSTA 0x1a /* Slot Status */ 634 #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ 635 #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ 636 #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ 637 #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ 638 #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ 639 #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ 640 #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ 641 #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ 642 #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ 643 #define PCI_EXP_RTCTL 0x1c /* Root Control */ 644 #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ 645 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ 646 #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ 647 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ 648 #define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */ 649 #define PCI_EXP_RTCTL_CRSSVE PCI_EXP_RTCTL_RRS_SVE /* compatibility */ 650 #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ 651 #define PCI_EXP_RTCAP_RRS_SV 0x0001 /* Config RRS Software Visibility */ 652 #define PCI_EXP_RTCAP_CRSVIS PCI_EXP_RTCAP_RRS_SV /* compatibility */ 653 #define PCI_EXP_RTSTA 0x20 /* Root Status */ 654 #define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ 655 #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 656 #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 657 /* 658 * The Device Capabilities 2, Device Status 2, Device Control 2, 659 * Link Capabilities 2, Link Status 2, Link Control 2, 660 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers 661 * are only present on devices with PCIe Capability version 2. 662 * Use pcie_capability_read_word() and similar interfaces to use them 663 * safely. 664 */ 665 #define PCI_EXP_DEVCAP2 0x24 /* Device Capabilities 2 */ 666 #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ 667 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ 668 #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ 669 #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ 670 #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ 671 #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ 672 #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ 673 #define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support */ 674 #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 675 #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 676 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 677 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ 678 #define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefixes */ 679 #define PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */ 680 #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 681 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ 682 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 683 #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ 684 #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ 685 #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 686 #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 687 #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 688 #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ 689 #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ 690 #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 691 #define PCI_EXP_DEVSTA2 0x2a /* Device Status 2 */ 692 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c /* end of v2 EPs w/o link */ 693 #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities 2 */ 694 #define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */ 695 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ 696 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ 697 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ 698 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ 699 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ 700 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */ 701 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 702 #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ 703 #define PCI_EXP_LNKCTL2_TLS 0x000f 704 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 705 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 706 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 707 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 708 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 709 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 710 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 711 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 712 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ 713 #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ 714 #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ 715 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ 716 #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ 717 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ 718 #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */ 719 #define PCI_EXP_SLTSTA2 0x3a /* Slot Status 2 */ 720 721 /* Extended Capabilities (PCI-X 2.0 and Express) */ 722 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 723 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 724 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 725 726 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 727 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 728 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 729 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 730 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 731 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 732 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 733 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 734 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 735 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 736 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 737 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 738 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 739 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 740 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 741 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 742 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 743 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 744 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 745 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 746 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 747 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 748 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 749 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 750 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 751 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 752 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 753 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ 754 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ 755 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ 756 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ 757 #define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ 758 #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ 759 #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ 760 #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ 761 #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ 762 #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ 763 #define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ 764 #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ 765 #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ 766 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT 767 768 #define PCI_EXT_CAP_DSN_SIZEOF 12 769 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 770 771 /* Advanced Error Reporting */ 772 #define PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ 773 #define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ 774 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 775 #define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ 776 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 777 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 778 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 779 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 780 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 781 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 782 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 783 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 784 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 785 #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ 786 #define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ 787 #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ 788 #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ 789 #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ 790 #define PCI_ERR_UNC_POISON_BLK 0x04000000 /* Poisoned TLP Egress Blocked */ 791 #define PCI_ERR_UNC_DMWR_BLK 0x08000000 /* DMWr Request Egress Blocked */ 792 #define PCI_ERR_UNC_IDE_CHECK 0x10000000 /* IDE Check Failed */ 793 #define PCI_ERR_UNC_MISR_IDE 0x20000000 /* Misrouted IDE TLP */ 794 #define PCI_ERR_UNC_PCRC_CHECK 0x40000000 /* PCRC Check Failed */ 795 #define PCI_ERR_UNC_XLAT_BLK 0x80000000 /* TLP Translation Egress Blocked */ 796 #define PCI_ERR_UNCOR_MASK 0x08 /* Uncorrectable Error Mask */ 797 /* Same bits as above */ 798 #define PCI_ERR_UNCOR_SEVER 0x0c /* Uncorrectable Error Severity */ 799 /* Same bits as above */ 800 #define PCI_ERR_COR_STATUS 0x10 /* Correctable Error Status */ 801 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 802 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 803 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 804 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 805 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 806 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ 807 #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ 808 #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ 809 #define PCI_ERR_COR_MASK 0x14 /* Correctable Error Mask */ 810 /* Same bits as above */ 811 #define PCI_ERR_CAP 0x18 /* Advanced Error Capabilities & Ctrl*/ 812 #define PCI_ERR_CAP_FEP(x) ((x) & 0x1f) /* First Error Pointer */ 813 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 814 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 815 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 816 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 817 #define PCI_ERR_CAP_PREFIX_LOG_PRESENT 0x00000800 /* TLP Prefix Log Present */ 818 #define PCI_ERR_CAP_COMP_TIME_LOG 0x00001000 /* Completion Timeout Prefix/Header Log Capable */ 819 #define PCI_ERR_CAP_TLP_LOG_FLIT 0x00040000 /* TLP was logged in Flit Mode */ 820 #define PCI_ERR_CAP_TLP_LOG_SIZE 0x00f80000 /* Logged TLP Size (only in Flit mode) */ 821 #define PCI_ERR_HEADER_LOG 0x1c /* Header Log Register (16 bytes) */ 822 #define PCI_ERR_ROOT_COMMAND 0x2c /* Root Error Command */ 823 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ 824 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ 825 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ 826 #define PCI_ERR_ROOT_STATUS 0x30 827 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 828 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ 829 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ 830 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ 831 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ 832 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 833 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 834 #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ 835 #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ 836 #define PCI_ERR_PREFIX_LOG 0x38 /* TLP Prefix LOG Register (up to 16 bytes) */ 837 838 /* Virtual Channel */ 839 #define PCI_VC_PORT_CAP1 0x04 840 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ 841 #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ 842 #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 843 #define PCI_VC_PORT_CAP2 0x08 844 #define PCI_VC_CAP2_32_PHASE 0x00000002 845 #define PCI_VC_CAP2_64_PHASE 0x00000004 846 #define PCI_VC_CAP2_128_PHASE 0x00000008 847 #define PCI_VC_CAP2_ARB_OFF 0xff000000 848 #define PCI_VC_PORT_CTRL 0x0c 849 #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 850 #define PCI_VC_PORT_STATUS 0x0e 851 #define PCI_VC_PORT_STATUS_TABLE 0x00000001 852 #define PCI_VC_RES_CAP 0x10 853 #define PCI_VC_RES_CAP_32_PHASE 0x00000002 854 #define PCI_VC_RES_CAP_64_PHASE 0x00000004 855 #define PCI_VC_RES_CAP_128_PHASE 0x00000008 856 #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 857 #define PCI_VC_RES_CAP_256_PHASE 0x00000020 858 #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 859 #define PCI_VC_RES_CTRL 0x14 860 #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 861 #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 862 #define PCI_VC_RES_CTRL_ID 0x07000000 863 #define PCI_VC_RES_CTRL_ENABLE 0x80000000 864 #define PCI_VC_RES_STATUS 0x1a 865 #define PCI_VC_RES_STATUS_TABLE 0x00000001 866 #define PCI_VC_RES_STATUS_NEGO 0x00000002 867 #define PCI_CAP_VC_BASE_SIZEOF 0x10 868 #define PCI_CAP_VC_PER_VC_SIZEOF 0x0c 869 870 /* Power Budgeting */ 871 #define PCI_PWR_DSR 0x04 /* Data Select Register */ 872 #define PCI_PWR_DATA 0x08 /* Data Register */ 873 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 874 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 875 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 876 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 877 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 878 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 879 #define PCI_PWR_CAP 0x0c /* Capability */ 880 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 881 #define PCI_EXT_CAP_PWR_SIZEOF 0x10 882 883 /* Root Complex Event Collector Endpoint Association */ 884 #define PCI_RCEC_RCIEP_BITMAP 4 /* Associated Bitmap for RCiEPs */ 885 #define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */ 886 #define PCI_RCEC_BUSN_REG_VER 0x02 /* Least version with BUSN present */ 887 #define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff) 888 #define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff) 889 890 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ 891 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ 892 #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 893 #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 894 #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 895 896 /* 897 * HyperTransport sub capability types 898 * 899 * Unfortunately there are both 3 bit and 5 bit capability types defined 900 * in the HT spec, catering for that is a little messy. You probably don't 901 * want to use these directly, just use pci_find_ht_capability() and it 902 * will do the right thing for you. 903 */ 904 #define HT_3BIT_CAP_MASK 0xE0 905 #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ 906 #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ 907 908 #define HT_5BIT_CAP_MASK 0xF8 909 #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ 910 #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ 911 #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ 912 #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ 913 #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ 914 #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ 915 #define HT_MSI_FLAGS 0x02 /* Offset to flags */ 916 #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ 917 #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ 918 #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ 919 #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ 920 #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ 921 #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ 922 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 923 #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 924 #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 925 #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ 926 #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ 927 #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ 928 #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ 929 930 /* Alternative Routing-ID Interpretation */ 931 #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ 932 #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ 933 #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ 934 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ 935 #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ 936 #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 937 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 938 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 939 #define PCI_EXT_CAP_ARI_SIZEOF 8 940 941 /* Address Translation Service */ 942 #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ 943 #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ 944 #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ 945 #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */ 946 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ 947 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ 948 #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ 949 #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 950 #define PCI_EXT_CAP_ATS_SIZEOF 8 951 952 /* Page Request Interface */ 953 #define PCI_PRI_CTRL 0x04 /* PRI control register */ 954 #define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ 955 #define PCI_PRI_CTRL_RESET 0x0002 /* Reset */ 956 #define PCI_PRI_STATUS 0x06 /* PRI status register */ 957 #define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ 958 #define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ 959 #define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ 960 #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ 961 #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 962 #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 963 #define PCI_EXT_CAP_PRI_SIZEOF 16 964 965 /* Process Address Space ID */ 966 #define PCI_PASID_CAP 0x04 /* PASID feature register */ 967 #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ 968 #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ 969 #define PCI_PASID_CAP_WIDTH 0x1f00 970 #define PCI_PASID_CTRL 0x06 /* PASID control register */ 971 #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ 972 #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ 973 #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ 974 #define PCI_EXT_CAP_PASID_SIZEOF 8 975 976 /* Single Root I/O Virtualization */ 977 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 978 #define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */ 979 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 980 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 981 #define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */ 982 #define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */ 983 #define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */ 984 #define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */ 985 #define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ 986 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 987 #define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */ 988 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 989 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 990 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 991 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 992 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 993 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 994 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 995 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 996 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 997 #define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ 998 #define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ 999 #define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ 1000 #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ 1001 #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ 1002 #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ 1003 #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ 1004 #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ 1005 #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ 1006 #define PCI_EXT_CAP_SRIOV_SIZEOF 0x40 1007 1008 #define PCI_LTR_MAX_SNOOP_LAT 0x4 1009 #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 1010 #define PCI_LTR_VALUE_MASK 0x000003ff 1011 #define PCI_LTR_SCALE_MASK 0x00001c00 1012 #define PCI_LTR_SCALE_SHIFT 10 1013 #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */ 1014 #define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */ 1015 #define PCI_EXT_CAP_LTR_SIZEOF 8 1016 1017 /* Access Control Service */ 1018 #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 1019 #define PCI_ACS_SV 0x0001 /* Source Validation */ 1020 #define PCI_ACS_TB 0x0002 /* Translation Blocking */ 1021 #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ 1022 #define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ 1023 #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ 1024 #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ 1025 #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ 1026 #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ 1027 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 1028 #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 1029 1030 /* SATA capability */ 1031 #define PCI_SATA_REGS 4 /* SATA REGs specifier */ 1032 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ 1033 #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ 1034 #define PCI_SATA_SIZEOF_SHORT 8 1035 #define PCI_SATA_SIZEOF_LONG 16 1036 1037 /* Resizable BARs */ 1038 #define PCI_REBAR_CAP 4 /* capability register */ 1039 #define PCI_REBAR_CAP_SIZES 0xFFFFFFF0 /* supported BAR sizes */ 1040 #define PCI_REBAR_CTRL 8 /* control register */ 1041 #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ 1042 #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ 1043 #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ 1044 #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ 1045 #define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */ 1046 1047 /* Dynamic Power Allocation */ 1048 #define PCI_DPA_CAP 4 /* capability register */ 1049 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ 1050 #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ 1051 1052 /* TPH Completer Support */ 1053 #define PCI_EXP_DEVCAP2_TPH_COMP_NONE 0x0 /* None */ 1054 #define PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY 0x1 /* TPH only */ 1055 #define PCI_EXP_DEVCAP2_TPH_COMP_EXT_TPH 0x3 /* TPH and Extended TPH */ 1056 1057 /* TPH Requester */ 1058 #define PCI_TPH_CAP 4 /* capability register */ 1059 #define PCI_TPH_CAP_ST_NS 0x00000001 /* No ST Mode Supported */ 1060 #define PCI_TPH_CAP_ST_IV 0x00000002 /* Interrupt Vector Mode Supported */ 1061 #define PCI_TPH_CAP_ST_DS 0x00000004 /* Device Specific Mode Supported */ 1062 #define PCI_TPH_CAP_EXT_TPH 0x00000100 /* Ext TPH Requester Supported */ 1063 #define PCI_TPH_CAP_LOC_MASK 0x00000600 /* ST Table Location */ 1064 #define PCI_TPH_LOC_NONE 0x00000000 /* Not present */ 1065 #define PCI_TPH_LOC_CAP 0x00000200 /* In capability */ 1066 #define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */ 1067 #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST Table Size */ 1068 #define PCI_TPH_CAP_ST_SHIFT 16 /* ST Table Size shift */ 1069 #define PCI_TPH_BASE_SIZEOF 0xc /* Size with no ST table */ 1070 1071 #define PCI_TPH_CTRL 8 /* control register */ 1072 #define PCI_TPH_CTRL_MODE_SEL_MASK 0x00000007 /* ST Mode Select */ 1073 #define PCI_TPH_ST_NS_MODE 0x0 /* No ST Mode */ 1074 #define PCI_TPH_ST_IV_MODE 0x1 /* Interrupt Vector Mode */ 1075 #define PCI_TPH_ST_DS_MODE 0x2 /* Device Specific Mode */ 1076 #define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */ 1077 #define PCI_TPH_REQ_DISABLE 0x0 /* No TPH requests allowed */ 1078 #define PCI_TPH_REQ_TPH_ONLY 0x1 /* TPH only requests allowed */ 1079 #define PCI_TPH_REQ_EXT_TPH 0x3 /* Extended TPH requests allowed */ 1080 1081 /* Downstream Port Containment */ 1082 #define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */ 1083 #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ 1084 #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */ 1085 #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */ 1086 #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */ 1087 #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size [3:0] */ 1088 #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ 1089 #define PCI_EXP_DPC_RP_PIO_LOG_SIZE4 0x2000 /* RP PIO Log Size [4] */ 1090 1091 #define PCI_EXP_DPC_CTL 0x06 /* DPC control */ 1092 #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ 1093 #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ 1094 #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ 1095 1096 #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ 1097 #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ 1098 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ 1099 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ 1100 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ 1101 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ 1102 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ 1103 #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ 1104 #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ 1105 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ 1106 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ 1107 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ 1108 #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ 1109 1110 #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ 1111 1112 #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ 1113 #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */ 1114 #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ 1115 #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ 1116 #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ 1117 #define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */ 1118 #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */ 1119 #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */ 1120 1121 /* Precision Time Measurement */ 1122 #define PCI_PTM_CAP 0x04 /* PTM Capability */ 1123 #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ 1124 #define PCI_PTM_CAP_RES 0x00000002 /* Responder capable */ 1125 #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ 1126 #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ 1127 #define PCI_PTM_CTRL 0x08 /* PTM Control */ 1128 #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ 1129 #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ 1130 1131 /* ASPM L1 PM Substates */ 1132 #define PCI_L1SS_CAP 0x04 /* Capabilities Register */ 1133 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ 1134 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ 1135 #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ 1136 #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ 1137 #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ 1138 #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ 1139 #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ 1140 #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ 1141 #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ 1142 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ 1143 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ 1144 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ 1145 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ 1146 #define PCI_L1SS_CTL1_L1_2_MASK 0x00000005 1147 #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f 1148 #define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ 1149 #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ 1150 #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ 1151 #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ 1152 #define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ 1153 #define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ 1154 1155 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ 1156 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ 1157 #define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff) 1158 #define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf) 1159 #define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff) 1160 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ 1161 #define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff) 1162 1163 /* VF Resizable BARs, same layout as PCI_REBAR */ 1164 #define PCI_VF_REBAR_CAP PCI_REBAR_CAP 1165 #define PCI_VF_REBAR_CAP_SIZES PCI_REBAR_CAP_SIZES 1166 #define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL 1167 #define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX 1168 #define PCI_VF_REBAR_CTRL_NBAR_MASK PCI_REBAR_CTRL_NBAR_MASK 1169 #define PCI_VF_REBAR_CTRL_BAR_SIZE PCI_REBAR_CTRL_BAR_SIZE 1170 1171 /* Data Link Feature */ 1172 #define PCI_DLF_CAP 0x04 /* Capabilities Register */ 1173 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ 1174 1175 /* Secondary PCIe Capability 8.0 GT/s */ 1176 #define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ 1177 1178 /* Physical Layer 16.0 GT/s */ 1179 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ 1180 #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F 1181 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 1182 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 1183 1184 /* Physical Layer 32.0 GT/s */ 1185 #define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ 1186 1187 /* Physical Layer 64.0 GT/s */ 1188 #define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ 1189 1190 /* Native PCIe Enclosure Management */ 1191 #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ 1192 #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ 1193 1194 #define PCI_NPEM_CTRL 0x08 /* NPEM control register */ 1195 #define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */ 1196 1197 /* 1198 * Native PCIe Enclosure Management indication bits and Reset command bit 1199 * are corresponding for capability and control registers. 1200 */ 1201 #define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */ 1202 #define PCI_NPEM_IND_OK 0x00000004 /* OK */ 1203 #define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */ 1204 #define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */ 1205 #define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */ 1206 #define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */ 1207 #define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */ 1208 #define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */ 1209 #define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */ 1210 #define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */ 1211 #define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */ 1212 #define PCI_NPEM_IND_SPEC_0 0x01000000 1213 #define PCI_NPEM_IND_SPEC_1 0x02000000 1214 #define PCI_NPEM_IND_SPEC_2 0x04000000 1215 #define PCI_NPEM_IND_SPEC_3 0x08000000 1216 #define PCI_NPEM_IND_SPEC_4 0x10000000 1217 #define PCI_NPEM_IND_SPEC_5 0x20000000 1218 #define PCI_NPEM_IND_SPEC_6 0x40000000 1219 #define PCI_NPEM_IND_SPEC_7 0x80000000 1220 1221 #define PCI_NPEM_STATUS 0x0c /* NPEM status register */ 1222 #define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */ 1223 1224 /* Data Object Exchange */ 1225 #define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */ 1226 #define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */ 1227 #define PCI_DOE_CAP_INT_MSG_NUM 0x00000ffe /* Interrupt Message Number */ 1228 #define PCI_DOE_CTRL 0x08 /* DOE Control Register */ 1229 #define PCI_DOE_CTRL_ABORT 0x00000001 /* DOE Abort */ 1230 #define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */ 1231 #define PCI_DOE_CTRL_GO 0x80000000 /* DOE Go */ 1232 #define PCI_DOE_STATUS 0x0c /* DOE Status Register */ 1233 #define PCI_DOE_STATUS_BUSY 0x00000001 /* DOE Busy */ 1234 #define PCI_DOE_STATUS_INT_STATUS 0x00000002 /* DOE Interrupt Status */ 1235 #define PCI_DOE_STATUS_ERROR 0x00000004 /* DOE Error */ 1236 #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ 1237 #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ 1238 #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ 1239 #define PCI_DOE_CAP_SIZEOF 0x18 /* Size of DOE register block */ 1240 1241 /* DOE Data Object - note not actually registers */ 1242 #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff 1243 #define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE 0x00ff0000 1244 #define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff 1245 1246 #define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff 1247 #define PCI_DOE_DATA_OBJECT_DISC_REQ_3_VER 0x0000ff00 1248 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff 1249 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE 0x00ff0000 1250 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 1251 1252 /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ 1253 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE 1254 1255 /* Device 3 Extended Capability */ 1256 #define PCI_DEV3_CAP 0x04 /* Device 3 Capabilities Register */ 1257 #define PCI_DEV3_CTL 0x08 /* Device 3 Control Register */ 1258 #define PCI_DEV3_STA 0x0c /* Device 3 Status Register */ 1259 #define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */ 1260 1261 /* Integrity and Data Encryption Extended Capability */ 1262 #define PCI_IDE_CAP 0x04 1263 #define PCI_IDE_CAP_LINK 0x1 /* Link IDE Stream Supported */ 1264 #define PCI_IDE_CAP_SELECTIVE 0x2 /* Selective IDE Streams Supported */ 1265 #define PCI_IDE_CAP_FLOWTHROUGH 0x4 /* Flow-Through IDE Stream Supported */ 1266 #define PCI_IDE_CAP_PARTIAL_HEADER_ENC 0x8 /* Partial Header Encryption Supported */ 1267 #define PCI_IDE_CAP_AGGREGATION 0x10 /* Aggregation Supported */ 1268 #define PCI_IDE_CAP_PCRC 0x20 /* PCRC Supported */ 1269 #define PCI_IDE_CAP_IDE_KM 0x40 /* IDE_KM Protocol Supported */ 1270 #define PCI_IDE_CAP_SEL_CFG 0x80 /* Selective IDE for Config Request Support */ 1271 #define PCI_IDE_CAP_ALG __GENMASK(12, 8) /* Supported Algorithms */ 1272 #define PCI_IDE_CAP_ALG_AES_GCM_256 0 /* AES-GCM 256 key size, 96b MAC */ 1273 #define PCI_IDE_CAP_LINK_TC_NUM __GENMASK(15, 13) /* Link IDE TCs */ 1274 #define PCI_IDE_CAP_SEL_NUM __GENMASK(23, 16) /* Supported Selective IDE Streams */ 1275 #define PCI_IDE_CAP_TEE_LIMITED 0x1000000 /* TEE-Limited Stream Supported */ 1276 #define PCI_IDE_CTL 0x08 1277 #define PCI_IDE_CTL_FLOWTHROUGH_IDE 0x4 /* Flow-Through IDE Stream Enabled */ 1278 1279 #define PCI_IDE_LINK_STREAM_0 0xc /* First Link Stream Register Block */ 1280 #define PCI_IDE_LINK_BLOCK_SIZE 8 1281 /* Link IDE Stream block, up to PCI_IDE_CAP_LINK_TC_NUM */ 1282 #define PCI_IDE_LINK_CTL_0 0x00 /* First Link Control Register Offset in block */ 1283 #define PCI_IDE_LINK_CTL_EN 0x1 /* Link IDE Stream Enable */ 1284 #define PCI_IDE_LINK_CTL_TX_AGGR_NPR __GENMASK(3, 2) /* Tx Aggregation Mode NPR */ 1285 #define PCI_IDE_LINK_CTL_TX_AGGR_PR __GENMASK(5, 4) /* Tx Aggregation Mode PR */ 1286 #define PCI_IDE_LINK_CTL_TX_AGGR_CPL __GENMASK(7, 6) /* Tx Aggregation Mode CPL */ 1287 #define PCI_IDE_LINK_CTL_PCRC_EN 0x100 /* PCRC Enable */ 1288 #define PCI_IDE_LINK_CTL_PART_ENC __GENMASK(13, 10) /* Partial Header Encryption Mode */ 1289 #define PCI_IDE_LINK_CTL_ALG __GENMASK(18, 14) /* Selection from PCI_IDE_CAP_ALG */ 1290 #define PCI_IDE_LINK_CTL_TC __GENMASK(21, 19) /* Traffic Class */ 1291 #define PCI_IDE_LINK_CTL_ID __GENMASK(31, 24) /* Stream ID */ 1292 #define PCI_IDE_LINK_STS_0 0x4 /* First Link Status Register Offset in block */ 1293 #define PCI_IDE_LINK_STS_STATE __GENMASK(3, 0) /* Link IDE Stream State */ 1294 #define PCI_IDE_LINK_STS_IDE_FAIL 0x80000000 /* IDE fail message received */ 1295 1296 /* Selective IDE Stream block, up to PCI_IDE_CAP_SELECTIVE_STREAMS_NUM */ 1297 /* Selective IDE Stream Capability Register */ 1298 #define PCI_IDE_SEL_CAP 0x00 1299 #define PCI_IDE_SEL_CAP_ASSOC_NUM __GENMASK(3, 0) 1300 /* Selective IDE Stream Control Register */ 1301 #define PCI_IDE_SEL_CTL 0x04 1302 #define PCI_IDE_SEL_CTL_EN 0x1 /* Selective IDE Stream Enable */ 1303 #define PCI_IDE_SEL_CTL_TX_AGGR_NPR __GENMASK(3, 2) /* Tx Aggregation Mode NPR */ 1304 #define PCI_IDE_SEL_CTL_TX_AGGR_PR __GENMASK(5, 4) /* Tx Aggregation Mode PR */ 1305 #define PCI_IDE_SEL_CTL_TX_AGGR_CPL __GENMASK(7, 6) /* Tx Aggregation Mode CPL */ 1306 #define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */ 1307 #define PCI_IDE_SEL_CTL_CFG_EN 0x200 /* Selective IDE for Configuration Requests */ 1308 #define PCI_IDE_SEL_CTL_PART_ENC __GENMASK(13, 10) /* Partial Header Encryption Mode */ 1309 #define PCI_IDE_SEL_CTL_ALG __GENMASK(18, 14) /* Selection from PCI_IDE_CAP_ALG */ 1310 #define PCI_IDE_SEL_CTL_TC __GENMASK(21, 19) /* Traffic Class */ 1311 #define PCI_IDE_SEL_CTL_DEFAULT 0x400000 /* Default Stream */ 1312 #define PCI_IDE_SEL_CTL_TEE_LIMITED 0x800000 /* TEE-Limited Stream */ 1313 #define PCI_IDE_SEL_CTL_ID __GENMASK(31, 24) /* Stream ID */ 1314 #define PCI_IDE_SEL_CTL_ID_MAX 255 1315 /* Selective IDE Stream Status Register */ 1316 #define PCI_IDE_SEL_STS 0x08 1317 #define PCI_IDE_SEL_STS_STATE __GENMASK(3, 0) /* Selective IDE Stream State */ 1318 #define PCI_IDE_SEL_STS_STATE_INSECURE 0 1319 #define PCI_IDE_SEL_STS_STATE_SECURE 2 1320 #define PCI_IDE_SEL_STS_IDE_FAIL 0x80000000 /* IDE fail message received */ 1321 /* IDE RID Association Register 1 */ 1322 #define PCI_IDE_SEL_RID_1 0x0c 1323 #define PCI_IDE_SEL_RID_1_LIMIT __GENMASK(23, 8) 1324 /* IDE RID Association Register 2 */ 1325 #define PCI_IDE_SEL_RID_2 0x10 1326 #define PCI_IDE_SEL_RID_2_VALID 0x1 1327 #define PCI_IDE_SEL_RID_2_BASE __GENMASK(23, 8) 1328 #define PCI_IDE_SEL_RID_2_SEG __GENMASK(31, 24) 1329 /* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_ASSOC_NUM */ 1330 #define PCI_IDE_SEL_ADDR_BLOCK_SIZE 12 1331 #define PCI_IDE_SEL_ADDR_1(x) (20 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) 1332 #define PCI_IDE_SEL_ADDR_1_VALID 0x1 1333 #define PCI_IDE_SEL_ADDR_1_BASE_LOW __GENMASK(19, 8) 1334 #define PCI_IDE_SEL_ADDR_1_LIMIT_LOW __GENMASK(31, 20) 1335 /* IDE Address Association Register 2 is "Memory Limit Upper" */ 1336 #define PCI_IDE_SEL_ADDR_2(x) (24 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) 1337 /* IDE Address Association Register 3 is "Memory Base Upper" */ 1338 #define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) 1339 #define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc)) 1340 1341 /* 1342 * Compute Express Link (CXL r4.0, sec 8.1) 1343 * 1344 * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state 1345 * is "disconnected" (CXL r4.0, sec 9.12.3). Re-enumerate these 1346 * registers on downstream link-up events. 1347 */ 1348 1349 /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */ 1350 #define PCI_DVSEC_CXL_DEVICE 0 1351 #define PCI_DVSEC_CXL_CAP 0xA 1352 #define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2) 1353 #define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4) 1354 #define PCI_DVSEC_CXL_CTRL 0xC 1355 #define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2) 1356 #define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) 1357 #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) 1358 #define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0) 1359 #define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1) 1360 #define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28) 1361 #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) 1362 #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) 1363 #define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28) 1364 1365 #define CXL_DVSEC_RANGE_MAX 2 1366 1367 /* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */ 1368 #define PCI_DVSEC_CXL_FUNCTION_MAP 2 1369 1370 /* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */ 1371 #define PCI_DVSEC_CXL_PORT 3 1372 #define PCI_DVSEC_CXL_PORT_CTL 0x0c 1373 #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 1374 1375 /* CXL r4.0, 8.1.6: GPF DVSEC for CXL Port */ 1376 #define PCI_DVSEC_CXL_PORT_GPF 4 1377 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL 0x0C 1378 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0) 1379 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8) 1380 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL 0xE 1381 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0) 1382 #define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8) 1383 1384 /* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */ 1385 #define PCI_DVSEC_CXL_DEVICE_GPF 5 1386 1387 /* CXL r4.0, 8.1.8: Flex Bus DVSEC */ 1388 #define PCI_DVSEC_CXL_FLEXBUS_PORT 7 1389 #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS 0xE 1390 #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE _BITUL(0) 1391 #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM _BITUL(2) 1392 1393 /* CXL r4.0, 8.1.9: Register Locator DVSEC */ 1394 #define PCI_DVSEC_CXL_REG_LOCATOR 8 1395 #define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC 1396 #define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0) 1397 #define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8) 1398 #define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16) 1399 1400 #endif /* LINUX_PCI_REGS_H */ 1401