1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * STM32 Low-Power Timer parent driver. 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com> 6 * Inspired by Benjamin Gaignard's stm32-timers driver 7 */ 8 9 #ifndef _LINUX_STM32_LPTIMER_H_ 10 #define _LINUX_STM32_LPTIMER_H_ 11 12 #include <linux/clk.h> 13 #include <linux/regmap.h> 14 15 #define STM32_LPTIM_ISR 0x00 /* Interrupt and Status Reg */ 16 #define STM32_LPTIM_ICR 0x04 /* Interrupt Clear Reg */ 17 #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ 18 #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ 19 #define STM32_LPTIM_CR 0x10 /* Control Reg */ 20 #define STM32_LPTIM_CMP 0x14 /* Compare Reg (MP25 CCR1) */ 21 #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ 22 #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ 23 #define STM32_LPTIM_CCMR1 0x2C /* Capture/Compare Mode MP25 */ 24 #define STM32_LPTIM_CCR2 0x34 /* Compare Reg2 MP25 */ 25 26 #define STM32_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 - MP25 */ 27 #define STM32_LPTIM_HWCFGR1 0x3F0 /* Hardware configuration register 1 - MP15 */ 28 #define STM32_LPTIM_VERR 0x3F4 /* Version identification register - MP15 */ 29 30 /* STM32_LPTIM_ISR - bit fields */ 31 #define STM32_LPTIM_DIEROK_ARROK (BIT(24) | BIT(4)) /* MP25 */ 32 #define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4)) 33 #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) 34 #define STM32_LPTIM_ARROK BIT(4) 35 #define STM32_LPTIM_CMPOK BIT(3) 36 37 /* STM32_LPTIM_ICR - bit fields */ 38 #define STM32_LPTIM_DIEROKCF_ARROKCF (BIT(24) | BIT(4)) /* MP25 */ 39 #define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4)) 40 #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) 41 #define STM32_LPTIM_ARRMCF BIT(1) 42 43 /* STM32_LPTIM_IER - bit fields */ 44 #define STM32_LPTIM_ARRMIE BIT(1) 45 46 /* STM32_LPTIM_CR - bit fields */ 47 #define STM32_LPTIM_CNTSTRT BIT(2) 48 #define STM32_LPTIM_SNGSTRT BIT(1) 49 #define STM32_LPTIM_ENABLE BIT(0) 50 51 /* STM32_LPTIM_CFGR - bit fields */ 52 #define STM32_LPTIM_ENC BIT(24) 53 #define STM32_LPTIM_COUNTMODE BIT(23) 54 #define STM32_LPTIM_WAVPOL BIT(21) 55 #define STM32_LPTIM_PRESC GENMASK(11, 9) 56 #define STM32_LPTIM_CKPOL GENMASK(2, 1) 57 58 /* STM32_LPTIM_CKPOL */ 59 #define STM32_LPTIM_CKPOL_RISING_EDGE 0 60 #define STM32_LPTIM_CKPOL_FALLING_EDGE 1 61 #define STM32_LPTIM_CKPOL_BOTH_EDGES 2 62 63 /* STM32_LPTIM_ARR */ 64 #define STM32_LPTIM_MAX_ARR 0xFFFF 65 66 /* STM32_LPTIM_CCMR1 */ 67 #define STM32_LPTIM_CC2P GENMASK(19, 18) 68 #define STM32_LPTIM_CC2E BIT(17) 69 #define STM32_LPTIM_CC2SEL BIT(16) 70 #define STM32_LPTIM_CC1P GENMASK(3, 2) 71 #define STM32_LPTIM_CC1E BIT(1) 72 #define STM32_LPTIM_CC1SEL BIT(0) 73 74 /* STM32_LPTIM_HWCFGR1 */ 75 #define STM32_LPTIM_HWCFGR1_ENCODER BIT(16) 76 77 /* STM32_LPTIM_HWCFGR2 */ 78 #define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0) 79 80 /* STM32_LPTIM_VERR */ 81 #define STM32_LPTIM_VERR_23 0x23 /* STM32MP25 */ 82 83 /** 84 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device 85 * @clk: clock reference for this instance 86 * @regmap: register map reference for this instance 87 * @has_encoder: indicates this Low-Power Timer supports encoder mode 88 * @num_cc_chans: indicates the number of capture/compare channels 89 * @version: indicates the major and minor revision of the controller 90 */ 91 struct stm32_lptimer { 92 struct clk *clk; 93 struct regmap *regmap; 94 bool has_encoder; 95 unsigned int num_cc_chans; 96 u32 version; 97 }; 98 99 #endif 100