1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/alignment.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Modifications for ARM processor (c) 1995-2001 Russell King 7 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc. 8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 9 * Copyright (C) 1996, Cygnus Software Technologies Ltd. 10 */ 11 #include <linux/moduleparam.h> 12 #include <linux/compiler.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/debug.h> 15 #include <linux/errno.h> 16 #include <linux/string.h> 17 #include <linux/proc_fs.h> 18 #include <linux/seq_file.h> 19 #include <linux/init.h> 20 #include <linux/sched/signal.h> 21 #include <linux/uaccess.h> 22 #include <linux/unaligned.h> 23 24 #include <asm/cp15.h> 25 #include <asm/system_info.h> 26 #include <asm/system_misc.h> 27 #include <asm/opcodes.h> 28 29 #include "fault.h" 30 #include "mm.h" 31 32 /* 33 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 34 * /proc/sys/debug/alignment, modified and integrated into 35 * Linux 2.1 by Russell King 36 * 37 * Speed optimisations and better fault handling by Russell King. 38 * 39 * *** NOTE *** 40 * This code is not portable to processors with late data abort handling. 41 */ 42 #define CODING_BITS(i) (i & 0x0e000000) 43 #define COND_BITS(i) (i & 0xf0000000) 44 45 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ 46 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ 47 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */ 48 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */ 49 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */ 50 51 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) 52 53 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ 54 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ 55 56 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */ 57 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */ 58 #define RM_BITS(i) (i & 15) /* Rm */ 59 60 #define REGMASK_BITS(i) (i & 0xffff) 61 #define OFFSET_BITS(i) (i & 0x0fff) 62 63 #define IS_SHIFT(i) (i & 0x0ff0) 64 #define SHIFT_BITS(i) ((i >> 7) & 0x1f) 65 #define SHIFT_TYPE(i) (i & 0x60) 66 #define SHIFT_LSL 0x00 67 #define SHIFT_LSR 0x20 68 #define SHIFT_ASR 0x40 69 #define SHIFT_RORRRX 0x60 70 71 #define BAD_INSTR 0xdeadc0de 72 73 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ 74 #define IS_T32(hi16) \ 75 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800)) 76 77 static unsigned long ai_user; 78 static unsigned long ai_sys; 79 static void *ai_sys_last_pc; 80 static unsigned long ai_skipped; 81 static unsigned long ai_half; 82 static unsigned long ai_word; 83 static unsigned long ai_dword; 84 static unsigned long ai_multi; 85 static int ai_usermode; 86 static unsigned long cr_no_alignment; 87 88 core_param(alignment, ai_usermode, int, 0600); 89 90 #define UM_WARN (1 << 0) 91 #define UM_FIXUP (1 << 1) 92 #define UM_SIGNAL (1 << 2) 93 94 /* Return true if and only if the ARMv6 unaligned access model is in use. */ 95 static bool cpu_is_v6_unaligned(void) 96 { 97 return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U; 98 } 99 100 static int safe_usermode(int new_usermode, bool warn) 101 { 102 /* 103 * ARMv6 and later CPUs can perform unaligned accesses for 104 * most single load and store instructions up to word size. 105 * LDM, STM, LDRD and STRD still need to be handled. 106 * 107 * Ignoring the alignment fault is not an option on these 108 * CPUs since we spin re-faulting the instruction without 109 * making any progress. 110 */ 111 if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) { 112 new_usermode |= UM_FIXUP; 113 114 if (warn) 115 pr_warn("alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n"); 116 } 117 118 return new_usermode; 119 } 120 121 #ifdef CONFIG_PROC_FS 122 static const char *usermode_action[] = { 123 "ignored", 124 "warn", 125 "fixup", 126 "fixup+warn", 127 "signal", 128 "signal+warn" 129 }; 130 131 static int alignment_proc_show(struct seq_file *m, void *v) 132 { 133 seq_printf(m, "User:\t\t%lu\n", ai_user); 134 seq_printf(m, "System:\t\t%lu (%pS)\n", ai_sys, ai_sys_last_pc); 135 seq_printf(m, "Skipped:\t%lu\n", ai_skipped); 136 seq_printf(m, "Half:\t\t%lu\n", ai_half); 137 seq_printf(m, "Word:\t\t%lu\n", ai_word); 138 if (cpu_architecture() >= CPU_ARCH_ARMv5TE) 139 seq_printf(m, "DWord:\t\t%lu\n", ai_dword); 140 seq_printf(m, "Multi:\t\t%lu\n", ai_multi); 141 seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode, 142 usermode_action[ai_usermode]); 143 144 return 0; 145 } 146 147 static int alignment_proc_open(struct inode *inode, struct file *file) 148 { 149 return single_open(file, alignment_proc_show, NULL); 150 } 151 152 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer, 153 size_t count, loff_t *pos) 154 { 155 char mode; 156 157 if (count > 0) { 158 if (get_user(mode, buffer)) 159 return -EFAULT; 160 if (mode >= '0' && mode <= '5') 161 ai_usermode = safe_usermode(mode - '0', true); 162 } 163 return count; 164 } 165 166 static const struct proc_ops alignment_proc_ops = { 167 .proc_open = alignment_proc_open, 168 .proc_read = seq_read, 169 .proc_lseek = seq_lseek, 170 .proc_release = single_release, 171 .proc_write = alignment_proc_write, 172 }; 173 #endif /* CONFIG_PROC_FS */ 174 175 union offset_union { 176 unsigned long un; 177 signed long sn; 178 }; 179 180 #define TYPE_ERROR 0 181 #define TYPE_FAULT 1 182 #define TYPE_LDST 2 183 #define TYPE_DONE 3 184 185 #ifdef __ARMEB__ 186 #define BE 1 187 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n" 188 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n" 189 #define NEXT_BYTE "ror #24" 190 #else 191 #define BE 0 192 #define FIRST_BYTE_16 193 #define FIRST_BYTE_32 194 #define NEXT_BYTE "lsr #8" 195 #endif 196 197 #define __get8_unaligned_check(ins,val,addr,err) \ 198 __asm__( \ 199 ARM( "1: "ins" %1, [%2], #1\n" ) \ 200 THUMB( "1: "ins" %1, [%2]\n" ) \ 201 THUMB( " add %2, %2, #1\n" ) \ 202 "2:\n" \ 203 " .pushsection .text.fixup,\"ax\"\n" \ 204 " .align 2\n" \ 205 "3: mov %0, #1\n" \ 206 " b 2b\n" \ 207 " .popsection\n" \ 208 " .pushsection __ex_table,\"a\"\n" \ 209 " .align 3\n" \ 210 " .long 1b, 3b\n" \ 211 " .popsection\n" \ 212 : "=r" (err), "=&r" (val), "=r" (addr) \ 213 : "0" (err), "2" (addr)) 214 215 #define __get16_unaligned_check(ins,val,addr) \ 216 do { \ 217 unsigned int err = 0, v, a = addr; \ 218 __get8_unaligned_check(ins,v,a,err); \ 219 val = v << ((BE) ? 8 : 0); \ 220 __get8_unaligned_check(ins,v,a,err); \ 221 val |= v << ((BE) ? 0 : 8); \ 222 if (err) \ 223 goto fault; \ 224 } while (0) 225 226 #define get16_unaligned_check(val,addr) \ 227 __get16_unaligned_check("ldrb",val,addr) 228 229 #define get16t_unaligned_check(val,addr) \ 230 __get16_unaligned_check("ldrbt",val,addr) 231 232 #define __get32_unaligned_check(ins,val,addr) \ 233 do { \ 234 unsigned int err = 0, v, a = addr; \ 235 __get8_unaligned_check(ins,v,a,err); \ 236 val = v << ((BE) ? 24 : 0); \ 237 __get8_unaligned_check(ins,v,a,err); \ 238 val |= v << ((BE) ? 16 : 8); \ 239 __get8_unaligned_check(ins,v,a,err); \ 240 val |= v << ((BE) ? 8 : 16); \ 241 __get8_unaligned_check(ins,v,a,err); \ 242 val |= v << ((BE) ? 0 : 24); \ 243 if (err) \ 244 goto fault; \ 245 } while (0) 246 247 #define get32_unaligned_check(val,addr) \ 248 __get32_unaligned_check("ldrb",val,addr) 249 250 #define get32t_unaligned_check(val,addr) \ 251 __get32_unaligned_check("ldrbt",val,addr) 252 253 #define __put16_unaligned_check(ins,val,addr) \ 254 do { \ 255 unsigned int err = 0, v = val, a = addr; \ 256 __asm__( FIRST_BYTE_16 \ 257 ARM( "1: "ins" %1, [%2], #1\n" ) \ 258 THUMB( "1: "ins" %1, [%2]\n" ) \ 259 THUMB( " add %2, %2, #1\n" ) \ 260 " mov %1, %1, "NEXT_BYTE"\n" \ 261 "2: "ins" %1, [%2]\n" \ 262 "3:\n" \ 263 " .pushsection .text.fixup,\"ax\"\n" \ 264 " .align 2\n" \ 265 "4: mov %0, #1\n" \ 266 " b 3b\n" \ 267 " .popsection\n" \ 268 " .pushsection __ex_table,\"a\"\n" \ 269 " .align 3\n" \ 270 " .long 1b, 4b\n" \ 271 " .long 2b, 4b\n" \ 272 " .popsection\n" \ 273 : "=r" (err), "=&r" (v), "=&r" (a) \ 274 : "0" (err), "1" (v), "2" (a)); \ 275 if (err) \ 276 goto fault; \ 277 } while (0) 278 279 #define put16_unaligned_check(val,addr) \ 280 __put16_unaligned_check("strb",val,addr) 281 282 #define put16t_unaligned_check(val,addr) \ 283 __put16_unaligned_check("strbt",val,addr) 284 285 #define __put32_unaligned_check(ins,val,addr) \ 286 do { \ 287 unsigned int err = 0, v = val, a = addr; \ 288 __asm__( FIRST_BYTE_32 \ 289 ARM( "1: "ins" %1, [%2], #1\n" ) \ 290 THUMB( "1: "ins" %1, [%2]\n" ) \ 291 THUMB( " add %2, %2, #1\n" ) \ 292 " mov %1, %1, "NEXT_BYTE"\n" \ 293 ARM( "2: "ins" %1, [%2], #1\n" ) \ 294 THUMB( "2: "ins" %1, [%2]\n" ) \ 295 THUMB( " add %2, %2, #1\n" ) \ 296 " mov %1, %1, "NEXT_BYTE"\n" \ 297 ARM( "3: "ins" %1, [%2], #1\n" ) \ 298 THUMB( "3: "ins" %1, [%2]\n" ) \ 299 THUMB( " add %2, %2, #1\n" ) \ 300 " mov %1, %1, "NEXT_BYTE"\n" \ 301 "4: "ins" %1, [%2]\n" \ 302 "5:\n" \ 303 " .pushsection .text.fixup,\"ax\"\n" \ 304 " .align 2\n" \ 305 "6: mov %0, #1\n" \ 306 " b 5b\n" \ 307 " .popsection\n" \ 308 " .pushsection __ex_table,\"a\"\n" \ 309 " .align 3\n" \ 310 " .long 1b, 6b\n" \ 311 " .long 2b, 6b\n" \ 312 " .long 3b, 6b\n" \ 313 " .long 4b, 6b\n" \ 314 " .popsection\n" \ 315 : "=r" (err), "=&r" (v), "=&r" (a) \ 316 : "0" (err), "1" (v), "2" (a)); \ 317 if (err) \ 318 goto fault; \ 319 } while (0) 320 321 #define put32_unaligned_check(val,addr) \ 322 __put32_unaligned_check("strb", val, addr) 323 324 #define put32t_unaligned_check(val,addr) \ 325 __put32_unaligned_check("strbt", val, addr) 326 327 static void 328 do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs, union offset_union offset) 329 { 330 if (!LDST_U_BIT(instr)) 331 offset.un = -offset.un; 332 333 if (!LDST_P_BIT(instr)) 334 addr += offset.un; 335 336 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) 337 regs->uregs[RN_BITS(instr)] = addr; 338 } 339 340 static int 341 do_alignment_ldrhstrh(unsigned long addr, u32 instr, struct pt_regs *regs) 342 { 343 unsigned int rd = RD_BITS(instr); 344 unsigned int ua_flags; 345 bool ua_saved = false; 346 347 ai_half += 1; 348 349 if (user_mode(regs)) 350 goto user; 351 352 if (LDST_L_BIT(instr)) { 353 unsigned long val; 354 get16_unaligned_check(val, addr); 355 356 /* signed half-word? */ 357 if (instr & 0x40) 358 val = (signed long)((signed short) val); 359 360 regs->uregs[rd] = val; 361 } else 362 put16_unaligned_check(regs->uregs[rd], addr); 363 364 return TYPE_LDST; 365 366 user: 367 if (LDST_L_BIT(instr)) { 368 unsigned long val; 369 370 ua_flags = uaccess_save_and_enable(); 371 ua_saved = true; 372 get16t_unaligned_check(val, addr); 373 uaccess_restore(ua_flags); 374 375 /* signed half-word? */ 376 if (instr & 0x40) 377 val = (signed long)((signed short) val); 378 379 regs->uregs[rd] = val; 380 } else { 381 ua_flags = uaccess_save_and_enable(); 382 ua_saved = true; 383 put16t_unaligned_check(regs->uregs[rd], addr); 384 uaccess_restore(ua_flags); 385 } 386 387 return TYPE_LDST; 388 389 fault: 390 if (ua_saved) 391 uaccess_restore(ua_flags); 392 return TYPE_FAULT; 393 } 394 395 static int 396 do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs) 397 { 398 unsigned int rd = RD_BITS(instr); 399 unsigned int rd2; 400 unsigned int ua_flags; 401 bool ua_saved = false; 402 int load; 403 404 if ((instr & 0xfe000000) == 0xe8000000) { 405 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ 406 rd2 = (instr >> 8) & 0xf; 407 load = !!(LDST_L_BIT(instr)); 408 } else if (((rd & 1) == 1) || (rd == 14)) 409 goto bad; 410 else { 411 load = ((instr & 0xf0) == 0xd0); 412 rd2 = rd + 1; 413 } 414 415 ai_dword += 1; 416 417 if (user_mode(regs)) 418 goto user; 419 420 if (load) { 421 unsigned long val; 422 get32_unaligned_check(val, addr); 423 regs->uregs[rd] = val; 424 get32_unaligned_check(val, addr + 4); 425 regs->uregs[rd2] = val; 426 } else { 427 put32_unaligned_check(regs->uregs[rd], addr); 428 put32_unaligned_check(regs->uregs[rd2], addr + 4); 429 } 430 431 return TYPE_LDST; 432 433 user: 434 if (load) { 435 unsigned long val, val2; 436 437 ua_flags = uaccess_save_and_enable(); 438 ua_saved = true; 439 get32t_unaligned_check(val, addr); 440 get32t_unaligned_check(val2, addr + 4); 441 442 uaccess_restore(ua_flags); 443 444 regs->uregs[rd] = val; 445 regs->uregs[rd2] = val2; 446 } else { 447 ua_flags = uaccess_save_and_enable(); 448 ua_saved = true; 449 put32t_unaligned_check(regs->uregs[rd], addr); 450 put32t_unaligned_check(regs->uregs[rd2], addr + 4); 451 uaccess_restore(ua_flags); 452 } 453 454 return TYPE_LDST; 455 bad: 456 return TYPE_ERROR; 457 fault: 458 if (ua_saved) 459 uaccess_restore(ua_flags); 460 return TYPE_FAULT; 461 } 462 463 static int 464 do_alignment_ldrstr(unsigned long addr, u32 instr, struct pt_regs *regs) 465 { 466 unsigned int rd = RD_BITS(instr); 467 unsigned int ua_flags; 468 bool ua_saved = false; 469 470 ai_word += 1; 471 472 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs)) 473 goto trans; 474 475 if (LDST_L_BIT(instr)) { 476 unsigned int val; 477 get32_unaligned_check(val, addr); 478 regs->uregs[rd] = val; 479 } else 480 put32_unaligned_check(regs->uregs[rd], addr); 481 return TYPE_LDST; 482 483 trans: 484 if (LDST_L_BIT(instr)) { 485 unsigned int val; 486 ua_flags = uaccess_save_and_enable(); 487 ua_saved = true; 488 get32t_unaligned_check(val, addr); 489 uaccess_restore(ua_flags); 490 regs->uregs[rd] = val; 491 } else { 492 ua_flags = uaccess_save_and_enable(); 493 ua_saved = true; 494 put32t_unaligned_check(regs->uregs[rd], addr); 495 uaccess_restore(ua_flags); 496 } 497 return TYPE_LDST; 498 499 fault: 500 if (ua_saved) 501 uaccess_restore(ua_flags); 502 return TYPE_FAULT; 503 } 504 505 /* 506 * LDM/STM alignment handler. 507 * 508 * There are 4 variants of this instruction: 509 * 510 * B = rn pointer before instruction, A = rn pointer after instruction 511 * ------ increasing address -----> 512 * | | r0 | r1 | ... | rx | | 513 * PU = 01 B A 514 * PU = 11 B A 515 * PU = 00 A B 516 * PU = 10 A B 517 */ 518 static int 519 do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs) 520 { 521 unsigned int rd, rn, correction, nr_regs, regbits; 522 unsigned long eaddr, newaddr; 523 unsigned int ua_flags; 524 bool ua_saved = false; 525 526 if (LDM_S_BIT(instr)) 527 goto bad; 528 529 correction = 4; /* processor implementation defined */ 530 regs->ARM_pc += correction; 531 532 ai_multi += 1; 533 534 /* count the number of registers in the mask to be transferred */ 535 nr_regs = hweight16(REGMASK_BITS(instr)) * 4; 536 537 rn = RN_BITS(instr); 538 newaddr = eaddr = regs->uregs[rn]; 539 540 if (!LDST_U_BIT(instr)) 541 nr_regs = -nr_regs; 542 newaddr += nr_regs; 543 if (!LDST_U_BIT(instr)) 544 eaddr = newaddr; 545 546 if (LDST_P_EQ_U(instr)) /* U = P */ 547 eaddr += 4; 548 549 /* 550 * For alignment faults on the ARM922T/ARM920T the MMU makes 551 * the FSR (and hence addr) equal to the updated base address 552 * of the multiple access rather than the restored value. 553 * Switch this message off if we've got a ARM92[02], otherwise 554 * [ls]dm alignment faults are noisy! 555 */ 556 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T) 557 /* 558 * This is a "hint" - we already have eaddr worked out by the 559 * processor for us. 560 */ 561 if (addr != eaddr) { 562 pr_err("LDMSTM: PC = %08lx, instr = %08x, " 563 "addr = %08lx, eaddr = %08lx\n", 564 instruction_pointer(regs), instr, addr, eaddr); 565 show_regs(regs); 566 } 567 #endif 568 569 if (user_mode(regs)) { 570 ua_flags = uaccess_save_and_enable(); 571 ua_saved = true; 572 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 573 regbits >>= 1, rd += 1) 574 if (regbits & 1) { 575 if (LDST_L_BIT(instr)) { 576 unsigned int val; 577 get32t_unaligned_check(val, eaddr); 578 regs->uregs[rd] = val; 579 } else 580 put32t_unaligned_check(regs->uregs[rd], eaddr); 581 eaddr += 4; 582 } 583 uaccess_restore(ua_flags); 584 } else { 585 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; 586 regbits >>= 1, rd += 1) 587 if (regbits & 1) { 588 if (LDST_L_BIT(instr)) { 589 unsigned int val; 590 get32_unaligned_check(val, eaddr); 591 regs->uregs[rd] = val; 592 } else 593 put32_unaligned_check(regs->uregs[rd], eaddr); 594 eaddr += 4; 595 } 596 } 597 598 if (LDST_W_BIT(instr)) 599 regs->uregs[rn] = newaddr; 600 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15))) 601 regs->ARM_pc -= correction; 602 return TYPE_DONE; 603 604 fault: 605 if (ua_saved) 606 uaccess_restore(ua_flags); 607 regs->ARM_pc -= correction; 608 return TYPE_FAULT; 609 610 bad: 611 pr_err("Alignment trap: not handling ldm with s-bit set\n"); 612 return TYPE_ERROR; 613 } 614 615 /* 616 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so 617 * we can reuse ARM userland alignment fault fixups for Thumb. 618 * 619 * This implementation was initially based on the algorithm found in 620 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same 621 * to convert only Thumb ld/st instruction forms to equivalent ARM forms. 622 * 623 * NOTES: 624 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections. 625 * 2. If for some reason we're passed an non-ld/st Thumb instruction to 626 * decode, we return 0xdeadc0de. This should never happen under normal 627 * circumstances but if it does, we've got other problems to deal with 628 * elsewhere and we obviously can't fix those problems here. 629 */ 630 631 static unsigned long 632 thumb2arm(u16 tinstr) 633 { 634 u32 L = (tinstr & (1<<11)) >> 11; 635 636 switch ((tinstr & 0xf800) >> 11) { 637 /* 6.5.1 Format 1: */ 638 case 0x6000 >> 11: /* 7.1.52 STR(1) */ 639 case 0x6800 >> 11: /* 7.1.26 LDR(1) */ 640 case 0x7000 >> 11: /* 7.1.55 STRB(1) */ 641 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */ 642 return 0xe5800000 | 643 ((tinstr & (1<<12)) << (22-12)) | /* fixup */ 644 (L<<20) | /* L==1? */ 645 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 646 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 647 ((tinstr & (31<<6)) >> /* immed_5 */ 648 (6 - ((tinstr & (1<<12)) ? 0 : 2))); 649 case 0x8000 >> 11: /* 7.1.57 STRH(1) */ 650 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */ 651 return 0xe1c000b0 | 652 (L<<20) | /* L==1? */ 653 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 654 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 655 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */ 656 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */ 657 658 /* 6.5.1 Format 2: */ 659 case 0x5000 >> 11: 660 case 0x5800 >> 11: 661 { 662 static const u32 subset[8] = { 663 0xe7800000, /* 7.1.53 STR(2) */ 664 0xe18000b0, /* 7.1.58 STRH(2) */ 665 0xe7c00000, /* 7.1.56 STRB(2) */ 666 0xe19000d0, /* 7.1.34 LDRSB */ 667 0xe7900000, /* 7.1.27 LDR(2) */ 668 0xe19000b0, /* 7.1.33 LDRH(2) */ 669 0xe7d00000, /* 7.1.31 LDRB(2) */ 670 0xe19000f0 /* 7.1.35 LDRSH */ 671 }; 672 return subset[(tinstr & (7<<9)) >> 9] | 673 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ 674 ((tinstr & (7<<3)) << (16-3)) | /* Rn */ 675 ((tinstr & (7<<6)) >> (6-0)); /* Rm */ 676 } 677 678 /* 6.5.1 Format 3: */ 679 case 0x4800 >> 11: /* 7.1.28 LDR(3) */ 680 /* NOTE: This case is not technically possible. We're 681 * loading 32-bit memory data via PC relative 682 * addressing mode. So we can and should eliminate 683 * this case. But I'll leave it here for now. 684 */ 685 return 0xe59f0000 | 686 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 687 ((tinstr & 255) << (2-0)); /* immed_8 */ 688 689 /* 6.5.1 Format 4: */ 690 case 0x9000 >> 11: /* 7.1.54 STR(3) */ 691 case 0x9800 >> 11: /* 7.1.29 LDR(4) */ 692 return 0xe58d0000 | 693 (L<<20) | /* L==1? */ 694 ((tinstr & (7<<8)) << (12-8)) | /* Rd */ 695 ((tinstr & 255) << 2); /* immed_8 */ 696 697 /* 6.6.1 Format 1: */ 698 case 0xc000 >> 11: /* 7.1.51 STMIA */ 699 case 0xc800 >> 11: /* 7.1.25 LDMIA */ 700 { 701 u32 Rn = (tinstr & (7<<8)) >> 8; 702 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21; 703 704 return 0xe8800000 | W | (L<<20) | (Rn<<16) | 705 (tinstr&255); 706 } 707 708 /* 6.6.1 Format 2: */ 709 case 0xb000 >> 11: /* 7.1.48 PUSH */ 710 case 0xb800 >> 11: /* 7.1.47 POP */ 711 if ((tinstr & (3 << 9)) == 0x0400) { 712 static const u32 subset[4] = { 713 0xe92d0000, /* STMDB sp!,{registers} */ 714 0xe92d4000, /* STMDB sp!,{registers,lr} */ 715 0xe8bd0000, /* LDMIA sp!,{registers} */ 716 0xe8bd8000 /* LDMIA sp!,{registers,pc} */ 717 }; 718 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] | 719 (tinstr & 255); /* register_list */ 720 } 721 fallthrough; /* for illegal instruction case */ 722 723 default: 724 return BAD_INSTR; 725 } 726 } 727 728 /* 729 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction 730 * handlable by ARM alignment handler, also find the corresponding handler, 731 * so that we can reuse ARM userland alignment fault fixups for Thumb. 732 * 733 * @pinstr: original Thumb-2 instruction; returns new handlable instruction 734 * @regs: register context. 735 * @poffset: return offset from faulted addr for later writeback 736 * 737 * NOTES: 738 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. 739 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt) 740 */ 741 static void * 742 do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs, 743 union offset_union *poffset) 744 { 745 u32 instr = *pinstr; 746 u16 tinst1 = (instr >> 16) & 0xffff; 747 u16 tinst2 = instr & 0xffff; 748 749 switch (tinst1 & 0xffe0) { 750 /* A6.3.5 Load/Store multiple */ 751 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ 752 case 0xe8a0: /* ...above writeback version */ 753 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ 754 case 0xe920: /* ...above writeback version */ 755 /* no need offset decision since handler calculates it */ 756 return do_alignment_ldmstm; 757 758 case 0xf840: /* POP/PUSH T3 (single register) */ 759 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { 760 u32 L = !!(LDST_L_BIT(instr)); 761 const u32 subset[2] = { 762 0xe92d0000, /* STMDB sp!,{registers} */ 763 0xe8bd0000, /* LDMIA sp!,{registers} */ 764 }; 765 *pinstr = subset[L] | (1<<RD_BITS(instr)); 766 return do_alignment_ldmstm; 767 } 768 /* Else fall through for illegal instruction case */ 769 break; 770 771 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */ 772 case 0xe860: 773 case 0xe960: 774 case 0xe8e0: 775 case 0xe9e0: 776 poffset->un = (tinst2 & 0xff) << 2; 777 fallthrough; 778 779 case 0xe940: 780 case 0xe9c0: 781 return do_alignment_ldrdstrd; 782 783 /* 784 * No need to handle load/store instructions up to word size 785 * since ARMv6 and later CPUs can perform unaligned accesses. 786 */ 787 default: 788 break; 789 } 790 return NULL; 791 } 792 793 static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst) 794 { 795 u32 instr = 0; 796 int fault; 797 798 if (user_mode(regs)) 799 fault = get_user(instr, ip); 800 else 801 fault = get_kernel_nofault(instr, ip); 802 803 *inst = __mem_to_opcode_arm(instr); 804 805 return fault; 806 } 807 808 static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst) 809 { 810 u16 instr = 0; 811 int fault; 812 813 if (user_mode(regs)) 814 fault = get_user(instr, ip); 815 else 816 fault = get_kernel_nofault(instr, ip); 817 818 *inst = __mem_to_opcode_thumb16(instr); 819 820 return fault; 821 } 822 823 static int 824 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 825 { 826 union offset_union offset; 827 unsigned long instrptr; 828 int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs); 829 unsigned int type; 830 u32 instr = 0; 831 u16 tinstr = 0; 832 int isize = 4; 833 int thumb2_32b = 0; 834 int fault; 835 836 if (addr >= TASK_SIZE && user_mode(regs)) 837 harden_branch_predictor(); 838 839 if (interrupts_enabled(regs)) 840 local_irq_enable(); 841 842 instrptr = instruction_pointer(regs); 843 844 if (thumb_mode(regs)) { 845 u16 *ptr = (u16 *)(instrptr & ~1); 846 847 fault = alignment_get_thumb(regs, ptr, &tinstr); 848 if (!fault) { 849 if (cpu_architecture() >= CPU_ARCH_ARMv7 && 850 IS_T32(tinstr)) { 851 /* Thumb-2 32-bit */ 852 u16 tinst2; 853 fault = alignment_get_thumb(regs, ptr + 1, &tinst2); 854 instr = __opcode_thumb32_compose(tinstr, tinst2); 855 thumb2_32b = 1; 856 } else { 857 isize = 2; 858 instr = thumb2arm(tinstr); 859 } 860 } 861 } else { 862 fault = alignment_get_arm(regs, (void *)instrptr, &instr); 863 } 864 865 if (fault) { 866 type = TYPE_FAULT; 867 goto bad_or_fault; 868 } 869 870 if (user_mode(regs)) 871 goto user; 872 873 ai_sys += 1; 874 ai_sys_last_pc = (void *)instruction_pointer(regs); 875 876 fixup: 877 878 regs->ARM_pc += isize; 879 880 switch (CODING_BITS(instr)) { 881 case 0x00000000: /* 3.13.4 load/store instruction extensions */ 882 if (LDSTHD_I_BIT(instr)) 883 offset.un = (instr & 0xf00) >> 4 | (instr & 15); 884 else 885 offset.un = regs->uregs[RM_BITS(instr)]; 886 887 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */ 888 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */ 889 handler = do_alignment_ldrhstrh; 890 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */ 891 (instr & 0x001000f0) == 0x000000f0) /* STRD */ 892 handler = do_alignment_ldrdstrd; 893 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */ 894 goto swp; 895 else 896 goto bad; 897 break; 898 899 case 0x04000000: /* ldr or str immediate */ 900 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */ 901 goto bad; 902 offset.un = OFFSET_BITS(instr); 903 handler = do_alignment_ldrstr; 904 break; 905 906 case 0x06000000: /* ldr or str register */ 907 offset.un = regs->uregs[RM_BITS(instr)]; 908 909 if (IS_SHIFT(instr)) { 910 unsigned int shiftval = SHIFT_BITS(instr); 911 912 switch(SHIFT_TYPE(instr)) { 913 case SHIFT_LSL: 914 offset.un <<= shiftval; 915 break; 916 917 case SHIFT_LSR: 918 if (shiftval == 0) 919 offset.un = 0; 920 else 921 offset.un >>= shiftval; 922 break; 923 924 case SHIFT_ASR: 925 if (shiftval == 0) 926 offset.sn >>= 31; 927 else 928 offset.sn >>= shiftval; 929 break; 930 931 case SHIFT_RORRRX: 932 if (shiftval == 0) { 933 offset.un >>= 1; 934 if (regs->ARM_cpsr & PSR_C_BIT) 935 offset.un |= 1 << 31; 936 } else 937 offset.un = offset.un >> shiftval | 938 offset.un << (32 - shiftval); 939 break; 940 } 941 } 942 handler = do_alignment_ldrstr; 943 break; 944 945 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ 946 if (thumb2_32b) { 947 offset.un = 0; 948 handler = do_alignment_t32_to_handler(&instr, regs, &offset); 949 } else { 950 offset.un = 0; 951 handler = do_alignment_ldmstm; 952 } 953 break; 954 955 default: 956 goto bad; 957 } 958 959 if (!handler) 960 goto bad; 961 type = handler(addr, instr, regs); 962 963 if (type == TYPE_ERROR || type == TYPE_FAULT) { 964 regs->ARM_pc -= isize; 965 goto bad_or_fault; 966 } 967 968 if (type == TYPE_LDST) 969 do_alignment_finish_ldst(addr, instr, regs, offset); 970 971 if (thumb_mode(regs)) 972 regs->ARM_cpsr = it_advance(regs->ARM_cpsr); 973 974 return 0; 975 976 bad_or_fault: 977 if (type == TYPE_ERROR) 978 goto bad; 979 /* 980 * We got a fault - fix it up, or die. 981 */ 982 do_bad_area(addr, fsr, regs); 983 return 0; 984 985 swp: 986 pr_err("Alignment trap: not handling swp instruction\n"); 987 988 bad: 989 /* 990 * Oops, we didn't handle the instruction. 991 */ 992 pr_err("Alignment trap: not handling instruction " 993 "%0*x at [<%08lx>]\n", 994 isize << 1, 995 isize == 2 ? tinstr : instr, instrptr); 996 ai_skipped += 1; 997 return 1; 998 999 user: 1000 ai_user += 1; 1001 1002 if (ai_usermode & UM_WARN) 1003 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x " 1004 "Address=0x%08lx FSR 0x%03x\n", current->comm, 1005 task_pid_nr(current), instrptr, 1006 isize << 1, 1007 isize == 2 ? tinstr : instr, 1008 addr, fsr); 1009 1010 if (ai_usermode & UM_FIXUP) 1011 goto fixup; 1012 1013 if (ai_usermode & UM_SIGNAL) { 1014 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)addr); 1015 } else { 1016 /* 1017 * We're about to disable the alignment trap and return to 1018 * user space. But if an interrupt occurs before actually 1019 * reaching user space, then the IRQ vector entry code will 1020 * notice that we were still in kernel space and therefore 1021 * the alignment trap won't be re-enabled in that case as it 1022 * is presumed to be always on from kernel space. 1023 * Let's prevent that race by disabling interrupts here (they 1024 * are disabled on the way back to user space anyway in 1025 * entry-common.S) and disable the alignment trap only if 1026 * there is no work pending for this thread. 1027 */ 1028 raw_local_irq_disable(); 1029 if (!(read_thread_flags() & _TIF_WORK_MASK)) 1030 set_cr(cr_no_alignment); 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int __init noalign_setup(char *__unused) 1037 { 1038 set_cr(__clear_cr(CR_A)); 1039 return 1; 1040 } 1041 __setup("noalign", noalign_setup); 1042 1043 /* 1044 * This needs to be done after sysctl_init_bases(), otherwise sys/ will be 1045 * overwritten. Actually, this shouldn't be in sys/ at all since 1046 * it isn't a sysctl, and it doesn't contain sysctl information. 1047 * We now locate it in /proc/cpu/alignment instead. 1048 */ 1049 static int __init alignment_init(void) 1050 { 1051 #ifdef CONFIG_PROC_FS 1052 struct proc_dir_entry *res; 1053 1054 res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL, 1055 &alignment_proc_ops); 1056 if (!res) 1057 return -ENOMEM; 1058 #endif 1059 1060 if (cpu_is_v6_unaligned()) { 1061 set_cr(__clear_cr(CR_A)); 1062 ai_usermode = safe_usermode(ai_usermode, false); 1063 } 1064 1065 cr_no_alignment = get_cr() & ~CR_A; 1066 1067 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN, 1068 "alignment exception"); 1069 1070 /* 1071 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section 1072 * fault, not as alignment error. 1073 * 1074 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is 1075 * needed. 1076 */ 1077 if (cpu_architecture() <= CPU_ARCH_ARMv6) { 1078 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN, 1079 "alignment exception"); 1080 } 1081 1082 return 0; 1083 } 1084 1085 fs_initcall(alignment_init); 1086