1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * libahci.c - Common AHCI SATA low-level routines
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/bitops.h>
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/module.h>
23 #include <linux/nospec.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/device.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/pci.h>
33 #include "ahci.h"
34 #include "libata.h"
35
36 static int ahci_skip_host_reset;
37 int ahci_ignore_sss;
38 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
39
40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
42
43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
45
46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
47 unsigned hints);
48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
50 size_t size);
51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
52 ssize_t size);
53
54
55
56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask);
60 static int ahci_port_start(struct ata_port *ap);
61 static void ahci_port_stop(struct ata_port *ap);
62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
64 static void ahci_freeze(struct ata_port *ap);
65 static void ahci_thaw(struct ata_port *ap);
66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
67 static void ahci_enable_fbs(struct ata_port *ap);
68 static void ahci_disable_fbs(struct ata_port *ap);
69 static void ahci_pmp_attach(struct ata_port *ap);
70 static void ahci_pmp_detach(struct ata_port *ap);
71 static int ahci_softreset(struct ata_link *link, unsigned int *class,
72 unsigned long deadline);
73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
74 unsigned long deadline);
75 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
76 unsigned long deadline);
77 static void ahci_postreset(struct ata_link *link, unsigned int *class);
78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
79 static void ahci_dev_config(struct ata_device *dev);
80 #ifdef CONFIG_PM
81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
82 #endif
83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
84 static ssize_t ahci_activity_store(struct ata_device *dev,
85 enum sw_activity val);
86 static void ahci_init_sw_activity(struct ata_link *link);
87
88 static ssize_t ahci_show_host_caps(struct device *dev,
89 struct device_attribute *attr, char *buf);
90 static ssize_t ahci_show_host_cap2(struct device *dev,
91 struct device_attribute *attr, char *buf);
92 static ssize_t ahci_show_host_version(struct device *dev,
93 struct device_attribute *attr, char *buf);
94 static ssize_t ahci_show_port_cmd(struct device *dev,
95 struct device_attribute *attr, char *buf);
96 static ssize_t ahci_read_em_buffer(struct device *dev,
97 struct device_attribute *attr, char *buf);
98 static ssize_t ahci_store_em_buffer(struct device *dev,
99 struct device_attribute *attr,
100 const char *buf, size_t size);
101 static ssize_t ahci_show_em_supported(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
104
105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
110 ahci_read_em_buffer, ahci_store_em_buffer);
111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
112
113 static struct attribute *ahci_shost_attrs[] = {
114 &dev_attr_link_power_management_policy.attr,
115 &dev_attr_em_message_type.attr,
116 &dev_attr_em_message.attr,
117 &dev_attr_ahci_host_caps.attr,
118 &dev_attr_ahci_host_cap2.attr,
119 &dev_attr_ahci_host_version.attr,
120 &dev_attr_ahci_port_cmd.attr,
121 &dev_attr_em_buffer.attr,
122 &dev_attr_em_message_supported.attr,
123 NULL
124 };
125
126 static const struct attribute_group ahci_shost_attr_group = {
127 .attrs = ahci_shost_attrs
128 };
129
130 const struct attribute_group *ahci_shost_groups[] = {
131 &ahci_shost_attr_group,
132 NULL
133 };
134 EXPORT_SYMBOL_GPL(ahci_shost_groups);
135
136 static struct attribute *ahci_sdev_attrs[] = {
137 &dev_attr_sw_activity.attr,
138 &dev_attr_unload_heads.attr,
139 &dev_attr_ncq_prio_supported.attr,
140 &dev_attr_ncq_prio_enable.attr,
141 NULL
142 };
143
144 static const struct attribute_group ahci_sdev_attr_group = {
145 .attrs = ahci_sdev_attrs
146 };
147
148 const struct attribute_group *ahci_sdev_groups[] = {
149 &ahci_sdev_attr_group,
150 NULL
151 };
152 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
153
154 struct ata_port_operations ahci_ops = {
155 .inherits = &sata_pmp_port_ops,
156
157 .qc_defer = ahci_pmp_qc_defer,
158 .qc_prep = ahci_qc_prep,
159 .qc_issue = ahci_qc_issue,
160 .qc_fill_rtf = ahci_qc_fill_rtf,
161 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf,
162
163 .freeze = ahci_freeze,
164 .thaw = ahci_thaw,
165 .softreset = ahci_softreset,
166 .hardreset = ahci_hardreset,
167 .postreset = ahci_postreset,
168 .pmp_softreset = ahci_softreset,
169 .error_handler = ahci_error_handler,
170 .post_internal_cmd = ahci_post_internal_cmd,
171 .dev_config = ahci_dev_config,
172
173 .scr_read = ahci_scr_read,
174 .scr_write = ahci_scr_write,
175 .pmp_attach = ahci_pmp_attach,
176 .pmp_detach = ahci_pmp_detach,
177
178 .set_lpm = ahci_set_lpm,
179 .em_show = ahci_led_show,
180 .em_store = ahci_led_store,
181 .sw_activity_show = ahci_activity_show,
182 .sw_activity_store = ahci_activity_store,
183 .transmit_led_message = ahci_transmit_led_message,
184 #ifdef CONFIG_PM
185 .port_suspend = ahci_port_suspend,
186 .port_resume = ahci_port_resume,
187 #endif
188 .port_start = ahci_port_start,
189 .port_stop = ahci_port_stop,
190 };
191 EXPORT_SYMBOL_GPL(ahci_ops);
192
193 struct ata_port_operations ahci_pmp_retry_srst_ops = {
194 .inherits = &ahci_ops,
195 .softreset = ahci_pmp_retry_softreset,
196 };
197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
198
199 static bool ahci_em_messages __read_mostly = true;
200 module_param(ahci_em_messages, bool, 0444);
201 /* add other LED protocol types when they become supported */
202 MODULE_PARM_DESC(ahci_em_messages,
203 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
204
205 /* device sleep idle timeout in ms */
206 static int devslp_idle_timeout __read_mostly = 1000;
207 module_param(devslp_idle_timeout, int, 0644);
208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
209
ahci_enable_ahci(void __iomem * mmio)210 static void ahci_enable_ahci(void __iomem *mmio)
211 {
212 int i;
213 u32 tmp;
214
215 /* turn on AHCI_EN */
216 tmp = readl(mmio + HOST_CTL);
217 if (tmp & HOST_AHCI_EN)
218 return;
219
220 /* Some controllers need AHCI_EN to be written multiple times.
221 * Try a few times before giving up.
222 */
223 for (i = 0; i < 5; i++) {
224 tmp |= HOST_AHCI_EN;
225 writel(tmp, mmio + HOST_CTL);
226 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
227 if (tmp & HOST_AHCI_EN)
228 return;
229 msleep(10);
230 }
231
232 WARN_ON(1);
233 }
234
235 /**
236 * ahci_rpm_get_port - Make sure the port is powered on
237 * @ap: Port to power on
238 *
239 * Whenever there is need to access the AHCI host registers outside of
240 * normal execution paths, call this function to make sure the host is
241 * actually powered on.
242 */
ahci_rpm_get_port(struct ata_port * ap)243 static int ahci_rpm_get_port(struct ata_port *ap)
244 {
245 return pm_runtime_get_sync(ap->dev);
246 }
247
248 /**
249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
250 * @ap: Port to power down
251 *
252 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
253 * if it has no more active users.
254 */
ahci_rpm_put_port(struct ata_port * ap)255 static void ahci_rpm_put_port(struct ata_port *ap)
256 {
257 pm_runtime_put(ap->dev);
258 }
259
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)260 static ssize_t ahci_show_host_caps(struct device *dev,
261 struct device_attribute *attr, char *buf)
262 {
263 struct Scsi_Host *shost = class_to_shost(dev);
264 struct ata_port *ap = ata_shost_to_port(shost);
265 struct ahci_host_priv *hpriv = ap->host->private_data;
266
267 return sprintf(buf, "%x\n", hpriv->cap);
268 }
269
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)270 static ssize_t ahci_show_host_cap2(struct device *dev,
271 struct device_attribute *attr, char *buf)
272 {
273 struct Scsi_Host *shost = class_to_shost(dev);
274 struct ata_port *ap = ata_shost_to_port(shost);
275 struct ahci_host_priv *hpriv = ap->host->private_data;
276
277 return sprintf(buf, "%x\n", hpriv->cap2);
278 }
279
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)280 static ssize_t ahci_show_host_version(struct device *dev,
281 struct device_attribute *attr, char *buf)
282 {
283 struct Scsi_Host *shost = class_to_shost(dev);
284 struct ata_port *ap = ata_shost_to_port(shost);
285 struct ahci_host_priv *hpriv = ap->host->private_data;
286
287 return sprintf(buf, "%x\n", hpriv->version);
288 }
289
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)290 static ssize_t ahci_show_port_cmd(struct device *dev,
291 struct device_attribute *attr, char *buf)
292 {
293 struct Scsi_Host *shost = class_to_shost(dev);
294 struct ata_port *ap = ata_shost_to_port(shost);
295 void __iomem *port_mmio = ahci_port_base(ap);
296 ssize_t ret;
297
298 ahci_rpm_get_port(ap);
299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
300 ahci_rpm_put_port(ap);
301
302 return ret;
303 }
304
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)305 static ssize_t ahci_read_em_buffer(struct device *dev,
306 struct device_attribute *attr, char *buf)
307 {
308 struct Scsi_Host *shost = class_to_shost(dev);
309 struct ata_port *ap = ata_shost_to_port(shost);
310 struct ahci_host_priv *hpriv = ap->host->private_data;
311 void __iomem *mmio = hpriv->mmio;
312 void __iomem *em_mmio = mmio + hpriv->em_loc;
313 u32 em_ctl, msg;
314 unsigned long flags;
315 size_t count;
316 int i;
317
318 ahci_rpm_get_port(ap);
319 spin_lock_irqsave(ap->lock, flags);
320
321 em_ctl = readl(mmio + HOST_EM_CTL);
322 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
323 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
326 return -EINVAL;
327 }
328
329 if (!(em_ctl & EM_CTL_MR)) {
330 spin_unlock_irqrestore(ap->lock, flags);
331 ahci_rpm_put_port(ap);
332 return -EAGAIN;
333 }
334
335 if (!(em_ctl & EM_CTL_SMB))
336 em_mmio += hpriv->em_buf_sz;
337
338 count = hpriv->em_buf_sz;
339
340 /* the count should not be larger than PAGE_SIZE */
341 if (count > PAGE_SIZE) {
342 if (printk_ratelimit())
343 ata_port_warn(ap,
344 "EM read buffer size too large: "
345 "buffer size %u, page size %lu\n",
346 hpriv->em_buf_sz, PAGE_SIZE);
347 count = PAGE_SIZE;
348 }
349
350 for (i = 0; i < count; i += 4) {
351 msg = readl(em_mmio + i);
352 buf[i] = msg & 0xff;
353 buf[i + 1] = (msg >> 8) & 0xff;
354 buf[i + 2] = (msg >> 16) & 0xff;
355 buf[i + 3] = (msg >> 24) & 0xff;
356 }
357
358 spin_unlock_irqrestore(ap->lock, flags);
359 ahci_rpm_put_port(ap);
360
361 return i;
362 }
363
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)364 static ssize_t ahci_store_em_buffer(struct device *dev,
365 struct device_attribute *attr,
366 const char *buf, size_t size)
367 {
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 void __iomem *em_mmio = mmio + hpriv->em_loc;
373 const unsigned char *msg_buf = buf;
374 u32 em_ctl, msg;
375 unsigned long flags;
376 int i;
377
378 /* check size validity */
379 if (!(ap->flags & ATA_FLAG_EM) ||
380 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
381 size % 4 || size > hpriv->em_buf_sz)
382 return -EINVAL;
383
384 ahci_rpm_get_port(ap);
385 spin_lock_irqsave(ap->lock, flags);
386
387 em_ctl = readl(mmio + HOST_EM_CTL);
388 if (em_ctl & EM_CTL_TM) {
389 spin_unlock_irqrestore(ap->lock, flags);
390 ahci_rpm_put_port(ap);
391 return -EBUSY;
392 }
393
394 for (i = 0; i < size; i += 4) {
395 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
396 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
397 writel(msg, em_mmio + i);
398 }
399
400 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
401
402 spin_unlock_irqrestore(ap->lock, flags);
403 ahci_rpm_put_port(ap);
404
405 return size;
406 }
407
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)408 static ssize_t ahci_show_em_supported(struct device *dev,
409 struct device_attribute *attr, char *buf)
410 {
411 struct Scsi_Host *shost = class_to_shost(dev);
412 struct ata_port *ap = ata_shost_to_port(shost);
413 struct ahci_host_priv *hpriv = ap->host->private_data;
414 void __iomem *mmio = hpriv->mmio;
415 u32 em_ctl;
416
417 ahci_rpm_get_port(ap);
418 em_ctl = readl(mmio + HOST_EM_CTL);
419 ahci_rpm_put_port(ap);
420
421 return sprintf(buf, "%s%s%s%s\n",
422 em_ctl & EM_CTL_LED ? "led " : "",
423 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
424 em_ctl & EM_CTL_SES ? "ses-2 " : "",
425 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
426 }
427
428 /**
429 * ahci_save_initial_config - Save and fixup initial config values
430 * @dev: target AHCI device
431 * @hpriv: host private area to store config values
432 *
433 * Some registers containing configuration info might be setup by
434 * BIOS and might be cleared on reset. This function saves the
435 * initial values of those registers into @hpriv such that they
436 * can be restored after controller reset.
437 *
438 * If inconsistent, config values are fixed up by this function.
439 *
440 * If it is not set already this function sets hpriv->start_engine to
441 * ahci_start_engine.
442 *
443 * LOCKING:
444 * None.
445 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
447 {
448 void __iomem *mmio = hpriv->mmio;
449 void __iomem *port_mmio;
450 unsigned long port_map;
451 u32 cap, cap2, vers;
452 int i;
453
454 /* make sure AHCI mode is enabled before accessing CAP */
455 ahci_enable_ahci(mmio);
456
457 /*
458 * Values prefixed with saved_ are written back to the HBA and ports
459 * registers after reset. Values without are used for driver operation.
460 */
461
462 /*
463 * Override HW-init HBA capability fields with the platform-specific
464 * values. The rest of the HBA capabilities are defined as Read-only
465 * and can't be modified in CSR anyway.
466 */
467 cap = readl(mmio + HOST_CAP);
468 if (hpriv->saved_cap)
469 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
470 hpriv->saved_cap = cap;
471
472 /* CAP2 register is only defined for AHCI 1.2 and later */
473 vers = readl(mmio + HOST_VERSION);
474 if ((vers >> 16) > 1 ||
475 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
476 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
477 else
478 hpriv->saved_cap2 = cap2 = 0;
479
480 /* some chips have errata preventing 64bit use */
481 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
482 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
483 cap &= ~HOST_CAP_64;
484 }
485
486 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
487 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
488 cap &= ~HOST_CAP_NCQ;
489 }
490
491 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
492 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
493 cap |= HOST_CAP_NCQ;
494 }
495
496 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
497 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
498 cap &= ~HOST_CAP_PMP;
499 }
500
501 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
502 dev_info(dev,
503 "controller can't do SNTF, turning off CAP_SNTF\n");
504 cap &= ~HOST_CAP_SNTF;
505 }
506
507 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
508 dev_info(dev,
509 "controller can't do DEVSLP, turning off\n");
510 cap2 &= ~HOST_CAP2_SDS;
511 cap2 &= ~HOST_CAP2_SADM;
512 }
513
514 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
515 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
516 cap |= HOST_CAP_FBS;
517 }
518
519 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
520 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
521 cap &= ~HOST_CAP_FBS;
522 }
523
524 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
525 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
526 cap |= HOST_CAP_ALPM;
527 }
528
529 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
530 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
531 cap &= ~HOST_CAP_SXS;
532 }
533
534 /* Override the HBA ports mapping if the platform needs it */
535 port_map = readl(mmio + HOST_PORTS_IMPL);
536 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
537 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
538 port_map, hpriv->saved_port_map);
539 port_map = hpriv->saved_port_map;
540 } else {
541 hpriv->saved_port_map = port_map;
542 }
543
544 /* mask_port_map not set means that all ports are available */
545 if (hpriv->mask_port_map) {
546 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
547 port_map,
548 port_map & hpriv->mask_port_map);
549 port_map &= hpriv->mask_port_map;
550 }
551
552 /* cross check port_map and cap.n_ports */
553 if (port_map) {
554 int map_ports = 0;
555
556 for (i = 0; i < AHCI_MAX_PORTS; i++)
557 if (port_map & (1 << i))
558 map_ports++;
559
560 /* If PI has more ports than n_ports, whine, clear
561 * port_map and let it be generated from n_ports.
562 */
563 if (map_ports > ahci_nr_ports(cap)) {
564 dev_warn(dev,
565 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
566 port_map, ahci_nr_ports(cap));
567 port_map = 0;
568 }
569 }
570
571 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
572 if (!port_map && vers < 0x10300) {
573 port_map = (1 << ahci_nr_ports(cap)) - 1;
574 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
575
576 /* write the fixed up value to the PI register */
577 hpriv->saved_port_map = port_map;
578 }
579
580 /*
581 * Preserve the ports capabilities defined by the platform. Note there
582 * is no need in storing the rest of the P#.CMD fields since they are
583 * volatile.
584 */
585 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
586 if (hpriv->saved_port_cap[i])
587 continue;
588
589 port_mmio = __ahci_port_base(hpriv, i);
590 hpriv->saved_port_cap[i] =
591 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
592 }
593
594 /* record values to use during operation */
595 hpriv->cap = cap;
596 hpriv->cap2 = cap2;
597 hpriv->version = vers;
598 hpriv->port_map = port_map;
599
600 if (!hpriv->start_engine)
601 hpriv->start_engine = ahci_start_engine;
602
603 if (!hpriv->stop_engine)
604 hpriv->stop_engine = ahci_stop_engine;
605
606 if (!hpriv->irq_handler)
607 hpriv->irq_handler = ahci_single_level_irq_intr;
608 }
609 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
610
611 /**
612 * ahci_restore_initial_config - Restore initial config
613 * @host: target ATA host
614 *
615 * Restore initial config stored by ahci_save_initial_config().
616 *
617 * LOCKING:
618 * None.
619 */
ahci_restore_initial_config(struct ata_host * host)620 static void ahci_restore_initial_config(struct ata_host *host)
621 {
622 struct ahci_host_priv *hpriv = host->private_data;
623 unsigned long port_map = hpriv->port_map;
624 void __iomem *mmio = hpriv->mmio;
625 void __iomem *port_mmio;
626 int i;
627
628 writel(hpriv->saved_cap, mmio + HOST_CAP);
629 if (hpriv->saved_cap2)
630 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
631 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
632 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
633
634 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
635 port_mmio = __ahci_port_base(hpriv, i);
636 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
637 }
638 }
639
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)640 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
641 {
642 static const int offset[] = {
643 [SCR_STATUS] = PORT_SCR_STAT,
644 [SCR_CONTROL] = PORT_SCR_CTL,
645 [SCR_ERROR] = PORT_SCR_ERR,
646 [SCR_ACTIVE] = PORT_SCR_ACT,
647 [SCR_NOTIFICATION] = PORT_SCR_NTF,
648 };
649 struct ahci_host_priv *hpriv = ap->host->private_data;
650
651 if (sc_reg < ARRAY_SIZE(offset) &&
652 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
653 return offset[sc_reg];
654 return 0;
655 }
656
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)657 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
658 {
659 void __iomem *port_mmio = ahci_port_base(link->ap);
660 int offset = ahci_scr_offset(link->ap, sc_reg);
661
662 if (offset) {
663 *val = readl(port_mmio + offset);
664 return 0;
665 }
666 return -EINVAL;
667 }
668
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)669 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
670 {
671 void __iomem *port_mmio = ahci_port_base(link->ap);
672 int offset = ahci_scr_offset(link->ap, sc_reg);
673
674 if (offset) {
675 writel(val, port_mmio + offset);
676 return 0;
677 }
678 return -EINVAL;
679 }
680
ahci_start_engine(struct ata_port * ap)681 void ahci_start_engine(struct ata_port *ap)
682 {
683 void __iomem *port_mmio = ahci_port_base(ap);
684 u32 tmp;
685
686 /* start DMA */
687 tmp = readl(port_mmio + PORT_CMD);
688 tmp |= PORT_CMD_START;
689 writel(tmp, port_mmio + PORT_CMD);
690 readl(port_mmio + PORT_CMD); /* flush */
691 }
692 EXPORT_SYMBOL_GPL(ahci_start_engine);
693
ahci_stop_engine(struct ata_port * ap)694 int ahci_stop_engine(struct ata_port *ap)
695 {
696 void __iomem *port_mmio = ahci_port_base(ap);
697 struct ahci_host_priv *hpriv = ap->host->private_data;
698 u32 tmp;
699
700 /*
701 * On some controllers, stopping a port's DMA engine while the port
702 * is in ALPM state (partial or slumber) results in failures on
703 * subsequent DMA engine starts. For those controllers, put the
704 * port back in active state before stopping its DMA engine.
705 */
706 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
707 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
708 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
709 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
710 return -EIO;
711 }
712
713 tmp = readl(port_mmio + PORT_CMD);
714
715 /* check if the HBA is idle */
716 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
717 return 0;
718
719 /*
720 * Don't try to issue commands but return with ENODEV if the
721 * AHCI controller not available anymore (e.g. due to PCIe hot
722 * unplugging). Otherwise a 500ms delay for each port is added.
723 */
724 if (tmp == 0xffffffff) {
725 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
726 return -ENODEV;
727 }
728
729 /* setting HBA to idle */
730 tmp &= ~PORT_CMD_START;
731 writel(tmp, port_mmio + PORT_CMD);
732
733 /* wait for engine to stop. This could be as long as 500 msec */
734 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
735 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
736 if (tmp & PORT_CMD_LIST_ON)
737 return -EIO;
738
739 return 0;
740 }
741 EXPORT_SYMBOL_GPL(ahci_stop_engine);
742
ahci_start_fis_rx(struct ata_port * ap)743 void ahci_start_fis_rx(struct ata_port *ap)
744 {
745 void __iomem *port_mmio = ahci_port_base(ap);
746 struct ahci_host_priv *hpriv = ap->host->private_data;
747 struct ahci_port_priv *pp = ap->private_data;
748 u32 tmp;
749
750 /* set FIS registers */
751 if (hpriv->cap & HOST_CAP_64)
752 writel((pp->cmd_slot_dma >> 16) >> 16,
753 port_mmio + PORT_LST_ADDR_HI);
754 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
755
756 if (hpriv->cap & HOST_CAP_64)
757 writel((pp->rx_fis_dma >> 16) >> 16,
758 port_mmio + PORT_FIS_ADDR_HI);
759 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
760
761 /* enable FIS reception */
762 tmp = readl(port_mmio + PORT_CMD);
763 tmp |= PORT_CMD_FIS_RX;
764 writel(tmp, port_mmio + PORT_CMD);
765
766 /* flush */
767 readl(port_mmio + PORT_CMD);
768 }
769 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
770
ahci_stop_fis_rx(struct ata_port * ap)771 static int ahci_stop_fis_rx(struct ata_port *ap)
772 {
773 void __iomem *port_mmio = ahci_port_base(ap);
774 u32 tmp;
775
776 /* disable FIS reception */
777 tmp = readl(port_mmio + PORT_CMD);
778 tmp &= ~PORT_CMD_FIS_RX;
779 writel(tmp, port_mmio + PORT_CMD);
780
781 /* wait for completion, spec says 500ms, give it 1000 */
782 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
783 PORT_CMD_FIS_ON, 10, 1000);
784 if (tmp & PORT_CMD_FIS_ON)
785 return -EBUSY;
786
787 return 0;
788 }
789
ahci_power_up(struct ata_port * ap)790 static void ahci_power_up(struct ata_port *ap)
791 {
792 struct ahci_host_priv *hpriv = ap->host->private_data;
793 void __iomem *port_mmio = ahci_port_base(ap);
794 u32 cmd;
795
796 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
797
798 /* spin up device */
799 if (hpriv->cap & HOST_CAP_SSS) {
800 cmd |= PORT_CMD_SPIN_UP;
801 writel(cmd, port_mmio + PORT_CMD);
802 }
803
804 /* wake up link */
805 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
806 }
807
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)808 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
809 unsigned int hints)
810 {
811 struct ata_port *ap = link->ap;
812 struct ahci_host_priv *hpriv = ap->host->private_data;
813 struct ahci_port_priv *pp = ap->private_data;
814 void __iomem *port_mmio = ahci_port_base(ap);
815
816 if (policy != ATA_LPM_MAX_POWER) {
817 /* wakeup flag only applies to the max power policy */
818 hints &= ~ATA_LPM_WAKE_ONLY;
819
820 /*
821 * Disable interrupts on Phy Ready. This keeps us from
822 * getting woken up due to spurious phy ready
823 * interrupts.
824 */
825 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
826 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
827
828 sata_link_scr_lpm(link, policy, false);
829 }
830
831 if (hpriv->cap & HOST_CAP_ALPM) {
832 u32 cmd = readl(port_mmio + PORT_CMD);
833
834 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
835 if (!(hints & ATA_LPM_WAKE_ONLY))
836 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
837 cmd |= PORT_CMD_ICC_ACTIVE;
838
839 writel(cmd, port_mmio + PORT_CMD);
840 readl(port_mmio + PORT_CMD);
841
842 /* wait 10ms to be sure we've come out of LPM state */
843 ata_msleep(ap, 10);
844
845 if (hints & ATA_LPM_WAKE_ONLY)
846 return 0;
847 } else {
848 cmd |= PORT_CMD_ALPE;
849 if (policy == ATA_LPM_MIN_POWER)
850 cmd |= PORT_CMD_ASP;
851 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
852 cmd &= ~PORT_CMD_ASP;
853
854 /* write out new cmd value */
855 writel(cmd, port_mmio + PORT_CMD);
856 }
857 }
858
859 /* set aggressive device sleep */
860 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
861 (hpriv->cap2 & HOST_CAP2_SADM) &&
862 (link->device->flags & ATA_DFLAG_DEVSLP)) {
863 if (policy == ATA_LPM_MIN_POWER ||
864 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
865 ahci_set_aggressive_devslp(ap, true);
866 else
867 ahci_set_aggressive_devslp(ap, false);
868 }
869
870 if (policy == ATA_LPM_MAX_POWER) {
871 sata_link_scr_lpm(link, policy, false);
872
873 /* turn PHYRDY IRQ back on */
874 pp->intr_mask |= PORT_IRQ_PHYRDY;
875 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
876 }
877
878 return 0;
879 }
880
881 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)882 static void ahci_power_down(struct ata_port *ap)
883 {
884 struct ahci_host_priv *hpriv = ap->host->private_data;
885 void __iomem *port_mmio = ahci_port_base(ap);
886 u32 cmd, scontrol;
887
888 if (!(hpriv->cap & HOST_CAP_SSS))
889 return;
890
891 /* put device into listen mode, first set PxSCTL.DET to 0 */
892 scontrol = readl(port_mmio + PORT_SCR_CTL);
893 scontrol &= ~0xf;
894 writel(scontrol, port_mmio + PORT_SCR_CTL);
895
896 /* then set PxCMD.SUD to 0 */
897 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
898 cmd &= ~PORT_CMD_SPIN_UP;
899 writel(cmd, port_mmio + PORT_CMD);
900 }
901 #endif
902
ahci_start_port(struct ata_port * ap)903 static void ahci_start_port(struct ata_port *ap)
904 {
905 struct ahci_host_priv *hpriv = ap->host->private_data;
906 struct ahci_port_priv *pp = ap->private_data;
907 struct ata_link *link;
908 struct ahci_em_priv *emp;
909 ssize_t rc;
910 int i;
911
912 /* enable FIS reception */
913 ahci_start_fis_rx(ap);
914
915 /* enable DMA */
916 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
917 hpriv->start_engine(ap);
918
919 /* turn on LEDs */
920 if (ap->flags & ATA_FLAG_EM) {
921 ata_for_each_link(link, ap, EDGE) {
922 emp = &pp->em_priv[link->pmp];
923
924 /* EM Transmit bit maybe busy during init */
925 for (i = 0; i < EM_MAX_RETRY; i++) {
926 rc = ap->ops->transmit_led_message(ap,
927 emp->led_state,
928 4);
929 /*
930 * If busy, give a breather but do not
931 * release EH ownership by using msleep()
932 * instead of ata_msleep(). EM Transmit
933 * bit is busy for the whole host and
934 * releasing ownership will cause other
935 * ports to fail the same way.
936 */
937 if (rc == -EBUSY)
938 msleep(1);
939 else
940 break;
941 }
942 }
943 }
944
945 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
946 ata_for_each_link(link, ap, EDGE)
947 ahci_init_sw_activity(link);
948
949 }
950
ahci_deinit_port(struct ata_port * ap,const char ** emsg)951 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
952 {
953 int rc;
954 struct ahci_host_priv *hpriv = ap->host->private_data;
955
956 /* disable DMA */
957 rc = hpriv->stop_engine(ap);
958 if (rc) {
959 *emsg = "failed to stop engine";
960 return rc;
961 }
962
963 /* disable FIS reception */
964 rc = ahci_stop_fis_rx(ap);
965 if (rc) {
966 *emsg = "failed stop FIS RX";
967 return rc;
968 }
969
970 return 0;
971 }
972
ahci_reset_controller(struct ata_host * host)973 int ahci_reset_controller(struct ata_host *host)
974 {
975 struct ahci_host_priv *hpriv = host->private_data;
976 void __iomem *mmio = hpriv->mmio;
977 u32 tmp;
978
979 /*
980 * We must be in AHCI mode, before using anything AHCI-specific, such
981 * as HOST_RESET.
982 */
983 ahci_enable_ahci(mmio);
984
985 /* Global controller reset */
986 if (ahci_skip_host_reset) {
987 dev_info(host->dev, "Skipping global host reset\n");
988 return 0;
989 }
990
991 tmp = readl(mmio + HOST_CTL);
992 if (!(tmp & HOST_RESET)) {
993 writel(tmp | HOST_RESET, mmio + HOST_CTL);
994 readl(mmio + HOST_CTL); /* flush */
995 }
996
997 /*
998 * To perform host reset, OS should set HOST_RESET and poll until this
999 * bit is read to be "0". Reset must complete within 1 second, or the
1000 * hardware should be considered fried.
1001 */
1002 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
1003 HOST_RESET, 10, 1000);
1004 if (tmp & HOST_RESET) {
1005 dev_err(host->dev, "Controller reset failed (0x%x)\n",
1006 tmp);
1007 return -EIO;
1008 }
1009
1010 /* Turn on AHCI mode */
1011 ahci_enable_ahci(mmio);
1012
1013 /* Some registers might be cleared on reset. Restore initial values. */
1014 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
1015 ahci_restore_initial_config(host);
1016
1017 return 0;
1018 }
1019 EXPORT_SYMBOL_GPL(ahci_reset_controller);
1020
ahci_sw_activity(struct ata_link * link)1021 static void ahci_sw_activity(struct ata_link *link)
1022 {
1023 struct ata_port *ap = link->ap;
1024 struct ahci_port_priv *pp = ap->private_data;
1025 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1026
1027 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1028 return;
1029
1030 emp->activity++;
1031 if (!timer_pending(&emp->timer))
1032 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1033 }
1034
ahci_sw_activity_blink(struct timer_list * t)1035 static void ahci_sw_activity_blink(struct timer_list *t)
1036 {
1037 struct ahci_em_priv *emp = from_timer(emp, t, timer);
1038 struct ata_link *link = emp->link;
1039 struct ata_port *ap = link->ap;
1040
1041 unsigned long led_message = emp->led_state;
1042 u32 activity_led_state;
1043 unsigned long flags;
1044
1045 led_message &= EM_MSG_LED_VALUE;
1046 led_message |= ap->port_no | (link->pmp << 8);
1047
1048 /* check to see if we've had activity. If so,
1049 * toggle state of LED and reset timer. If not,
1050 * turn LED to desired idle state.
1051 */
1052 spin_lock_irqsave(ap->lock, flags);
1053 if (emp->saved_activity != emp->activity) {
1054 emp->saved_activity = emp->activity;
1055 /* get the current LED state */
1056 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1057
1058 if (activity_led_state)
1059 activity_led_state = 0;
1060 else
1061 activity_led_state = 1;
1062
1063 /* clear old state */
1064 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1065
1066 /* toggle state */
1067 led_message |= (activity_led_state << 16);
1068 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1069 } else {
1070 /* switch to idle */
1071 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1072 if (emp->blink_policy == BLINK_OFF)
1073 led_message |= (1 << 16);
1074 }
1075 spin_unlock_irqrestore(ap->lock, flags);
1076 ap->ops->transmit_led_message(ap, led_message, 4);
1077 }
1078
ahci_init_sw_activity(struct ata_link * link)1079 static void ahci_init_sw_activity(struct ata_link *link)
1080 {
1081 struct ata_port *ap = link->ap;
1082 struct ahci_port_priv *pp = ap->private_data;
1083 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1084
1085 /* init activity stats, setup timer */
1086 emp->saved_activity = emp->activity = 0;
1087 emp->link = link;
1088 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1089
1090 /* check our blink policy and set flag for link if it's enabled */
1091 if (emp->blink_policy)
1092 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1093 }
1094
ahci_reset_em(struct ata_host * host)1095 int ahci_reset_em(struct ata_host *host)
1096 {
1097 struct ahci_host_priv *hpriv = host->private_data;
1098 void __iomem *mmio = hpriv->mmio;
1099 u32 em_ctl;
1100
1101 em_ctl = readl(mmio + HOST_EM_CTL);
1102 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1103 return -EINVAL;
1104
1105 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1106 return 0;
1107 }
1108 EXPORT_SYMBOL_GPL(ahci_reset_em);
1109
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1110 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1111 ssize_t size)
1112 {
1113 struct ahci_host_priv *hpriv = ap->host->private_data;
1114 struct ahci_port_priv *pp = ap->private_data;
1115 void __iomem *mmio = hpriv->mmio;
1116 u32 em_ctl;
1117 u32 message[] = {0, 0};
1118 unsigned long flags;
1119 int pmp;
1120 struct ahci_em_priv *emp;
1121
1122 /* get the slot number from the message */
1123 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1124 if (pmp < EM_MAX_SLOTS)
1125 emp = &pp->em_priv[pmp];
1126 else
1127 return -EINVAL;
1128
1129 ahci_rpm_get_port(ap);
1130 spin_lock_irqsave(ap->lock, flags);
1131
1132 /*
1133 * if we are still busy transmitting a previous message,
1134 * do not allow
1135 */
1136 em_ctl = readl(mmio + HOST_EM_CTL);
1137 if (em_ctl & EM_CTL_TM) {
1138 spin_unlock_irqrestore(ap->lock, flags);
1139 ahci_rpm_put_port(ap);
1140 return -EBUSY;
1141 }
1142
1143 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1144 /*
1145 * create message header - this is all zero except for
1146 * the message size, which is 4 bytes.
1147 */
1148 message[0] |= (4 << 8);
1149
1150 /* ignore 0:4 of byte zero, fill in port info yourself */
1151 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1152
1153 /* write message to EM_LOC */
1154 writel(message[0], mmio + hpriv->em_loc);
1155 writel(message[1], mmio + hpriv->em_loc+4);
1156
1157 /*
1158 * tell hardware to transmit the message
1159 */
1160 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1161 }
1162
1163 /* save off new led state for port/slot */
1164 emp->led_state = state;
1165
1166 spin_unlock_irqrestore(ap->lock, flags);
1167 ahci_rpm_put_port(ap);
1168
1169 return size;
1170 }
1171
ahci_led_show(struct ata_port * ap,char * buf)1172 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1173 {
1174 struct ahci_port_priv *pp = ap->private_data;
1175 struct ata_link *link;
1176 struct ahci_em_priv *emp;
1177 int rc = 0;
1178
1179 ata_for_each_link(link, ap, EDGE) {
1180 emp = &pp->em_priv[link->pmp];
1181 rc += sprintf(buf, "%lx\n", emp->led_state);
1182 }
1183 return rc;
1184 }
1185
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1186 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1187 size_t size)
1188 {
1189 unsigned int state;
1190 int pmp;
1191 struct ahci_port_priv *pp = ap->private_data;
1192 struct ahci_em_priv *emp;
1193
1194 if (kstrtouint(buf, 0, &state) < 0)
1195 return -EINVAL;
1196
1197 /* get the slot number from the message */
1198 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1199 if (pmp < EM_MAX_SLOTS) {
1200 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1201 emp = &pp->em_priv[pmp];
1202 } else {
1203 return -EINVAL;
1204 }
1205
1206 /* mask off the activity bits if we are in sw_activity
1207 * mode, user should turn off sw_activity before setting
1208 * activity led through em_message
1209 */
1210 if (emp->blink_policy)
1211 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1212
1213 return ap->ops->transmit_led_message(ap, state, size);
1214 }
1215
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1216 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1217 {
1218 struct ata_link *link = dev->link;
1219 struct ata_port *ap = link->ap;
1220 struct ahci_port_priv *pp = ap->private_data;
1221 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1222 u32 port_led_state = emp->led_state;
1223
1224 /* save the desired Activity LED behavior */
1225 if (val == OFF) {
1226 /* clear LFLAG */
1227 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1228
1229 /* set the LED to OFF */
1230 port_led_state &= EM_MSG_LED_VALUE_OFF;
1231 port_led_state |= (ap->port_no | (link->pmp << 8));
1232 ap->ops->transmit_led_message(ap, port_led_state, 4);
1233 } else {
1234 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1235 if (val == BLINK_OFF) {
1236 /* set LED to ON for idle */
1237 port_led_state &= EM_MSG_LED_VALUE_OFF;
1238 port_led_state |= (ap->port_no | (link->pmp << 8));
1239 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1240 ap->ops->transmit_led_message(ap, port_led_state, 4);
1241 }
1242 }
1243 emp->blink_policy = val;
1244 return 0;
1245 }
1246
ahci_activity_show(struct ata_device * dev,char * buf)1247 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1248 {
1249 struct ata_link *link = dev->link;
1250 struct ata_port *ap = link->ap;
1251 struct ahci_port_priv *pp = ap->private_data;
1252 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1253
1254 /* display the saved value of activity behavior for this
1255 * disk.
1256 */
1257 return sprintf(buf, "%d\n", emp->blink_policy);
1258 }
1259
ahci_port_clear_pending_irq(struct ata_port * ap)1260 static void ahci_port_clear_pending_irq(struct ata_port *ap)
1261 {
1262 struct ahci_host_priv *hpriv = ap->host->private_data;
1263 void __iomem *port_mmio = ahci_port_base(ap);
1264 u32 tmp;
1265
1266 /* clear SError */
1267 tmp = readl(port_mmio + PORT_SCR_ERR);
1268 dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
1269 writel(tmp, port_mmio + PORT_SCR_ERR);
1270
1271 /* clear port IRQ */
1272 tmp = readl(port_mmio + PORT_IRQ_STAT);
1273 dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1274 if (tmp)
1275 writel(tmp, port_mmio + PORT_IRQ_STAT);
1276
1277 writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
1278 }
1279
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1280 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1281 int port_no, void __iomem *mmio,
1282 void __iomem *port_mmio)
1283 {
1284 const char *emsg = NULL;
1285 int rc;
1286
1287 /* make sure port is not active */
1288 rc = ahci_deinit_port(ap, &emsg);
1289 if (rc)
1290 dev_warn(dev, "%s (%d)\n", emsg, rc);
1291
1292 ahci_port_clear_pending_irq(ap);
1293 }
1294
ahci_init_controller(struct ata_host * host)1295 void ahci_init_controller(struct ata_host *host)
1296 {
1297 struct ahci_host_priv *hpriv = host->private_data;
1298 void __iomem *mmio = hpriv->mmio;
1299 int i;
1300 void __iomem *port_mmio;
1301 u32 tmp;
1302
1303 for (i = 0; i < host->n_ports; i++) {
1304 struct ata_port *ap = host->ports[i];
1305
1306 port_mmio = ahci_port_base(ap);
1307 if (ata_port_is_dummy(ap))
1308 continue;
1309
1310 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1311 }
1312
1313 tmp = readl(mmio + HOST_CTL);
1314 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1315 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1316 tmp = readl(mmio + HOST_CTL);
1317 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1318 }
1319 EXPORT_SYMBOL_GPL(ahci_init_controller);
1320
ahci_dev_config(struct ata_device * dev)1321 static void ahci_dev_config(struct ata_device *dev)
1322 {
1323 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1324
1325 if ((dev->class == ATA_DEV_ATAPI) &&
1326 (hpriv->flags & AHCI_HFLAG_ATAPI_DMA_QUIRK))
1327 dev->quirks |= ATA_QUIRK_ATAPI_MOD16_DMA;
1328
1329 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1330 dev->max_sectors = 255;
1331 ata_dev_info(dev,
1332 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1333 }
1334 }
1335
ahci_dev_classify(struct ata_port * ap)1336 unsigned int ahci_dev_classify(struct ata_port *ap)
1337 {
1338 void __iomem *port_mmio = ahci_port_base(ap);
1339 struct ata_taskfile tf;
1340 u32 tmp;
1341
1342 tmp = readl(port_mmio + PORT_SIG);
1343 tf.lbah = (tmp >> 24) & 0xff;
1344 tf.lbam = (tmp >> 16) & 0xff;
1345 tf.lbal = (tmp >> 8) & 0xff;
1346 tf.nsect = (tmp) & 0xff;
1347
1348 return ata_port_classify(ap, &tf);
1349 }
1350 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1351
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1352 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1353 u32 opts)
1354 {
1355 dma_addr_t cmd_tbl_dma;
1356
1357 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1358
1359 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1360 pp->cmd_slot[tag].status = 0;
1361 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1362 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1363 }
1364 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1365
ahci_kick_engine(struct ata_port * ap)1366 int ahci_kick_engine(struct ata_port *ap)
1367 {
1368 void __iomem *port_mmio = ahci_port_base(ap);
1369 struct ahci_host_priv *hpriv = ap->host->private_data;
1370 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1371 u32 tmp;
1372 int busy, rc;
1373
1374 /* stop engine */
1375 rc = hpriv->stop_engine(ap);
1376 if (rc)
1377 goto out_restart;
1378
1379 /* need to do CLO?
1380 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1381 */
1382 busy = status & (ATA_BUSY | ATA_DRQ);
1383 if (!busy && !sata_pmp_attached(ap)) {
1384 rc = 0;
1385 goto out_restart;
1386 }
1387
1388 if (!(hpriv->cap & HOST_CAP_CLO)) {
1389 rc = -EOPNOTSUPP;
1390 goto out_restart;
1391 }
1392
1393 /* perform CLO */
1394 tmp = readl(port_mmio + PORT_CMD);
1395 tmp |= PORT_CMD_CLO;
1396 writel(tmp, port_mmio + PORT_CMD);
1397
1398 rc = 0;
1399 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1400 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1401 if (tmp & PORT_CMD_CLO)
1402 rc = -EIO;
1403
1404 /* restart engine */
1405 out_restart:
1406 hpriv->start_engine(ap);
1407 return rc;
1408 }
1409 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1410
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned int timeout_msec)1411 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1412 struct ata_taskfile *tf, int is_cmd, u16 flags,
1413 unsigned int timeout_msec)
1414 {
1415 const u32 cmd_fis_len = 5; /* five dwords */
1416 struct ahci_port_priv *pp = ap->private_data;
1417 void __iomem *port_mmio = ahci_port_base(ap);
1418 u8 *fis = pp->cmd_tbl;
1419 u32 tmp;
1420
1421 /* prep the command */
1422 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1423 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1424
1425 /* set port value for softreset of Port Multiplier */
1426 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1427 tmp = readl(port_mmio + PORT_FBS);
1428 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1429 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1430 writel(tmp, port_mmio + PORT_FBS);
1431 pp->fbs_last_dev = pmp;
1432 }
1433
1434 /* issue & wait */
1435 writel(1, port_mmio + PORT_CMD_ISSUE);
1436
1437 if (timeout_msec) {
1438 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1439 0x1, 0x1, 1, timeout_msec);
1440 if (tmp & 0x1) {
1441 ahci_kick_engine(ap);
1442 return -EBUSY;
1443 }
1444 } else
1445 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1446
1447 return 0;
1448 }
1449
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1450 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1451 int pmp, unsigned long deadline,
1452 int (*check_ready)(struct ata_link *link))
1453 {
1454 struct ata_port *ap = link->ap;
1455 struct ahci_host_priv *hpriv = ap->host->private_data;
1456 struct ahci_port_priv *pp = ap->private_data;
1457 const char *reason = NULL;
1458 unsigned long now;
1459 unsigned int msecs;
1460 struct ata_taskfile tf;
1461 bool fbs_disabled = false;
1462 int rc;
1463
1464 /* prepare for SRST (AHCI-1.1 10.4.1) */
1465 rc = ahci_kick_engine(ap);
1466 if (rc && rc != -EOPNOTSUPP)
1467 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1468
1469 /*
1470 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1471 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1472 * that is attached to port multiplier.
1473 */
1474 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1475 ahci_disable_fbs(ap);
1476 fbs_disabled = true;
1477 }
1478
1479 ata_tf_init(link->device, &tf);
1480
1481 /* issue the first H2D Register FIS */
1482 msecs = 0;
1483 now = jiffies;
1484 if (time_after(deadline, now))
1485 msecs = jiffies_to_msecs(deadline - now);
1486
1487 tf.ctl |= ATA_SRST;
1488 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1489 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1490 rc = -EIO;
1491 reason = "1st FIS failed";
1492 goto fail;
1493 }
1494
1495 /* spec says at least 5us, but be generous and sleep for 1ms */
1496 ata_msleep(ap, 1);
1497
1498 /* issue the second H2D Register FIS */
1499 tf.ctl &= ~ATA_SRST;
1500 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1501
1502 /* wait for link to become ready */
1503 rc = ata_wait_after_reset(link, deadline, check_ready);
1504 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1505 /*
1506 * Workaround for cases where link online status can't
1507 * be trusted. Treat device readiness timeout as link
1508 * offline.
1509 */
1510 ata_link_info(link, "device not ready, treating as offline\n");
1511 *class = ATA_DEV_NONE;
1512 } else if (rc) {
1513 /* link occupied, -ENODEV too is an error */
1514 reason = "device not ready";
1515 goto fail;
1516 } else
1517 *class = ahci_dev_classify(ap);
1518
1519 /* re-enable FBS if disabled before */
1520 if (fbs_disabled)
1521 ahci_enable_fbs(ap);
1522
1523 return 0;
1524
1525 fail:
1526 ata_link_err(link, "softreset failed (%s)\n", reason);
1527 return rc;
1528 }
1529
ahci_check_ready(struct ata_link * link)1530 int ahci_check_ready(struct ata_link *link)
1531 {
1532 void __iomem *port_mmio = ahci_port_base(link->ap);
1533 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1534
1535 return ata_check_ready(status);
1536 }
1537 EXPORT_SYMBOL_GPL(ahci_check_ready);
1538
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1539 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1540 unsigned long deadline)
1541 {
1542 int pmp = sata_srst_pmp(link);
1543
1544 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1545 }
1546 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1547
ahci_bad_pmp_check_ready(struct ata_link * link)1548 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1549 {
1550 void __iomem *port_mmio = ahci_port_base(link->ap);
1551 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1552 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1553
1554 /*
1555 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1556 * which can save timeout delay.
1557 */
1558 if (irq_status & PORT_IRQ_BAD_PMP)
1559 return -EIO;
1560
1561 return ata_check_ready(status);
1562 }
1563
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1564 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1565 unsigned long deadline)
1566 {
1567 struct ata_port *ap = link->ap;
1568 void __iomem *port_mmio = ahci_port_base(ap);
1569 int pmp = sata_srst_pmp(link);
1570 int rc;
1571 u32 irq_sts;
1572
1573 rc = ahci_do_softreset(link, class, pmp, deadline,
1574 ahci_bad_pmp_check_ready);
1575
1576 /*
1577 * Soft reset fails with IPMS set when PMP is enabled but
1578 * SATA HDD/ODD is connected to SATA port, do soft reset
1579 * again to port 0.
1580 */
1581 if (rc == -EIO) {
1582 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1583 if (irq_sts & PORT_IRQ_BAD_PMP) {
1584 ata_link_warn(link,
1585 "applying PMP SRST workaround "
1586 "and retrying\n");
1587 rc = ahci_do_softreset(link, class, 0, deadline,
1588 ahci_check_ready);
1589 }
1590 }
1591
1592 return rc;
1593 }
1594
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1595 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1596 unsigned long deadline, bool *online)
1597 {
1598 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
1599 struct ata_port *ap = link->ap;
1600 struct ahci_port_priv *pp = ap->private_data;
1601 struct ahci_host_priv *hpriv = ap->host->private_data;
1602 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1603 struct ata_taskfile tf;
1604 int rc;
1605
1606 hpriv->stop_engine(ap);
1607
1608 /* clear D2H reception area to properly wait for D2H FIS */
1609 ata_tf_init(link->device, &tf);
1610 tf.status = ATA_BUSY;
1611 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1612
1613 ahci_port_clear_pending_irq(ap);
1614
1615 rc = sata_link_hardreset(link, timing, deadline, online,
1616 ahci_check_ready);
1617
1618 hpriv->start_engine(ap);
1619
1620 if (*online)
1621 *class = ahci_dev_classify(ap);
1622
1623 return rc;
1624 }
1625 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1626
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1627 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1628 unsigned long deadline)
1629 {
1630 bool online;
1631
1632 return ahci_do_hardreset(link, class, deadline, &online);
1633 }
1634
ahci_postreset(struct ata_link * link,unsigned int * class)1635 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1636 {
1637 struct ata_port *ap = link->ap;
1638 void __iomem *port_mmio = ahci_port_base(ap);
1639 u32 new_tmp, tmp;
1640
1641 ata_std_postreset(link, class);
1642
1643 /* Make sure port's ATAPI bit is set appropriately */
1644 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1645 if (*class == ATA_DEV_ATAPI)
1646 new_tmp |= PORT_CMD_ATAPI;
1647 else
1648 new_tmp &= ~PORT_CMD_ATAPI;
1649 if (new_tmp != tmp) {
1650 writel(new_tmp, port_mmio + PORT_CMD);
1651 readl(port_mmio + PORT_CMD); /* flush */
1652 }
1653 }
1654
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1655 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1656 {
1657 struct scatterlist *sg;
1658 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1659 unsigned int si;
1660
1661 /*
1662 * Next, the S/G list.
1663 */
1664 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1665 dma_addr_t addr = sg_dma_address(sg);
1666 u32 sg_len = sg_dma_len(sg);
1667
1668 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1669 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1670 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1671 }
1672
1673 return si;
1674 }
1675
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1676 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1677 {
1678 struct ata_port *ap = qc->ap;
1679 struct ahci_port_priv *pp = ap->private_data;
1680
1681 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1682 return ata_std_qc_defer(qc);
1683 else
1684 return sata_pmp_qc_defer_cmd_switch(qc);
1685 }
1686
ahci_qc_prep(struct ata_queued_cmd * qc)1687 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1688 {
1689 struct ata_port *ap = qc->ap;
1690 struct ahci_port_priv *pp = ap->private_data;
1691 int is_atapi = ata_is_atapi(qc->tf.protocol);
1692 void *cmd_tbl;
1693 u32 opts;
1694 const u32 cmd_fis_len = 5; /* five dwords */
1695 unsigned int n_elem;
1696
1697 /*
1698 * Fill in command table information. First, the header,
1699 * a SATA Register - Host to Device command FIS.
1700 */
1701 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1702
1703 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1704 if (is_atapi) {
1705 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1706 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1707 }
1708
1709 n_elem = 0;
1710 if (qc->flags & ATA_QCFLAG_DMAMAP)
1711 n_elem = ahci_fill_sg(qc, cmd_tbl);
1712
1713 /*
1714 * Fill in command slot information.
1715 */
1716 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1717 if (qc->tf.flags & ATA_TFLAG_WRITE)
1718 opts |= AHCI_CMD_WRITE;
1719 if (is_atapi)
1720 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1721
1722 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1723
1724 return AC_ERR_OK;
1725 }
1726
ahci_fbs_dec_intr(struct ata_port * ap)1727 static void ahci_fbs_dec_intr(struct ata_port *ap)
1728 {
1729 struct ahci_port_priv *pp = ap->private_data;
1730 void __iomem *port_mmio = ahci_port_base(ap);
1731 u32 fbs = readl(port_mmio + PORT_FBS);
1732 int retries = 3;
1733
1734 BUG_ON(!pp->fbs_enabled);
1735
1736 /* time to wait for DEC is not specified by AHCI spec,
1737 * add a retry loop for safety.
1738 */
1739 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1740 fbs = readl(port_mmio + PORT_FBS);
1741 while ((fbs & PORT_FBS_DEC) && retries--) {
1742 udelay(1);
1743 fbs = readl(port_mmio + PORT_FBS);
1744 }
1745
1746 if (fbs & PORT_FBS_DEC)
1747 dev_err(ap->host->dev, "failed to clear device error\n");
1748 }
1749
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1750 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1751 {
1752 struct ahci_host_priv *hpriv = ap->host->private_data;
1753 struct ahci_port_priv *pp = ap->private_data;
1754 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1755 struct ata_link *link = NULL;
1756 struct ata_queued_cmd *active_qc;
1757 struct ata_eh_info *active_ehi;
1758 bool fbs_need_dec = false;
1759 u32 serror;
1760
1761 /* determine active link with error */
1762 if (pp->fbs_enabled) {
1763 void __iomem *port_mmio = ahci_port_base(ap);
1764 u32 fbs = readl(port_mmio + PORT_FBS);
1765 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1766
1767 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1768 link = &ap->pmp_link[pmp];
1769 fbs_need_dec = true;
1770 }
1771
1772 } else
1773 ata_for_each_link(link, ap, EDGE)
1774 if (ata_link_active(link))
1775 break;
1776
1777 if (!link)
1778 link = &ap->link;
1779
1780 active_qc = ata_qc_from_tag(ap, link->active_tag);
1781 active_ehi = &link->eh_info;
1782
1783 /* record irq stat */
1784 ata_ehi_clear_desc(host_ehi);
1785 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1786
1787 /* AHCI needs SError cleared; otherwise, it might lock up */
1788 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1789 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1790 host_ehi->serror |= serror;
1791
1792 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1793 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1794 irq_stat &= ~PORT_IRQ_IF_ERR;
1795
1796 if (irq_stat & PORT_IRQ_TF_ERR) {
1797 /* If qc is active, charge it; otherwise, the active
1798 * link. There's no active qc on NCQ errors. It will
1799 * be determined by EH by reading log page 10h.
1800 */
1801 if (active_qc)
1802 active_qc->err_mask |= AC_ERR_DEV;
1803 else
1804 active_ehi->err_mask |= AC_ERR_DEV;
1805
1806 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1807 host_ehi->serror &= ~SERR_INTERNAL;
1808 }
1809
1810 if (irq_stat & PORT_IRQ_UNK_FIS) {
1811 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1812
1813 active_ehi->err_mask |= AC_ERR_HSM;
1814 active_ehi->action |= ATA_EH_RESET;
1815 ata_ehi_push_desc(active_ehi,
1816 "unknown FIS %08x %08x %08x %08x" ,
1817 unk[0], unk[1], unk[2], unk[3]);
1818 }
1819
1820 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1821 active_ehi->err_mask |= AC_ERR_HSM;
1822 active_ehi->action |= ATA_EH_RESET;
1823 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1824 }
1825
1826 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1827 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1828 host_ehi->action |= ATA_EH_RESET;
1829 ata_ehi_push_desc(host_ehi, "host bus error");
1830 }
1831
1832 if (irq_stat & PORT_IRQ_IF_ERR) {
1833 if (fbs_need_dec)
1834 active_ehi->err_mask |= AC_ERR_DEV;
1835 else {
1836 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1837 host_ehi->action |= ATA_EH_RESET;
1838 }
1839
1840 ata_ehi_push_desc(host_ehi, "interface fatal error");
1841 }
1842
1843 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1844 ata_ehi_hotplugged(host_ehi);
1845 ata_ehi_push_desc(host_ehi, "%s",
1846 irq_stat & PORT_IRQ_CONNECT ?
1847 "connection status changed" : "PHY RDY changed");
1848 }
1849
1850 /* okay, let's hand over to EH */
1851
1852 if (irq_stat & PORT_IRQ_FREEZE)
1853 ata_port_freeze(ap);
1854 else if (fbs_need_dec) {
1855 ata_link_abort(link);
1856 ahci_fbs_dec_intr(ap);
1857 } else
1858 ata_port_abort(ap);
1859 }
1860
ahci_qc_complete(struct ata_port * ap,void __iomem * port_mmio)1861 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio)
1862 {
1863 struct ata_eh_info *ehi = &ap->link.eh_info;
1864 struct ahci_port_priv *pp = ap->private_data;
1865 u32 qc_active = 0;
1866 int rc;
1867
1868 /*
1869 * pp->active_link is not reliable once FBS is enabled, both
1870 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1871 * NCQ and non-NCQ commands may be in flight at the same time.
1872 */
1873 if (pp->fbs_enabled) {
1874 if (ap->qc_active) {
1875 qc_active = readl(port_mmio + PORT_SCR_ACT);
1876 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1877 }
1878 } else {
1879 /* pp->active_link is valid iff any command is in flight */
1880 if (ap->qc_active && pp->active_link->sactive)
1881 qc_active = readl(port_mmio + PORT_SCR_ACT);
1882 else
1883 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1884 }
1885
1886 rc = ata_qc_complete_multiple(ap, qc_active);
1887 if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) {
1888 ehi->err_mask |= AC_ERR_HSM;
1889 ehi->action |= ATA_EH_RESET;
1890 ata_port_freeze(ap);
1891 }
1892 }
1893
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1894 static void ahci_handle_port_interrupt(struct ata_port *ap,
1895 void __iomem *port_mmio, u32 status)
1896 {
1897 struct ahci_port_priv *pp = ap->private_data;
1898 struct ahci_host_priv *hpriv = ap->host->private_data;
1899
1900 /* ignore BAD_PMP while resetting */
1901 if (unlikely(ap->pflags & ATA_PFLAG_RESETTING))
1902 status &= ~PORT_IRQ_BAD_PMP;
1903
1904 if (sata_lpm_ignore_phy_events(&ap->link)) {
1905 status &= ~PORT_IRQ_PHYRDY;
1906 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1907 }
1908
1909 if (unlikely(status & PORT_IRQ_ERROR)) {
1910 /*
1911 * Before getting the error notification, we may have
1912 * received SDB FISes notifying successful completions.
1913 * Handle these first and then handle the error.
1914 */
1915 ahci_qc_complete(ap, port_mmio);
1916 ahci_error_intr(ap, status);
1917 return;
1918 }
1919
1920 if (status & PORT_IRQ_SDB_FIS) {
1921 /* If SNotification is available, leave notification
1922 * handling to sata_async_notification(). If not,
1923 * emulate it by snooping SDB FIS RX area.
1924 *
1925 * Snooping FIS RX area is probably cheaper than
1926 * poking SNotification but some constrollers which
1927 * implement SNotification, ICH9 for example, don't
1928 * store AN SDB FIS into receive area.
1929 */
1930 if (hpriv->cap & HOST_CAP_SNTF)
1931 sata_async_notification(ap);
1932 else {
1933 /* If the 'N' bit in word 0 of the FIS is set,
1934 * we just received asynchronous notification.
1935 * Tell libata about it.
1936 *
1937 * Lack of SNotification should not appear in
1938 * ahci 1.2, so the workaround is unnecessary
1939 * when FBS is enabled.
1940 */
1941 if (pp->fbs_enabled)
1942 WARN_ON_ONCE(1);
1943 else {
1944 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1945 u32 f0 = le32_to_cpu(f[0]);
1946 if (f0 & (1 << 15))
1947 sata_async_notification(ap);
1948 }
1949 }
1950 }
1951
1952 /* Handle completed commands */
1953 ahci_qc_complete(ap, port_mmio);
1954 }
1955
ahci_port_intr(struct ata_port * ap)1956 static void ahci_port_intr(struct ata_port *ap)
1957 {
1958 void __iomem *port_mmio = ahci_port_base(ap);
1959 u32 status;
1960
1961 status = readl(port_mmio + PORT_IRQ_STAT);
1962 writel(status, port_mmio + PORT_IRQ_STAT);
1963
1964 ahci_handle_port_interrupt(ap, port_mmio, status);
1965 }
1966
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1967 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1968 {
1969 struct ata_port *ap = dev_instance;
1970 void __iomem *port_mmio = ahci_port_base(ap);
1971 u32 status;
1972
1973 status = readl(port_mmio + PORT_IRQ_STAT);
1974 writel(status, port_mmio + PORT_IRQ_STAT);
1975
1976 spin_lock(ap->lock);
1977 ahci_handle_port_interrupt(ap, port_mmio, status);
1978 spin_unlock(ap->lock);
1979
1980 return IRQ_HANDLED;
1981 }
1982
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1983 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1984 {
1985 unsigned int i, handled = 0;
1986
1987 for (i = 0; i < host->n_ports; i++) {
1988 struct ata_port *ap;
1989
1990 if (!(irq_masked & (1 << i)))
1991 continue;
1992
1993 ap = host->ports[i];
1994 if (ap) {
1995 ahci_port_intr(ap);
1996 } else {
1997 if (ata_ratelimit())
1998 dev_warn(host->dev,
1999 "interrupt on disabled port %u\n", i);
2000 }
2001
2002 handled = 1;
2003 }
2004
2005 return handled;
2006 }
2007 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
2008
ahci_single_level_irq_intr(int irq,void * dev_instance)2009 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
2010 {
2011 struct ata_host *host = dev_instance;
2012 struct ahci_host_priv *hpriv;
2013 unsigned int rc = 0;
2014 void __iomem *mmio;
2015 u32 irq_stat, irq_masked;
2016
2017 hpriv = host->private_data;
2018 mmio = hpriv->mmio;
2019
2020 /* sigh. 0xffffffff is a valid return from h/w */
2021 irq_stat = readl(mmio + HOST_IRQ_STAT);
2022 if (!irq_stat)
2023 return IRQ_NONE;
2024
2025 irq_masked = irq_stat & hpriv->port_map;
2026
2027 spin_lock(&host->lock);
2028
2029 rc = ahci_handle_port_intr(host, irq_masked);
2030
2031 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2032 * it should be cleared after all the port events are cleared;
2033 * otherwise, it will raise a spurious interrupt after each
2034 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2035 * information.
2036 *
2037 * Also, use the unmasked value to clear interrupt as spurious
2038 * pending event on a dummy port might cause screaming IRQ.
2039 */
2040 writel(irq_stat, mmio + HOST_IRQ_STAT);
2041
2042 spin_unlock(&host->lock);
2043
2044 return IRQ_RETVAL(rc);
2045 }
2046
ahci_qc_issue(struct ata_queued_cmd * qc)2047 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2048 {
2049 struct ata_port *ap = qc->ap;
2050 void __iomem *port_mmio = ahci_port_base(ap);
2051 struct ahci_port_priv *pp = ap->private_data;
2052
2053 /* Keep track of the currently active link. It will be used
2054 * in completion path to determine whether NCQ phase is in
2055 * progress.
2056 */
2057 pp->active_link = qc->dev->link;
2058
2059 if (ata_is_ncq(qc->tf.protocol))
2060 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2061
2062 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2063 u32 fbs = readl(port_mmio + PORT_FBS);
2064 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2065 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2066 writel(fbs, port_mmio + PORT_FBS);
2067 pp->fbs_last_dev = qc->dev->link->pmp;
2068 }
2069
2070 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2071
2072 ahci_sw_activity(qc->dev->link);
2073
2074 return 0;
2075 }
2076 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2077
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2078 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2079 {
2080 struct ahci_port_priv *pp = qc->ap->private_data;
2081 u8 *rx_fis = pp->rx_fis;
2082
2083 if (pp->fbs_enabled)
2084 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2085
2086 /*
2087 * After a successful execution of an ATA PIO data-in command,
2088 * the device doesn't send D2H Reg FIS to update the TF and
2089 * the host should take TF and E_Status from the preceding PIO
2090 * Setup FIS.
2091 */
2092 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2093 !(qc->flags & ATA_QCFLAG_EH)) {
2094 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2095 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
2096 return;
2097 }
2098
2099 /*
2100 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register
2101 * FIS area of the Received FIS Structure (which contains a copy of the
2102 * last D2H FIS received) will contain an outdated status code.
2103 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
2104 * instead. However, the SDB FIS does not contain the LBA, so we can't
2105 * use the ata_tf_from_fis() helper.
2106 */
2107 if (ata_is_ncq(qc->tf.protocol)) {
2108 const u8 *fis = rx_fis + RX_FIS_SDB;
2109
2110 /*
2111 * Successful NCQ commands have been filled already.
2112 * A failed NCQ command will read the status here.
2113 * (Note that a failed NCQ command will get a more specific
2114 * error when reading the NCQ Command Error log.)
2115 */
2116 qc->result_tf.status = fis[2];
2117 qc->result_tf.error = fis[3];
2118 return;
2119 }
2120
2121 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2122 }
2123
ahci_qc_ncq_fill_rtf(struct ata_port * ap,u64 done_mask)2124 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask)
2125 {
2126 struct ahci_port_priv *pp = ap->private_data;
2127 const u8 *fis;
2128
2129 /* No outstanding commands. */
2130 if (!ap->qc_active)
2131 return;
2132
2133 /*
2134 * FBS not enabled, so read status and error once, since they are shared
2135 * for all QCs.
2136 */
2137 if (!pp->fbs_enabled) {
2138 u8 status, error;
2139
2140 /* No outstanding NCQ commands. */
2141 if (!pp->active_link->sactive)
2142 return;
2143
2144 fis = pp->rx_fis + RX_FIS_SDB;
2145 status = fis[2];
2146 error = fis[3];
2147
2148 while (done_mask) {
2149 struct ata_queued_cmd *qc;
2150 unsigned int tag = __ffs64(done_mask);
2151
2152 qc = ata_qc_from_tag(ap, tag);
2153 if (qc && ata_is_ncq(qc->tf.protocol)) {
2154 qc->result_tf.status = status;
2155 qc->result_tf.error = error;
2156 qc->result_tf.flags = qc->tf.flags;
2157 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2158 }
2159 done_mask &= ~(1ULL << tag);
2160 }
2161
2162 return;
2163 }
2164
2165 /*
2166 * FBS enabled, so read the status and error for each QC, since the QCs
2167 * can belong to different PMP links. (Each PMP link has its own FIS
2168 * Receive Area.)
2169 */
2170 while (done_mask) {
2171 struct ata_queued_cmd *qc;
2172 unsigned int tag = __ffs64(done_mask);
2173
2174 qc = ata_qc_from_tag(ap, tag);
2175 if (qc && ata_is_ncq(qc->tf.protocol)) {
2176 fis = pp->rx_fis;
2177 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2178 fis += RX_FIS_SDB;
2179 qc->result_tf.status = fis[2];
2180 qc->result_tf.error = fis[3];
2181 qc->result_tf.flags = qc->tf.flags;
2182 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2183 }
2184 done_mask &= ~(1ULL << tag);
2185 }
2186 }
2187
ahci_freeze(struct ata_port * ap)2188 static void ahci_freeze(struct ata_port *ap)
2189 {
2190 void __iomem *port_mmio = ahci_port_base(ap);
2191
2192 /* turn IRQ off */
2193 writel(0, port_mmio + PORT_IRQ_MASK);
2194 }
2195
ahci_thaw(struct ata_port * ap)2196 static void ahci_thaw(struct ata_port *ap)
2197 {
2198 struct ahci_host_priv *hpriv = ap->host->private_data;
2199 void __iomem *mmio = hpriv->mmio;
2200 void __iomem *port_mmio = ahci_port_base(ap);
2201 u32 tmp;
2202 struct ahci_port_priv *pp = ap->private_data;
2203
2204 /* clear IRQ */
2205 tmp = readl(port_mmio + PORT_IRQ_STAT);
2206 writel(tmp, port_mmio + PORT_IRQ_STAT);
2207 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2208
2209 /* turn IRQ back on */
2210 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2211 }
2212
ahci_error_handler(struct ata_port * ap)2213 void ahci_error_handler(struct ata_port *ap)
2214 {
2215 struct ahci_host_priv *hpriv = ap->host->private_data;
2216
2217 if (!ata_port_is_frozen(ap)) {
2218 /* restart engine */
2219 hpriv->stop_engine(ap);
2220 hpriv->start_engine(ap);
2221 }
2222
2223 sata_pmp_error_handler(ap);
2224
2225 if (!ata_dev_enabled(ap->link.device))
2226 hpriv->stop_engine(ap);
2227 }
2228 EXPORT_SYMBOL_GPL(ahci_error_handler);
2229
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2230 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2231 {
2232 struct ata_port *ap = qc->ap;
2233
2234 /* make DMA engine forget about the failed command */
2235 if (qc->flags & ATA_QCFLAG_EH)
2236 ahci_kick_engine(ap);
2237 }
2238
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2239 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2240 {
2241 struct ahci_host_priv *hpriv = ap->host->private_data;
2242 void __iomem *port_mmio = ahci_port_base(ap);
2243 struct ata_device *dev = ap->link.device;
2244 u32 devslp, dm, dito, mdat, deto, dito_conf;
2245 int rc;
2246 unsigned int err_mask;
2247
2248 devslp = readl(port_mmio + PORT_DEVSLP);
2249 if (!(devslp & PORT_DEVSLP_DSP)) {
2250 dev_info(ap->host->dev, "port does not support device sleep\n");
2251 return;
2252 }
2253
2254 /* disable device sleep */
2255 if (!sleep) {
2256 if (devslp & PORT_DEVSLP_ADSE) {
2257 writel(devslp & ~PORT_DEVSLP_ADSE,
2258 port_mmio + PORT_DEVSLP);
2259 err_mask = ata_dev_set_feature(dev,
2260 SETFEATURES_SATA_DISABLE,
2261 SATA_DEVSLP);
2262 if (err_mask && err_mask != AC_ERR_DEV)
2263 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2264 }
2265 return;
2266 }
2267
2268 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2269 dito = devslp_idle_timeout / (dm + 1);
2270 if (dito > 0x3ff)
2271 dito = 0x3ff;
2272
2273 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2274
2275 /* device sleep was already enabled and same dito */
2276 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2277 return;
2278
2279 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2280 rc = hpriv->stop_engine(ap);
2281 if (rc)
2282 return;
2283
2284 /* Use the nominal value 10 ms if the read MDAT is zero,
2285 * the nominal value of DETO is 20 ms.
2286 */
2287 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2288 ATA_LOG_DEVSLP_VALID_MASK) {
2289 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2290 ATA_LOG_DEVSLP_MDAT_MASK;
2291 if (!mdat)
2292 mdat = 10;
2293 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2294 if (!deto)
2295 deto = 20;
2296 } else {
2297 mdat = 10;
2298 deto = 20;
2299 }
2300
2301 /* Make dito, mdat, deto bits to 0s */
2302 devslp &= ~GENMASK_ULL(24, 2);
2303 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2304 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2305 (deto << PORT_DEVSLP_DETO_OFFSET) |
2306 PORT_DEVSLP_ADSE);
2307 writel(devslp, port_mmio + PORT_DEVSLP);
2308
2309 hpriv->start_engine(ap);
2310
2311 /* enable device sleep feature for the drive */
2312 err_mask = ata_dev_set_feature(dev,
2313 SETFEATURES_SATA_ENABLE,
2314 SATA_DEVSLP);
2315 if (err_mask && err_mask != AC_ERR_DEV)
2316 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2317 }
2318
ahci_enable_fbs(struct ata_port * ap)2319 static void ahci_enable_fbs(struct ata_port *ap)
2320 {
2321 struct ahci_host_priv *hpriv = ap->host->private_data;
2322 struct ahci_port_priv *pp = ap->private_data;
2323 void __iomem *port_mmio = ahci_port_base(ap);
2324 u32 fbs;
2325 int rc;
2326
2327 if (!pp->fbs_supported)
2328 return;
2329
2330 fbs = readl(port_mmio + PORT_FBS);
2331 if (fbs & PORT_FBS_EN) {
2332 pp->fbs_enabled = true;
2333 pp->fbs_last_dev = -1; /* initialization */
2334 return;
2335 }
2336
2337 rc = hpriv->stop_engine(ap);
2338 if (rc)
2339 return;
2340
2341 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2342 fbs = readl(port_mmio + PORT_FBS);
2343 if (fbs & PORT_FBS_EN) {
2344 dev_info(ap->host->dev, "FBS is enabled\n");
2345 pp->fbs_enabled = true;
2346 pp->fbs_last_dev = -1; /* initialization */
2347 } else
2348 dev_err(ap->host->dev, "Failed to enable FBS\n");
2349
2350 hpriv->start_engine(ap);
2351 }
2352
ahci_disable_fbs(struct ata_port * ap)2353 static void ahci_disable_fbs(struct ata_port *ap)
2354 {
2355 struct ahci_host_priv *hpriv = ap->host->private_data;
2356 struct ahci_port_priv *pp = ap->private_data;
2357 void __iomem *port_mmio = ahci_port_base(ap);
2358 u32 fbs;
2359 int rc;
2360
2361 if (!pp->fbs_supported)
2362 return;
2363
2364 fbs = readl(port_mmio + PORT_FBS);
2365 if ((fbs & PORT_FBS_EN) == 0) {
2366 pp->fbs_enabled = false;
2367 return;
2368 }
2369
2370 rc = hpriv->stop_engine(ap);
2371 if (rc)
2372 return;
2373
2374 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2375 fbs = readl(port_mmio + PORT_FBS);
2376 if (fbs & PORT_FBS_EN)
2377 dev_err(ap->host->dev, "Failed to disable FBS\n");
2378 else {
2379 dev_info(ap->host->dev, "FBS is disabled\n");
2380 pp->fbs_enabled = false;
2381 }
2382
2383 hpriv->start_engine(ap);
2384 }
2385
ahci_pmp_attach(struct ata_port * ap)2386 static void ahci_pmp_attach(struct ata_port *ap)
2387 {
2388 void __iomem *port_mmio = ahci_port_base(ap);
2389 struct ahci_port_priv *pp = ap->private_data;
2390 u32 cmd;
2391
2392 cmd = readl(port_mmio + PORT_CMD);
2393 cmd |= PORT_CMD_PMP;
2394 writel(cmd, port_mmio + PORT_CMD);
2395
2396 ahci_enable_fbs(ap);
2397
2398 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2399
2400 /*
2401 * We must not change the port interrupt mask register if the
2402 * port is marked frozen, the value in pp->intr_mask will be
2403 * restored later when the port is thawed.
2404 *
2405 * Note that during initialization, the port is marked as
2406 * frozen since the irq handler is not yet registered.
2407 */
2408 if (!ata_port_is_frozen(ap))
2409 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2410 }
2411
ahci_pmp_detach(struct ata_port * ap)2412 static void ahci_pmp_detach(struct ata_port *ap)
2413 {
2414 void __iomem *port_mmio = ahci_port_base(ap);
2415 struct ahci_port_priv *pp = ap->private_data;
2416 u32 cmd;
2417
2418 ahci_disable_fbs(ap);
2419
2420 cmd = readl(port_mmio + PORT_CMD);
2421 cmd &= ~PORT_CMD_PMP;
2422 writel(cmd, port_mmio + PORT_CMD);
2423
2424 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2425
2426 /* see comment above in ahci_pmp_attach() */
2427 if (!ata_port_is_frozen(ap))
2428 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2429 }
2430
ahci_port_resume(struct ata_port * ap)2431 int ahci_port_resume(struct ata_port *ap)
2432 {
2433 ahci_rpm_get_port(ap);
2434
2435 ahci_power_up(ap);
2436 ahci_start_port(ap);
2437
2438 if (sata_pmp_attached(ap))
2439 ahci_pmp_attach(ap);
2440 else
2441 ahci_pmp_detach(ap);
2442
2443 return 0;
2444 }
2445 EXPORT_SYMBOL_GPL(ahci_port_resume);
2446
2447 #ifdef CONFIG_PM
ahci_handle_s2idle(struct ata_port * ap)2448 static void ahci_handle_s2idle(struct ata_port *ap)
2449 {
2450 void __iomem *port_mmio = ahci_port_base(ap);
2451 u32 devslp;
2452
2453 if (pm_suspend_via_firmware())
2454 return;
2455 devslp = readl(port_mmio + PORT_DEVSLP);
2456 if ((devslp & PORT_DEVSLP_ADSE))
2457 ata_msleep(ap, devslp_idle_timeout);
2458 }
2459
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2460 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2461 {
2462 const char *emsg = NULL;
2463 int rc;
2464
2465 rc = ahci_deinit_port(ap, &emsg);
2466 if (rc == 0)
2467 ahci_power_down(ap);
2468 else {
2469 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2470 ata_port_freeze(ap);
2471 }
2472
2473 if (acpi_storage_d3(ap->host->dev))
2474 ahci_handle_s2idle(ap);
2475
2476 ahci_rpm_put_port(ap);
2477 return rc;
2478 }
2479 #endif
2480
ahci_port_start(struct ata_port * ap)2481 static int ahci_port_start(struct ata_port *ap)
2482 {
2483 struct ahci_host_priv *hpriv = ap->host->private_data;
2484 struct device *dev = ap->host->dev;
2485 struct ahci_port_priv *pp;
2486 void *mem;
2487 dma_addr_t mem_dma;
2488 size_t dma_sz, rx_fis_sz;
2489
2490 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2491 if (!pp)
2492 return -ENOMEM;
2493
2494 if (ap->host->n_ports > 1) {
2495 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2496 if (!pp->irq_desc) {
2497 devm_kfree(dev, pp);
2498 return -ENOMEM;
2499 }
2500 snprintf(pp->irq_desc, 8,
2501 "%s%d", dev_driver_string(dev), ap->port_no);
2502 }
2503
2504 /* check FBS capability */
2505 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2506 void __iomem *port_mmio = ahci_port_base(ap);
2507 u32 cmd = readl(port_mmio + PORT_CMD);
2508 if (cmd & PORT_CMD_FBSCP)
2509 pp->fbs_supported = true;
2510 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2511 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2512 ap->port_no);
2513 pp->fbs_supported = true;
2514 } else
2515 dev_warn(dev, "port %d is not capable of FBS\n",
2516 ap->port_no);
2517 }
2518
2519 if (pp->fbs_supported) {
2520 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2521 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2522 } else {
2523 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2524 rx_fis_sz = AHCI_RX_FIS_SZ;
2525 }
2526
2527 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2528 if (!mem)
2529 return -ENOMEM;
2530
2531 /*
2532 * First item in chunk of DMA memory: 32-slot command table,
2533 * 32 bytes each in size
2534 */
2535 pp->cmd_slot = mem;
2536 pp->cmd_slot_dma = mem_dma;
2537
2538 mem += AHCI_CMD_SLOT_SZ;
2539 mem_dma += AHCI_CMD_SLOT_SZ;
2540
2541 /*
2542 * Second item: Received-FIS area
2543 */
2544 pp->rx_fis = mem;
2545 pp->rx_fis_dma = mem_dma;
2546
2547 mem += rx_fis_sz;
2548 mem_dma += rx_fis_sz;
2549
2550 /*
2551 * Third item: data area for storing a single command
2552 * and its scatter-gather table
2553 */
2554 pp->cmd_tbl = mem;
2555 pp->cmd_tbl_dma = mem_dma;
2556
2557 /*
2558 * Save off initial list of interrupts to be enabled.
2559 * This could be changed later
2560 */
2561 pp->intr_mask = DEF_PORT_IRQ;
2562
2563 /*
2564 * Switch to per-port locking in case each port has its own MSI vector.
2565 */
2566 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2567 spin_lock_init(&pp->lock);
2568 ap->lock = &pp->lock;
2569 }
2570
2571 ap->private_data = pp;
2572
2573 /* engage engines, captain */
2574 return ahci_port_resume(ap);
2575 }
2576
ahci_port_stop(struct ata_port * ap)2577 static void ahci_port_stop(struct ata_port *ap)
2578 {
2579 const char *emsg = NULL;
2580 struct ahci_host_priv *hpriv = ap->host->private_data;
2581 void __iomem *host_mmio = hpriv->mmio;
2582 int rc;
2583
2584 /* de-initialize port */
2585 rc = ahci_deinit_port(ap, &emsg);
2586 if (rc)
2587 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2588
2589 /*
2590 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2591 * re-enabling INTx.
2592 */
2593 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2594
2595 ahci_rpm_put_port(ap);
2596 }
2597
ahci_print_info(struct ata_host * host,const char * scc_s)2598 void ahci_print_info(struct ata_host *host, const char *scc_s)
2599 {
2600 struct ahci_host_priv *hpriv = host->private_data;
2601 u32 vers, cap, cap2, impl, speed;
2602 const char *speed_s;
2603
2604 vers = hpriv->version;
2605 cap = hpriv->cap;
2606 cap2 = hpriv->cap2;
2607 impl = hpriv->port_map;
2608
2609 speed = (cap >> 20) & 0xf;
2610 if (speed == 1)
2611 speed_s = "1.5";
2612 else if (speed == 2)
2613 speed_s = "3";
2614 else if (speed == 3)
2615 speed_s = "6";
2616 else
2617 speed_s = "?";
2618
2619 dev_info(host->dev,
2620 "AHCI vers %02x%02x.%02x%02x, "
2621 "%u command slots, %s Gbps, %s mode\n"
2622 ,
2623
2624 (vers >> 24) & 0xff,
2625 (vers >> 16) & 0xff,
2626 (vers >> 8) & 0xff,
2627 vers & 0xff,
2628
2629 ((cap >> 8) & 0x1f) + 1,
2630 speed_s,
2631 scc_s);
2632
2633 dev_info(host->dev,
2634 "%u/%u ports implemented (port mask 0x%x)\n"
2635 ,
2636
2637 hweight32(impl),
2638 (cap & 0x1f) + 1,
2639 impl);
2640
2641 dev_info(host->dev,
2642 "flags: "
2643 "%s%s%s%s%s%s%s"
2644 "%s%s%s%s%s%s%s"
2645 "%s%s%s%s%s%s%s"
2646 "%s%s\n"
2647 ,
2648
2649 cap & HOST_CAP_64 ? "64bit " : "",
2650 cap & HOST_CAP_NCQ ? "ncq " : "",
2651 cap & HOST_CAP_SNTF ? "sntf " : "",
2652 cap & HOST_CAP_MPS ? "ilck " : "",
2653 cap & HOST_CAP_SSS ? "stag " : "",
2654 cap & HOST_CAP_ALPM ? "pm " : "",
2655 cap & HOST_CAP_LED ? "led " : "",
2656 cap & HOST_CAP_CLO ? "clo " : "",
2657 cap & HOST_CAP_ONLY ? "only " : "",
2658 cap & HOST_CAP_PMP ? "pmp " : "",
2659 cap & HOST_CAP_FBS ? "fbs " : "",
2660 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2661 cap & HOST_CAP_SSC ? "slum " : "",
2662 cap & HOST_CAP_PART ? "part " : "",
2663 cap & HOST_CAP_CCC ? "ccc " : "",
2664 cap & HOST_CAP_EMS ? "ems " : "",
2665 cap & HOST_CAP_SXS ? "sxs " : "",
2666 cap2 & HOST_CAP2_DESO ? "deso " : "",
2667 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2668 cap2 & HOST_CAP2_SDS ? "sds " : "",
2669 cap2 & HOST_CAP2_APST ? "apst " : "",
2670 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2671 cap2 & HOST_CAP2_BOH ? "boh " : ""
2672 );
2673 }
2674 EXPORT_SYMBOL_GPL(ahci_print_info);
2675
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2676 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2677 struct ata_port_info *pi)
2678 {
2679 u8 messages;
2680 void __iomem *mmio = hpriv->mmio;
2681 u32 em_loc = readl(mmio + HOST_EM_LOC);
2682 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2683
2684 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2685 return;
2686
2687 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2688
2689 if (messages) {
2690 /* store em_loc */
2691 hpriv->em_loc = ((em_loc >> 16) * 4);
2692 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2693 hpriv->em_msg_type = messages;
2694 pi->flags |= ATA_FLAG_EM;
2695 if (!(em_ctl & EM_CTL_ALHD))
2696 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2697 }
2698 }
2699 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2700
ahci_host_activate_multi_irqs(struct ata_host * host,const struct scsi_host_template * sht)2701 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2702 const struct scsi_host_template *sht)
2703 {
2704 struct ahci_host_priv *hpriv = host->private_data;
2705 int i, rc;
2706
2707 rc = ata_host_start(host);
2708 if (rc)
2709 return rc;
2710 /*
2711 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2712 * allocated. That is one MSI per port, starting from @irq.
2713 */
2714 for (i = 0; i < host->n_ports; i++) {
2715 struct ahci_port_priv *pp = host->ports[i]->private_data;
2716 int irq = hpriv->get_irq_vector(host, i);
2717
2718 /* Do not receive interrupts sent by dummy ports */
2719 if (!pp) {
2720 disable_irq(irq);
2721 continue;
2722 }
2723
2724 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2725 0, pp->irq_desc, host->ports[i]);
2726
2727 if (rc)
2728 return rc;
2729 ata_port_desc_misc(host->ports[i], irq);
2730 }
2731
2732 return ata_host_register(host, sht);
2733 }
2734
2735 /**
2736 * ahci_host_activate - start AHCI host, request IRQs and register it
2737 * @host: target ATA host
2738 * @sht: scsi_host_template to use when registering the host
2739 *
2740 * LOCKING:
2741 * Inherited from calling layer (may sleep).
2742 *
2743 * RETURNS:
2744 * 0 on success, -errno otherwise.
2745 */
ahci_host_activate(struct ata_host * host,const struct scsi_host_template * sht)2746 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht)
2747 {
2748 struct ahci_host_priv *hpriv = host->private_data;
2749 int irq = hpriv->irq;
2750 int rc;
2751
2752 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2753 if (hpriv->irq_handler &&
2754 hpriv->irq_handler != ahci_single_level_irq_intr)
2755 dev_warn(host->dev,
2756 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2757 if (!hpriv->get_irq_vector) {
2758 dev_err(host->dev,
2759 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2760 return -EIO;
2761 }
2762
2763 rc = ahci_host_activate_multi_irqs(host, sht);
2764 } else {
2765 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2766 IRQF_SHARED, sht);
2767 }
2768
2769
2770 return rc;
2771 }
2772 EXPORT_SYMBOL_GPL(ahci_host_activate);
2773
2774 MODULE_AUTHOR("Jeff Garzik");
2775 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2776 MODULE_LICENSE("GPL");
2777