1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2023 Intel Corporation 4 */ 5 6#ifndef __ASSEMBLY__ 7#define __ASSEMBLY__ 8#endif 9 10#include <asm/csr.h> 11 12.macro save_context 13 addi sp, sp, (-8*36) 14 sd x1, 8(sp) 15 sd x2, 16(sp) 16 sd x3, 24(sp) 17 sd x4, 32(sp) 18 sd x5, 40(sp) 19 sd x6, 48(sp) 20 sd x7, 56(sp) 21 sd x8, 64(sp) 22 sd x9, 72(sp) 23 sd x10, 80(sp) 24 sd x11, 88(sp) 25 sd x12, 96(sp) 26 sd x13, 104(sp) 27 sd x14, 112(sp) 28 sd x15, 120(sp) 29 sd x16, 128(sp) 30 sd x17, 136(sp) 31 sd x18, 144(sp) 32 sd x19, 152(sp) 33 sd x20, 160(sp) 34 sd x21, 168(sp) 35 sd x22, 176(sp) 36 sd x23, 184(sp) 37 sd x24, 192(sp) 38 sd x25, 200(sp) 39 sd x26, 208(sp) 40 sd x27, 216(sp) 41 sd x28, 224(sp) 42 sd x29, 232(sp) 43 sd x30, 240(sp) 44 sd x31, 248(sp) 45 csrr s0, CSR_SEPC 46 csrr s1, CSR_SSTATUS 47 csrr s2, CSR_STVAL 48 csrr s3, CSR_SCAUSE 49 sd s0, 0(sp) 50 sd s1, 256(sp) 51 sd s2, 264(sp) 52 sd s3, 272(sp) 53.endm 54 55.macro restore_context 56 ld s3, 272(sp) 57 ld s2, 264(sp) 58 ld s1, 256(sp) 59 ld s0, 0(sp) 60 csrw CSR_SCAUSE, s3 61 csrw CSR_SSTATUS, s1 62 csrw CSR_SEPC, s0 63 ld x31, 248(sp) 64 ld x30, 240(sp) 65 ld x29, 232(sp) 66 ld x28, 224(sp) 67 ld x27, 216(sp) 68 ld x26, 208(sp) 69 ld x25, 200(sp) 70 ld x24, 192(sp) 71 ld x23, 184(sp) 72 ld x22, 176(sp) 73 ld x21, 168(sp) 74 ld x20, 160(sp) 75 ld x19, 152(sp) 76 ld x18, 144(sp) 77 ld x17, 136(sp) 78 ld x16, 128(sp) 79 ld x15, 120(sp) 80 ld x14, 112(sp) 81 ld x13, 104(sp) 82 ld x12, 96(sp) 83 ld x11, 88(sp) 84 ld x10, 80(sp) 85 ld x9, 72(sp) 86 ld x8, 64(sp) 87 ld x7, 56(sp) 88 ld x6, 48(sp) 89 ld x5, 40(sp) 90 ld x4, 32(sp) 91 ld x3, 24(sp) 92 ld x2, 16(sp) 93 ld x1, 8(sp) 94 addi sp, sp, (8*36) 95.endm 96 97.balign 4 98.global exception_vectors 99exception_vectors: 100 save_context 101 move a0, sp 102 call route_exception 103 restore_context 104 sret 105