1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 /* 25 * MSMC is configured by bootloaders and a runtime fixup is done in the 26 * DT for this node 27 */ 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x00 0x70000000 0x00 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x00 0x20000>; 37 }; 38 39 tifs-sram@1f0000 { 40 reg = <0x1f0000 0x10000>; 41 }; 42 43 l3cache-sram@200000 { 44 reg = <0x200000 0x200000>; 45 }; 46 }; 47 48 scm_conf: bus@100000 { 49 compatible = "simple-bus"; 50 reg = <0x00 0x00100000 0x00 0x1c000>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 ranges = <0x00 0x00 0x00100000 0x1c000>; 54 55 cpsw1_phy_gmii_sel: phy@4034 { 56 compatible = "ti,am654-phy-gmii-sel"; 57 reg = <0x4034 0x4>; 58 #phy-cells = <1>; 59 }; 60 61 cpsw0_phy_gmii_sel: phy@4044 { 62 compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; 63 reg = <0x4044 0x20>; 64 #phy-cells = <1>; 65 ti,qsgmii-main-ports = <7>, <7>; 66 }; 67 68 pcie0_ctrl: pcie0-ctrl@4070 { 69 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 70 reg = <0x4070 0x4>; 71 }; 72 73 pcie1_ctrl: pcie1-ctrl@4074 { 74 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 75 reg = <0x4074 0x4>; 76 }; 77 78 serdes_ln_ctrl: mux-controller@4080 { 79 compatible = "reg-mux"; 80 reg = <0x00004080 0x50>; 81 #mux-control-cells = <1>; 82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 83 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 85 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 87 <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ 88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 89 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 90 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 91 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 92 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 93 <J784S4_SERDES0_LANE3_USB>, 94 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 95 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 96 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 97 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 98 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 99 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 100 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 101 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 102 <J784S4_SERDES4_LANE0_EDP_LANE0>, 103 <J784S4_SERDES4_LANE1_EDP_LANE1>, 104 <J784S4_SERDES4_LANE2_EDP_LANE2>, 105 <J784S4_SERDES4_LANE3_EDP_LANE3>; 106 }; 107 108 usb_serdes_mux: mux-controller@4000 { 109 compatible = "reg-mux"; 110 reg = <0x4000 0x4>; 111 #mux-control-cells = <1>; 112 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ 113 }; 114 115 ehrpwm_tbclk: clock-controller@4140 { 116 compatible = "ti,am654-ehrpwm-tbclk"; 117 reg = <0x4140 0x18>; 118 #clock-cells = <1>; 119 }; 120 121 audio_refclk1: clock@82e4 { 122 compatible = "ti,am62-audio-refclk"; 123 reg = <0x82e4 0x4>; 124 clocks = <&k3_clks 157 34>; 125 assigned-clocks = <&k3_clks 157 34>; 126 assigned-clock-parents = <&k3_clks 157 63>; 127 #clock-cells = <0>; 128 }; 129 130 acspcie0_proxy_ctrl: clock-controller@1a090 { 131 compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; 132 reg = <0x1a090 0x4>; 133 }; 134 }; 135 136 main_ehrpwm0: pwm@3000000 { 137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 138 reg = <0x00 0x3000000 0x00 0x100>; 139 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; 140 clock-names = "tbclk", "fck"; 141 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 142 #pwm-cells = <3>; 143 status = "disabled"; 144 }; 145 146 main_ehrpwm1: pwm@3010000 { 147 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 148 reg = <0x00 0x3010000 0x00 0x100>; 149 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; 150 clock-names = "tbclk", "fck"; 151 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 152 #pwm-cells = <3>; 153 status = "disabled"; 154 }; 155 156 main_ehrpwm2: pwm@3020000 { 157 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 158 reg = <0x00 0x3020000 0x00 0x100>; 159 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; 160 clock-names = "tbclk", "fck"; 161 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 162 #pwm-cells = <3>; 163 status = "disabled"; 164 }; 165 166 main_ehrpwm3: pwm@3030000 { 167 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 168 reg = <0x00 0x3030000 0x00 0x100>; 169 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; 170 clock-names = "tbclk", "fck"; 171 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 172 #pwm-cells = <3>; 173 status = "disabled"; 174 }; 175 176 main_ehrpwm4: pwm@3040000 { 177 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 178 reg = <0x00 0x3040000 0x00 0x100>; 179 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; 180 clock-names = "tbclk", "fck"; 181 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 182 #pwm-cells = <3>; 183 status = "disabled"; 184 }; 185 186 main_ehrpwm5: pwm@3050000 { 187 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 188 reg = <0x00 0x3050000 0x00 0x100>; 189 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; 190 clock-names = "tbclk", "fck"; 191 power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; 192 #pwm-cells = <3>; 193 status = "disabled"; 194 }; 195 196 gic500: interrupt-controller@1800000 { 197 compatible = "arm,gic-v3"; 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 #interrupt-cells = <3>; 202 interrupt-controller; 203 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 204 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 205 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 206 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 207 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 208 209 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 210 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 211 212 gic_its: msi-controller@1820000 { 213 compatible = "arm,gic-v3-its"; 214 reg = <0x00 0x01820000 0x00 0x10000>; 215 socionext,synquacer-pre-its = <0x1000000 0x400000>; 216 msi-controller; 217 #msi-cells = <1>; 218 }; 219 }; 220 221 main_gpio_intr: interrupt-controller@a00000 { 222 compatible = "ti,sci-intr"; 223 reg = <0x00 0x00a00000 0x00 0x800>; 224 ti,intr-trigger-type = <1>; 225 interrupt-controller; 226 interrupt-parent = <&gic500>; 227 #interrupt-cells = <1>; 228 ti,sci = <&sms>; 229 ti,sci-dev-id = <10>; 230 ti,interrupt-ranges = <8 392 56>; 231 }; 232 233 main_pmx0: pinctrl@11c000 { 234 compatible = "ti,j7200-padconf", "pinctrl-single"; 235 /* Proxy 0 addressing */ 236 reg = <0x00 0x11c000 0x00 0x120>; 237 #pinctrl-cells = <1>; 238 pinctrl-single,register-width = <32>; 239 pinctrl-single,function-mask = <0xffffffff>; 240 }; 241 242 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 243 main_timerio_input: pinctrl@104200 { 244 compatible = "ti,j7200-padconf", "pinctrl-single"; 245 reg = <0x00 0x104200 0x00 0x50>; 246 #pinctrl-cells = <1>; 247 pinctrl-single,register-width = <32>; 248 pinctrl-single,function-mask = <0x00000007>; 249 }; 250 251 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 252 main_timerio_output: pinctrl@104280 { 253 compatible = "ti,j7200-padconf", "pinctrl-single"; 254 reg = <0x00 0x104280 0x00 0x20>; 255 #pinctrl-cells = <1>; 256 pinctrl-single,register-width = <32>; 257 pinctrl-single,function-mask = <0x0000001f>; 258 }; 259 260 main_crypto: crypto@4e00000 { 261 compatible = "ti,j721e-sa2ul"; 262 reg = <0x00 0x4e00000 0x00 0x1200>; 263 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 264 #address-cells = <2>; 265 #size-cells = <2>; 266 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 267 268 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 269 <&main_udmap 0x4a41>; 270 dma-names = "tx", "rx1", "rx2"; 271 272 rng: rng@4e10000 { 273 compatible = "inside-secure,safexcel-eip76"; 274 reg = <0x00 0x4e10000 0x00 0x7d>; 275 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 }; 278 279 main_timer0: timer@2400000 { 280 compatible = "ti,am654-timer"; 281 reg = <0x00 0x2400000 0x00 0x400>; 282 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&k3_clks 97 2>; 284 clock-names = "fck"; 285 assigned-clocks = <&k3_clks 97 2>; 286 assigned-clock-parents = <&k3_clks 97 3>; 287 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 288 ti,timer-pwm; 289 }; 290 291 main_timer1: timer@2410000 { 292 compatible = "ti,am654-timer"; 293 reg = <0x00 0x2410000 0x00 0x400>; 294 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&k3_clks 98 2>; 296 clock-names = "fck"; 297 assigned-clocks = <&k3_clks 98 2>; 298 assigned-clock-parents = <&k3_clks 98 3>; 299 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 300 ti,timer-pwm; 301 }; 302 303 main_timer2: timer@2420000 { 304 compatible = "ti,am654-timer"; 305 reg = <0x00 0x2420000 0x00 0x400>; 306 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&k3_clks 99 2>; 308 clock-names = "fck"; 309 assigned-clocks = <&k3_clks 99 2>; 310 assigned-clock-parents = <&k3_clks 99 3>; 311 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 312 ti,timer-pwm; 313 }; 314 315 main_timer3: timer@2430000 { 316 compatible = "ti,am654-timer"; 317 reg = <0x00 0x2430000 0x00 0x400>; 318 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&k3_clks 100 2>; 320 clock-names = "fck"; 321 assigned-clocks = <&k3_clks 100 2>; 322 assigned-clock-parents = <&k3_clks 100 3>; 323 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 324 ti,timer-pwm; 325 }; 326 327 main_timer4: timer@2440000 { 328 compatible = "ti,am654-timer"; 329 reg = <0x00 0x2440000 0x00 0x400>; 330 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&k3_clks 101 2>; 332 clock-names = "fck"; 333 assigned-clocks = <&k3_clks 101 2>; 334 assigned-clock-parents = <&k3_clks 101 3>; 335 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 336 ti,timer-pwm; 337 }; 338 339 main_timer5: timer@2450000 { 340 compatible = "ti,am654-timer"; 341 reg = <0x00 0x2450000 0x00 0x400>; 342 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&k3_clks 102 2>; 344 clock-names = "fck"; 345 assigned-clocks = <&k3_clks 102 2>; 346 assigned-clock-parents = <&k3_clks 102 3>; 347 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 348 ti,timer-pwm; 349 }; 350 351 main_timer6: timer@2460000 { 352 compatible = "ti,am654-timer"; 353 reg = <0x00 0x2460000 0x00 0x400>; 354 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&k3_clks 103 2>; 356 clock-names = "fck"; 357 assigned-clocks = <&k3_clks 103 2>; 358 assigned-clock-parents = <&k3_clks 103 3>; 359 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 360 ti,timer-pwm; 361 }; 362 363 main_timer7: timer@2470000 { 364 compatible = "ti,am654-timer"; 365 reg = <0x00 0x2470000 0x00 0x400>; 366 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&k3_clks 104 2>; 368 clock-names = "fck"; 369 assigned-clocks = <&k3_clks 104 2>; 370 assigned-clock-parents = <&k3_clks 104 3>; 371 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 372 ti,timer-pwm; 373 }; 374 375 main_timer8: timer@2480000 { 376 compatible = "ti,am654-timer"; 377 reg = <0x00 0x2480000 0x00 0x400>; 378 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&k3_clks 105 2>; 380 clock-names = "fck"; 381 assigned-clocks = <&k3_clks 105 2>; 382 assigned-clock-parents = <&k3_clks 105 3>; 383 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 384 ti,timer-pwm; 385 }; 386 387 main_timer9: timer@2490000 { 388 compatible = "ti,am654-timer"; 389 reg = <0x00 0x2490000 0x00 0x400>; 390 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&k3_clks 106 2>; 392 clock-names = "fck"; 393 assigned-clocks = <&k3_clks 106 2>; 394 assigned-clock-parents = <&k3_clks 106 3>; 395 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 396 ti,timer-pwm; 397 }; 398 399 main_timer10: timer@24a0000 { 400 compatible = "ti,am654-timer"; 401 reg = <0x00 0x24a0000 0x00 0x400>; 402 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&k3_clks 107 2>; 404 clock-names = "fck"; 405 assigned-clocks = <&k3_clks 107 2>; 406 assigned-clock-parents = <&k3_clks 107 3>; 407 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 408 ti,timer-pwm; 409 }; 410 411 main_timer11: timer@24b0000 { 412 compatible = "ti,am654-timer"; 413 reg = <0x00 0x24b0000 0x00 0x400>; 414 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&k3_clks 108 2>; 416 clock-names = "fck"; 417 assigned-clocks = <&k3_clks 108 2>; 418 assigned-clock-parents = <&k3_clks 108 3>; 419 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 420 ti,timer-pwm; 421 }; 422 423 main_timer12: timer@24c0000 { 424 compatible = "ti,am654-timer"; 425 reg = <0x00 0x24c0000 0x00 0x400>; 426 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&k3_clks 109 2>; 428 clock-names = "fck"; 429 assigned-clocks = <&k3_clks 109 2>; 430 assigned-clock-parents = <&k3_clks 109 3>; 431 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 432 ti,timer-pwm; 433 }; 434 435 main_timer13: timer@24d0000 { 436 compatible = "ti,am654-timer"; 437 reg = <0x00 0x24d0000 0x00 0x400>; 438 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&k3_clks 110 2>; 440 clock-names = "fck"; 441 assigned-clocks = <&k3_clks 110 2>; 442 assigned-clock-parents = <&k3_clks 110 3>; 443 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 444 ti,timer-pwm; 445 }; 446 447 main_timer14: timer@24e0000 { 448 compatible = "ti,am654-timer"; 449 reg = <0x00 0x24e0000 0x00 0x400>; 450 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&k3_clks 111 2>; 452 clock-names = "fck"; 453 assigned-clocks = <&k3_clks 111 2>; 454 assigned-clock-parents = <&k3_clks 111 3>; 455 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 456 ti,timer-pwm; 457 }; 458 459 main_timer15: timer@24f0000 { 460 compatible = "ti,am654-timer"; 461 reg = <0x00 0x24f0000 0x00 0x400>; 462 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&k3_clks 112 2>; 464 clock-names = "fck"; 465 assigned-clocks = <&k3_clks 112 2>; 466 assigned-clock-parents = <&k3_clks 112 3>; 467 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 468 ti,timer-pwm; 469 }; 470 471 main_timer16: timer@2500000 { 472 compatible = "ti,am654-timer"; 473 reg = <0x00 0x2500000 0x00 0x400>; 474 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&k3_clks 113 2>; 476 clock-names = "fck"; 477 assigned-clocks = <&k3_clks 113 2>; 478 assigned-clock-parents = <&k3_clks 113 3>; 479 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 480 ti,timer-pwm; 481 }; 482 483 main_timer17: timer@2510000 { 484 compatible = "ti,am654-timer"; 485 reg = <0x00 0x2510000 0x00 0x400>; 486 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&k3_clks 114 2>; 488 clock-names = "fck"; 489 assigned-clocks = <&k3_clks 114 2>; 490 assigned-clock-parents = <&k3_clks 114 3>; 491 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 492 ti,timer-pwm; 493 }; 494 495 main_timer18: timer@2520000 { 496 compatible = "ti,am654-timer"; 497 reg = <0x00 0x2520000 0x00 0x400>; 498 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&k3_clks 115 2>; 500 clock-names = "fck"; 501 assigned-clocks = <&k3_clks 115 2>; 502 assigned-clock-parents = <&k3_clks 115 3>; 503 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 504 ti,timer-pwm; 505 }; 506 507 main_timer19: timer@2530000 { 508 compatible = "ti,am654-timer"; 509 reg = <0x00 0x2530000 0x00 0x400>; 510 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&k3_clks 116 2>; 512 clock-names = "fck"; 513 assigned-clocks = <&k3_clks 116 2>; 514 assigned-clock-parents = <&k3_clks 116 3>; 515 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 516 ti,timer-pwm; 517 }; 518 519 main_uart0: serial@2800000 { 520 compatible = "ti,j721e-uart", "ti,am654-uart"; 521 reg = <0x00 0x02800000 0x00 0x200>; 522 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&k3_clks 146 0>; 524 clock-names = "fclk"; 525 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 526 status = "disabled"; 527 }; 528 529 main_uart1: serial@2810000 { 530 compatible = "ti,j721e-uart", "ti,am654-uart"; 531 reg = <0x00 0x02810000 0x00 0x200>; 532 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&k3_clks 388 0>; 534 clock-names = "fclk"; 535 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 536 status = "disabled"; 537 }; 538 539 main_uart2: serial@2820000 { 540 compatible = "ti,j721e-uart", "ti,am654-uart"; 541 reg = <0x00 0x02820000 0x00 0x200>; 542 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&k3_clks 389 0>; 544 clock-names = "fclk"; 545 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 546 status = "disabled"; 547 }; 548 549 main_uart3: serial@2830000 { 550 compatible = "ti,j721e-uart", "ti,am654-uart"; 551 reg = <0x00 0x02830000 0x00 0x200>; 552 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&k3_clks 390 0>; 554 clock-names = "fclk"; 555 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 556 status = "disabled"; 557 }; 558 559 main_uart4: serial@2840000 { 560 compatible = "ti,j721e-uart", "ti,am654-uart"; 561 reg = <0x00 0x02840000 0x00 0x200>; 562 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&k3_clks 391 0>; 564 clock-names = "fclk"; 565 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 566 status = "disabled"; 567 }; 568 569 main_uart5: serial@2850000 { 570 compatible = "ti,j721e-uart", "ti,am654-uart"; 571 reg = <0x00 0x02850000 0x00 0x200>; 572 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&k3_clks 392 0>; 574 clock-names = "fclk"; 575 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 576 status = "disabled"; 577 }; 578 579 main_uart6: serial@2860000 { 580 compatible = "ti,j721e-uart", "ti,am654-uart"; 581 reg = <0x00 0x02860000 0x00 0x200>; 582 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&k3_clks 393 0>; 584 clock-names = "fclk"; 585 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 586 status = "disabled"; 587 }; 588 589 main_uart7: serial@2870000 { 590 compatible = "ti,j721e-uart", "ti,am654-uart"; 591 reg = <0x00 0x02870000 0x00 0x200>; 592 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&k3_clks 394 0>; 594 clock-names = "fclk"; 595 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 596 status = "disabled"; 597 }; 598 599 main_uart8: serial@2880000 { 600 compatible = "ti,j721e-uart", "ti,am654-uart"; 601 reg = <0x00 0x02880000 0x00 0x200>; 602 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&k3_clks 395 0>; 604 clock-names = "fclk"; 605 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 606 status = "disabled"; 607 }; 608 609 main_uart9: serial@2890000 { 610 compatible = "ti,j721e-uart", "ti,am654-uart"; 611 reg = <0x00 0x02890000 0x00 0x200>; 612 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&k3_clks 396 0>; 614 clock-names = "fclk"; 615 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 616 status = "disabled"; 617 }; 618 619 main_gpio0: gpio@600000 { 620 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 621 reg = <0x00 0x00600000 0x00 0x100>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 interrupt-parent = <&main_gpio_intr>; 625 interrupts = <145>, <146>, <147>, <148>, <149>; 626 interrupt-controller; 627 #interrupt-cells = <2>; 628 ti,ngpio = <66>; 629 ti,davinci-gpio-unbanked = <0>; 630 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 631 clocks = <&k3_clks 163 0>; 632 clock-names = "gpio"; 633 status = "disabled"; 634 }; 635 636 main_gpio2: gpio@610000 { 637 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 638 reg = <0x00 0x00610000 0x00 0x100>; 639 gpio-controller; 640 #gpio-cells = <2>; 641 interrupt-parent = <&main_gpio_intr>; 642 interrupts = <154>, <155>, <156>, <157>, <158>; 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 ti,ngpio = <66>; 646 ti,davinci-gpio-unbanked = <0>; 647 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 648 clocks = <&k3_clks 164 0>; 649 clock-names = "gpio"; 650 status = "disabled"; 651 }; 652 653 main_gpio4: gpio@620000 { 654 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 655 reg = <0x00 0x00620000 0x00 0x100>; 656 gpio-controller; 657 #gpio-cells = <2>; 658 interrupt-parent = <&main_gpio_intr>; 659 interrupts = <163>, <164>, <165>, <166>, <167>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 ti,ngpio = <66>; 663 ti,davinci-gpio-unbanked = <0>; 664 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 665 clocks = <&k3_clks 165 0>; 666 clock-names = "gpio"; 667 status = "disabled"; 668 }; 669 670 main_gpio6: gpio@630000 { 671 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 672 reg = <0x00 0x00630000 0x00 0x100>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 interrupt-parent = <&main_gpio_intr>; 676 interrupts = <172>, <173>, <174>, <175>, <176>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 ti,ngpio = <66>; 680 ti,davinci-gpio-unbanked = <0>; 681 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 682 clocks = <&k3_clks 166 0>; 683 clock-names = "gpio"; 684 status = "disabled"; 685 }; 686 687 usbss0: usb@4104000 { 688 bootph-all; 689 compatible = "ti,j721e-usb"; 690 reg = <0x00 0x4104000 0x00 0x100>; 691 dma-coherent; 692 power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; 693 clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; 694 clock-names = "ref", "lpm"; 695 assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ 696 assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ 697 #address-cells = <2>; 698 #size-cells = <2>; 699 ranges; 700 701 status = "disabled"; /* Needs lane config */ 702 703 usb0: usb@6000000 { 704 bootph-all; 705 compatible = "cdns,usb3"; 706 reg = <0x00 0x6000000 0x00 0x10000>, 707 <0x00 0x6010000 0x00 0x10000>, 708 <0x00 0x6020000 0x00 0x10000>; 709 reg-names = "otg", "xhci", "dev"; 710 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 711 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 712 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 713 interrupt-names = "host", 714 "peripheral", 715 "otg"; 716 }; 717 }; 718 719 main_i2c0: i2c@2000000 { 720 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 721 reg = <0x00 0x02000000 0x00 0x100>; 722 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 clocks = <&k3_clks 270 2>; 726 clock-names = "fck"; 727 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 728 status = "disabled"; 729 }; 730 731 main_i2c1: i2c@2010000 { 732 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 733 reg = <0x00 0x02010000 0x00 0x100>; 734 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 clocks = <&k3_clks 271 2>; 738 clock-names = "fck"; 739 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 740 status = "disabled"; 741 }; 742 743 main_i2c2: i2c@2020000 { 744 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 745 reg = <0x00 0x02020000 0x00 0x100>; 746 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 clocks = <&k3_clks 272 2>; 750 clock-names = "fck"; 751 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 752 status = "disabled"; 753 }; 754 755 main_i2c3: i2c@2030000 { 756 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 757 reg = <0x00 0x02030000 0x00 0x100>; 758 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&k3_clks 273 2>; 762 clock-names = "fck"; 763 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 764 status = "disabled"; 765 }; 766 767 main_i2c4: i2c@2040000 { 768 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 769 reg = <0x00 0x02040000 0x00 0x100>; 770 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 clocks = <&k3_clks 274 2>; 774 clock-names = "fck"; 775 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 776 status = "disabled"; 777 }; 778 779 main_i2c5: i2c@2050000 { 780 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 781 reg = <0x00 0x02050000 0x00 0x100>; 782 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 clocks = <&k3_clks 275 2>; 786 clock-names = "fck"; 787 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 788 status = "disabled"; 789 }; 790 791 main_i2c6: i2c@2060000 { 792 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 793 reg = <0x00 0x02060000 0x00 0x100>; 794 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 clocks = <&k3_clks 276 2>; 798 clock-names = "fck"; 799 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 800 status = "disabled"; 801 }; 802 803 ti_csi2rx0: ticsi2rx@4500000 { 804 compatible = "ti,j721e-csi2rx-shim"; 805 reg = <0x00 0x04500000 0x00 0x00001000>; 806 ranges; 807 #address-cells = <2>; 808 #size-cells = <2>; 809 dmas = <&main_bcdma_csi 0 0x4940 0>; 810 dma-names = "rx0"; 811 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 812 status = "disabled"; 813 814 cdns_csi2rx0: csi-bridge@4504000 { 815 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 816 reg = <0x00 0x04504000 0x00 0x00001000>; 817 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 818 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 819 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 820 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 821 phys = <&dphy0>; 822 phy-names = "dphy"; 823 824 ports { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 csi0_port0: port@0 { 829 reg = <0>; 830 status = "disabled"; 831 }; 832 833 csi0_port1: port@1 { 834 reg = <1>; 835 status = "disabled"; 836 }; 837 838 csi0_port2: port@2 { 839 reg = <2>; 840 status = "disabled"; 841 }; 842 843 csi0_port3: port@3 { 844 reg = <3>; 845 status = "disabled"; 846 }; 847 848 csi0_port4: port@4 { 849 reg = <4>; 850 status = "disabled"; 851 }; 852 }; 853 }; 854 }; 855 856 ti_csi2rx1: ticsi2rx@4510000 { 857 compatible = "ti,j721e-csi2rx-shim"; 858 reg = <0x00 0x04510000 0x00 0x1000>; 859 ranges; 860 #address-cells = <2>; 861 #size-cells = <2>; 862 dmas = <&main_bcdma_csi 0 0x4960 0>; 863 dma-names = "rx0"; 864 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 865 status = "disabled"; 866 867 cdns_csi2rx1: csi-bridge@4514000 { 868 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 869 reg = <0x00 0x04514000 0x00 0x00001000>; 870 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 871 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 872 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 873 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 874 phys = <&dphy1>; 875 phy-names = "dphy"; 876 ports { 877 #address-cells = <1>; 878 #size-cells = <0>; 879 880 csi1_port0: port@0 { 881 reg = <0>; 882 status = "disabled"; 883 }; 884 885 csi1_port1: port@1 { 886 reg = <1>; 887 status = "disabled"; 888 }; 889 890 csi1_port2: port@2 { 891 reg = <2>; 892 status = "disabled"; 893 }; 894 895 csi1_port3: port@3 { 896 reg = <3>; 897 status = "disabled"; 898 }; 899 900 csi1_port4: port@4 { 901 reg = <4>; 902 status = "disabled"; 903 }; 904 }; 905 }; 906 }; 907 908 ti_csi2rx2: ticsi2rx@4520000 { 909 compatible = "ti,j721e-csi2rx-shim"; 910 reg = <0x00 0x04520000 0x00 0x00001000>; 911 ranges; 912 #address-cells = <2>; 913 #size-cells = <2>; 914 dmas = <&main_bcdma_csi 0 0x4980 0>; 915 dma-names = "rx0"; 916 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 917 status = "disabled"; 918 919 cdns_csi2rx2: csi-bridge@4524000 { 920 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 921 reg = <0x00 0x04524000 0x00 0x00001000>; 922 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 923 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 924 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 925 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 926 phys = <&dphy2>; 927 phy-names = "dphy"; 928 929 ports { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 csi2_port0: port@0 { 934 reg = <0>; 935 status = "disabled"; 936 }; 937 938 csi2_port1: port@1 { 939 reg = <1>; 940 status = "disabled"; 941 }; 942 943 csi2_port2: port@2 { 944 reg = <2>; 945 status = "disabled"; 946 }; 947 948 csi2_port3: port@3 { 949 reg = <3>; 950 status = "disabled"; 951 }; 952 953 csi2_port4: port@4 { 954 reg = <4>; 955 status = "disabled"; 956 }; 957 }; 958 }; 959 }; 960 961 dphy0: phy@4580000 { 962 compatible = "cdns,dphy-rx"; 963 reg = <0x00 0x04580000 0x00 0x00001100>; 964 #phy-cells = <0>; 965 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 966 status = "disabled"; 967 }; 968 969 dphy1: phy@4590000 { 970 compatible = "cdns,dphy-rx"; 971 reg = <0x00 0x04590000 0x00 0x00001100>; 972 #phy-cells = <0>; 973 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 974 status = "disabled"; 975 }; 976 977 dphy2: phy@45a0000 { 978 compatible = "cdns,dphy-rx"; 979 reg = <0x00 0x045a0000 0x00 0x00001100>; 980 #phy-cells = <0>; 981 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 982 status = "disabled"; 983 }; 984 985 vpu0: video-codec@4210000 { 986 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 987 reg = <0x00 0x4210000 0x00 0x10000>; 988 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&k3_clks 241 2>; 990 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 991 }; 992 993 vpu1: video-codec@4220000 { 994 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 995 reg = <0x00 0x4220000 0x00 0x10000>; 996 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&k3_clks 242 2>; 998 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 999 }; 1000 1001 main_sdhci0: mmc@4f80000 { 1002 compatible = "ti,j721e-sdhci-8bit"; 1003 reg = <0x00 0x04f80000 0x00 0x1000>, 1004 <0x00 0x04f88000 0x00 0x400>; 1005 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1006 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 1007 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 1008 clock-names = "clk_ahb", "clk_xin"; 1009 assigned-clocks = <&k3_clks 140 2>; 1010 assigned-clock-parents = <&k3_clks 140 3>; 1011 bus-width = <8>; 1012 ti,otap-del-sel-legacy = <0x0>; 1013 ti,otap-del-sel-mmc-hs = <0x0>; 1014 ti,otap-del-sel-ddr52 = <0x6>; 1015 ti,otap-del-sel-hs200 = <0x8>; 1016 ti,otap-del-sel-hs400 = <0x5>; 1017 ti,itap-del-sel-legacy = <0x10>; 1018 ti,itap-del-sel-mmc-hs = <0xa>; 1019 ti,strobe-sel = <0x77>; 1020 ti,clkbuf-sel = <0x7>; 1021 ti,trm-icp = <0x8>; 1022 mmc-ddr-1_8v; 1023 mmc-hs200-1_8v; 1024 mmc-hs400-1_8v; 1025 dma-coherent; 1026 status = "disabled"; 1027 }; 1028 1029 main_sdhci1: mmc@4fb0000 { 1030 compatible = "ti,j721e-sdhci-4bit"; 1031 reg = <0x00 0x04fb0000 0x00 0x1000>, 1032 <0x00 0x04fb8000 0x00 0x400>; 1033 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 1035 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 1036 clock-names = "clk_ahb", "clk_xin"; 1037 assigned-clocks = <&k3_clks 141 4>; 1038 assigned-clock-parents = <&k3_clks 141 5>; 1039 bus-width = <4>; 1040 ti,otap-del-sel-legacy = <0x0>; 1041 ti,otap-del-sel-sd-hs = <0x0>; 1042 ti,otap-del-sel-sdr12 = <0xf>; 1043 ti,otap-del-sel-sdr25 = <0xf>; 1044 ti,otap-del-sel-sdr50 = <0xc>; 1045 ti,otap-del-sel-sdr104 = <0x5>; 1046 ti,otap-del-sel-ddr50 = <0xc>; 1047 ti,itap-del-sel-legacy = <0x0>; 1048 ti,itap-del-sel-sd-hs = <0x0>; 1049 ti,itap-del-sel-sdr12 = <0x0>; 1050 ti,itap-del-sel-sdr25 = <0x0>; 1051 ti,itap-del-sel-ddr50 = <0x2>; 1052 ti,clkbuf-sel = <0x7>; 1053 ti,trm-icp = <0x8>; 1054 dma-coherent; 1055 status = "disabled"; 1056 }; 1057 1058 pcie0_rc: pcie@2900000 { 1059 compatible = "ti,j784s4-pcie-host"; 1060 reg = <0x00 0x02900000 0x00 0x1000>, 1061 <0x00 0x02907000 0x00 0x400>, 1062 <0x00 0x0d000000 0x00 0x00800000>, 1063 <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1064 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1065 interrupt-names = "link_state"; 1066 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 1067 device_type = "pci"; 1068 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1069 max-link-speed = <3>; 1070 num-lanes = <4>; 1071 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 1072 clocks = <&k3_clks 332 0>; 1073 clock-names = "fck"; 1074 #address-cells = <3>; 1075 #size-cells = <2>; 1076 bus-range = <0x0 0xff>; 1077 vendor-id = <0x104c>; 1078 device-id = <0xb012>; 1079 msi-map = <0x0 &gic_its 0x0 0x10000>; 1080 dma-coherent; 1081 ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1082 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1083 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1084 status = "disabled"; 1085 }; 1086 1087 pcie1_rc: pcie@2910000 { 1088 compatible = "ti,j784s4-pcie-host"; 1089 reg = <0x00 0x02910000 0x00 0x1000>, 1090 <0x00 0x02917000 0x00 0x400>, 1091 <0x00 0x0d800000 0x00 0x00800000>, 1092 <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1093 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1094 interrupt-names = "link_state"; 1095 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1096 device_type = "pci"; 1097 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1098 max-link-speed = <3>; 1099 num-lanes = <4>; 1100 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 1101 clocks = <&k3_clks 333 0>; 1102 clock-names = "fck"; 1103 #address-cells = <3>; 1104 #size-cells = <2>; 1105 bus-range = <0x0 0xff>; 1106 vendor-id = <0x104c>; 1107 device-id = <0xb012>; 1108 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1109 dma-coherent; 1110 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1111 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1112 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1113 status = "disabled"; 1114 }; 1115 1116 serdes_wiz0: wiz@5060000 { 1117 compatible = "ti,j784s4-wiz-10g"; 1118 #address-cells = <1>; 1119 #size-cells = <1>; 1120 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 1121 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 1122 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1123 assigned-clocks = <&k3_clks 404 6>; 1124 assigned-clock-parents = <&k3_clks 404 10>; 1125 num-lanes = <4>; 1126 #reset-cells = <1>; 1127 #clock-cells = <1>; 1128 ranges = <0x5060000 0x00 0x5060000 0x10000>; 1129 status = "disabled"; 1130 1131 serdes0: serdes@5060000 { 1132 compatible = "ti,j721e-serdes-10g"; 1133 reg = <0x05060000 0x010000>; 1134 reg-names = "torrent_phy"; 1135 resets = <&serdes_wiz0 0>; 1136 reset-names = "torrent_reset"; 1137 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1138 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1139 clock-names = "refclk", "phy_en_refclk"; 1140 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1141 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1142 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1143 assigned-clock-parents = <&k3_clks 404 6>, 1144 <&k3_clks 404 6>, 1145 <&k3_clks 404 6>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 #clock-cells = <1>; 1149 status = "disabled"; 1150 }; 1151 }; 1152 1153 serdes_wiz1: wiz@5070000 { 1154 compatible = "ti,j784s4-wiz-10g"; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 1158 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 1159 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1160 assigned-clocks = <&k3_clks 405 6>; 1161 assigned-clock-parents = <&k3_clks 405 10>; 1162 num-lanes = <4>; 1163 #reset-cells = <1>; 1164 #clock-cells = <1>; 1165 ranges = <0x05070000 0x00 0x05070000 0x10000>; 1166 status = "disabled"; 1167 1168 serdes1: serdes@5070000 { 1169 compatible = "ti,j721e-serdes-10g"; 1170 reg = <0x05070000 0x010000>; 1171 reg-names = "torrent_phy"; 1172 resets = <&serdes_wiz1 0>; 1173 reset-names = "torrent_reset"; 1174 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1175 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 1176 clock-names = "refclk", "phy_en_refclk"; 1177 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1178 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 1179 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 1180 assigned-clock-parents = <&k3_clks 405 6>, 1181 <&k3_clks 405 6>, 1182 <&k3_clks 405 6>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 #clock-cells = <1>; 1186 status = "disabled"; 1187 }; 1188 }; 1189 1190 serdes_wiz4: wiz@5050000 { 1191 compatible = "ti,j784s4-wiz-10g"; 1192 #address-cells = <1>; 1193 #size-cells = <1>; 1194 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1195 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1196 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1197 assigned-clocks = <&k3_clks 407 6>; 1198 assigned-clock-parents = <&k3_clks 407 10>; 1199 num-lanes = <4>; 1200 #reset-cells = <1>; 1201 #clock-cells = <1>; 1202 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1203 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1204 status = "disabled"; 1205 1206 serdes4: serdes@5050000 { 1207 /* 1208 * Note: we also map DPTX PHY registers as the Torrent 1209 * needs to manage those. 1210 */ 1211 compatible = "ti,j721e-serdes-10g"; 1212 reg = <0x05050000 0x010000>, 1213 <0x0a030a00 0x40>; /* DPTX PHY */ 1214 reg-names = "torrent_phy"; 1215 resets = <&serdes_wiz4 0>; 1216 reset-names = "torrent_reset"; 1217 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1218 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1219 clock-names = "refclk", "phy_en_refclk"; 1220 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1221 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1222 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1223 assigned-clock-parents = <&k3_clks 407 6>, 1224 <&k3_clks 407 6>, 1225 <&k3_clks 407 6>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 #clock-cells = <1>; 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 main_navss: bus@30000000 { 1234 bootph-all; 1235 compatible = "simple-bus"; 1236 #address-cells = <2>; 1237 #size-cells = <2>; 1238 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1239 ti,sci-dev-id = <280>; 1240 dma-coherent; 1241 dma-ranges; 1242 1243 main_navss_intr: interrupt-controller@310e0000 { 1244 compatible = "ti,sci-intr"; 1245 reg = <0x00 0x310e0000 0x00 0x4000>; 1246 ti,intr-trigger-type = <4>; 1247 interrupt-controller; 1248 interrupt-parent = <&gic500>; 1249 #interrupt-cells = <1>; 1250 ti,sci = <&sms>; 1251 ti,sci-dev-id = <283>; 1252 ti,interrupt-ranges = <0 64 64>, 1253 <64 448 64>, 1254 <128 672 64>; 1255 }; 1256 1257 main_udmass_inta: msi-controller@33d00000 { 1258 compatible = "ti,sci-inta"; 1259 reg = <0x00 0x33d00000 0x00 0x100000>; 1260 interrupt-controller; 1261 #interrupt-cells = <0>; 1262 interrupt-parent = <&main_navss_intr>; 1263 msi-controller; 1264 ti,sci = <&sms>; 1265 ti,sci-dev-id = <321>; 1266 ti,interrupt-ranges = <0 0 256>; 1267 ti,unmapped-event-sources = <&main_bcdma_csi>; 1268 }; 1269 1270 secure_proxy_main: mailbox@32c00000 { 1271 bootph-all; 1272 compatible = "ti,am654-secure-proxy"; 1273 #mbox-cells = <1>; 1274 reg-names = "target_data", "rt", "scfg"; 1275 reg = <0x00 0x32c00000 0x00 0x100000>, 1276 <0x00 0x32400000 0x00 0x100000>, 1277 <0x00 0x32800000 0x00 0x100000>; 1278 interrupt-names = "rx_011"; 1279 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1280 }; 1281 1282 hwspinlock: hwlock@30e00000 { 1283 compatible = "ti,am654-hwspinlock"; 1284 reg = <0x00 0x30e00000 0x00 0x1000>; 1285 #hwlock-cells = <1>; 1286 }; 1287 1288 mailbox0_cluster0: mailbox@31f80000 { 1289 compatible = "ti,am654-mailbox"; 1290 reg = <0x00 0x31f80000 0x00 0x200>; 1291 #mbox-cells = <1>; 1292 ti,mbox-num-users = <4>; 1293 ti,mbox-num-fifos = <16>; 1294 interrupt-parent = <&main_navss_intr>; 1295 status = "disabled"; 1296 }; 1297 1298 mailbox0_cluster1: mailbox@31f81000 { 1299 compatible = "ti,am654-mailbox"; 1300 reg = <0x00 0x31f81000 0x00 0x200>; 1301 #mbox-cells = <1>; 1302 ti,mbox-num-users = <4>; 1303 ti,mbox-num-fifos = <16>; 1304 interrupt-parent = <&main_navss_intr>; 1305 status = "disabled"; 1306 }; 1307 1308 mailbox0_cluster2: mailbox@31f82000 { 1309 compatible = "ti,am654-mailbox"; 1310 reg = <0x00 0x31f82000 0x00 0x200>; 1311 #mbox-cells = <1>; 1312 ti,mbox-num-users = <4>; 1313 ti,mbox-num-fifos = <16>; 1314 interrupt-parent = <&main_navss_intr>; 1315 status = "disabled"; 1316 }; 1317 1318 mailbox0_cluster3: mailbox@31f83000 { 1319 compatible = "ti,am654-mailbox"; 1320 reg = <0x00 0x31f83000 0x00 0x200>; 1321 #mbox-cells = <1>; 1322 ti,mbox-num-users = <4>; 1323 ti,mbox-num-fifos = <16>; 1324 interrupt-parent = <&main_navss_intr>; 1325 status = "disabled"; 1326 }; 1327 1328 mailbox0_cluster4: mailbox@31f84000 { 1329 compatible = "ti,am654-mailbox"; 1330 reg = <0x00 0x31f84000 0x00 0x200>; 1331 #mbox-cells = <1>; 1332 ti,mbox-num-users = <4>; 1333 ti,mbox-num-fifos = <16>; 1334 interrupt-parent = <&main_navss_intr>; 1335 status = "disabled"; 1336 }; 1337 1338 mailbox0_cluster5: mailbox@31f85000 { 1339 compatible = "ti,am654-mailbox"; 1340 reg = <0x00 0x31f85000 0x00 0x200>; 1341 #mbox-cells = <1>; 1342 ti,mbox-num-users = <4>; 1343 ti,mbox-num-fifos = <16>; 1344 interrupt-parent = <&main_navss_intr>; 1345 status = "disabled"; 1346 }; 1347 1348 mailbox0_cluster6: mailbox@31f86000 { 1349 compatible = "ti,am654-mailbox"; 1350 reg = <0x00 0x31f86000 0x00 0x200>; 1351 #mbox-cells = <1>; 1352 ti,mbox-num-users = <4>; 1353 ti,mbox-num-fifos = <16>; 1354 interrupt-parent = <&main_navss_intr>; 1355 status = "disabled"; 1356 }; 1357 1358 mailbox0_cluster7: mailbox@31f87000 { 1359 compatible = "ti,am654-mailbox"; 1360 reg = <0x00 0x31f87000 0x00 0x200>; 1361 #mbox-cells = <1>; 1362 ti,mbox-num-users = <4>; 1363 ti,mbox-num-fifos = <16>; 1364 interrupt-parent = <&main_navss_intr>; 1365 status = "disabled"; 1366 }; 1367 1368 mailbox0_cluster8: mailbox@31f88000 { 1369 compatible = "ti,am654-mailbox"; 1370 reg = <0x00 0x31f88000 0x00 0x200>; 1371 #mbox-cells = <1>; 1372 ti,mbox-num-users = <4>; 1373 ti,mbox-num-fifos = <16>; 1374 interrupt-parent = <&main_navss_intr>; 1375 status = "disabled"; 1376 }; 1377 1378 mailbox0_cluster9: mailbox@31f89000 { 1379 compatible = "ti,am654-mailbox"; 1380 reg = <0x00 0x31f89000 0x00 0x200>; 1381 #mbox-cells = <1>; 1382 ti,mbox-num-users = <4>; 1383 ti,mbox-num-fifos = <16>; 1384 interrupt-parent = <&main_navss_intr>; 1385 status = "disabled"; 1386 }; 1387 1388 mailbox0_cluster10: mailbox@31f8a000 { 1389 compatible = "ti,am654-mailbox"; 1390 reg = <0x00 0x31f8a000 0x00 0x200>; 1391 #mbox-cells = <1>; 1392 ti,mbox-num-users = <4>; 1393 ti,mbox-num-fifos = <16>; 1394 interrupt-parent = <&main_navss_intr>; 1395 status = "disabled"; 1396 }; 1397 1398 mailbox0_cluster11: mailbox@31f8b000 { 1399 compatible = "ti,am654-mailbox"; 1400 reg = <0x00 0x31f8b000 0x00 0x200>; 1401 #mbox-cells = <1>; 1402 ti,mbox-num-users = <4>; 1403 ti,mbox-num-fifos = <16>; 1404 interrupt-parent = <&main_navss_intr>; 1405 status = "disabled"; 1406 }; 1407 1408 mailbox1_cluster0: mailbox@31f90000 { 1409 compatible = "ti,am654-mailbox"; 1410 reg = <0x00 0x31f90000 0x00 0x200>; 1411 #mbox-cells = <1>; 1412 ti,mbox-num-users = <4>; 1413 ti,mbox-num-fifos = <16>; 1414 interrupt-parent = <&main_navss_intr>; 1415 status = "disabled"; 1416 }; 1417 1418 mailbox1_cluster1: mailbox@31f91000 { 1419 compatible = "ti,am654-mailbox"; 1420 reg = <0x00 0x31f91000 0x00 0x200>; 1421 #mbox-cells = <1>; 1422 ti,mbox-num-users = <4>; 1423 ti,mbox-num-fifos = <16>; 1424 interrupt-parent = <&main_navss_intr>; 1425 status = "disabled"; 1426 }; 1427 1428 mailbox1_cluster2: mailbox@31f92000 { 1429 compatible = "ti,am654-mailbox"; 1430 reg = <0x00 0x31f92000 0x00 0x200>; 1431 #mbox-cells = <1>; 1432 ti,mbox-num-users = <4>; 1433 ti,mbox-num-fifos = <16>; 1434 interrupt-parent = <&main_navss_intr>; 1435 status = "disabled"; 1436 }; 1437 1438 mailbox1_cluster3: mailbox@31f93000 { 1439 compatible = "ti,am654-mailbox"; 1440 reg = <0x00 0x31f93000 0x00 0x200>; 1441 #mbox-cells = <1>; 1442 ti,mbox-num-users = <4>; 1443 ti,mbox-num-fifos = <16>; 1444 interrupt-parent = <&main_navss_intr>; 1445 status = "disabled"; 1446 }; 1447 1448 mailbox1_cluster4: mailbox@31f94000 { 1449 compatible = "ti,am654-mailbox"; 1450 reg = <0x00 0x31f94000 0x00 0x200>; 1451 #mbox-cells = <1>; 1452 ti,mbox-num-users = <4>; 1453 ti,mbox-num-fifos = <16>; 1454 interrupt-parent = <&main_navss_intr>; 1455 status = "disabled"; 1456 }; 1457 1458 mailbox1_cluster5: mailbox@31f95000 { 1459 compatible = "ti,am654-mailbox"; 1460 reg = <0x00 0x31f95000 0x00 0x200>; 1461 #mbox-cells = <1>; 1462 ti,mbox-num-users = <4>; 1463 ti,mbox-num-fifos = <16>; 1464 interrupt-parent = <&main_navss_intr>; 1465 status = "disabled"; 1466 }; 1467 1468 mailbox1_cluster6: mailbox@31f96000 { 1469 compatible = "ti,am654-mailbox"; 1470 reg = <0x00 0x31f96000 0x00 0x200>; 1471 #mbox-cells = <1>; 1472 ti,mbox-num-users = <4>; 1473 ti,mbox-num-fifos = <16>; 1474 interrupt-parent = <&main_navss_intr>; 1475 status = "disabled"; 1476 }; 1477 1478 mailbox1_cluster7: mailbox@31f97000 { 1479 compatible = "ti,am654-mailbox"; 1480 reg = <0x00 0x31f97000 0x00 0x200>; 1481 #mbox-cells = <1>; 1482 ti,mbox-num-users = <4>; 1483 ti,mbox-num-fifos = <16>; 1484 interrupt-parent = <&main_navss_intr>; 1485 status = "disabled"; 1486 }; 1487 1488 mailbox1_cluster8: mailbox@31f98000 { 1489 compatible = "ti,am654-mailbox"; 1490 reg = <0x00 0x31f98000 0x00 0x200>; 1491 #mbox-cells = <1>; 1492 ti,mbox-num-users = <4>; 1493 ti,mbox-num-fifos = <16>; 1494 interrupt-parent = <&main_navss_intr>; 1495 status = "disabled"; 1496 }; 1497 1498 mailbox1_cluster9: mailbox@31f99000 { 1499 compatible = "ti,am654-mailbox"; 1500 reg = <0x00 0x31f99000 0x00 0x200>; 1501 #mbox-cells = <1>; 1502 ti,mbox-num-users = <4>; 1503 ti,mbox-num-fifos = <16>; 1504 interrupt-parent = <&main_navss_intr>; 1505 status = "disabled"; 1506 }; 1507 1508 mailbox1_cluster10: mailbox@31f9a000 { 1509 compatible = "ti,am654-mailbox"; 1510 reg = <0x00 0x31f9a000 0x00 0x200>; 1511 #mbox-cells = <1>; 1512 ti,mbox-num-users = <4>; 1513 ti,mbox-num-fifos = <16>; 1514 interrupt-parent = <&main_navss_intr>; 1515 status = "disabled"; 1516 }; 1517 1518 mailbox1_cluster11: mailbox@31f9b000 { 1519 compatible = "ti,am654-mailbox"; 1520 reg = <0x00 0x31f9b000 0x00 0x200>; 1521 #mbox-cells = <1>; 1522 ti,mbox-num-users = <4>; 1523 ti,mbox-num-fifos = <16>; 1524 interrupt-parent = <&main_navss_intr>; 1525 status = "disabled"; 1526 }; 1527 1528 main_ringacc: ringacc@3c000000 { 1529 compatible = "ti,am654-navss-ringacc"; 1530 reg = <0x00 0x3c000000 0x00 0x400000>, 1531 <0x00 0x38000000 0x00 0x400000>, 1532 <0x00 0x31120000 0x00 0x100>, 1533 <0x00 0x33000000 0x00 0x40000>, 1534 <0x00 0x31080000 0x00 0x40000>; 1535 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1536 ti,num-rings = <1024>; 1537 ti,sci-rm-range-gp-rings = <0x1>; 1538 ti,sci = <&sms>; 1539 ti,sci-dev-id = <315>; 1540 msi-parent = <&main_udmass_inta>; 1541 }; 1542 1543 main_udmap: dma-controller@31150000 { 1544 compatible = "ti,j721e-navss-main-udmap"; 1545 reg = <0x00 0x31150000 0x00 0x100>, 1546 <0x00 0x34000000 0x00 0x80000>, 1547 <0x00 0x35000000 0x00 0x200000>, 1548 <0x00 0x30b00000 0x00 0x20000>, 1549 <0x00 0x30c00000 0x00 0x8000>, 1550 <0x00 0x30d00000 0x00 0x4000>; 1551 reg-names = "gcfg", "rchanrt", "tchanrt", 1552 "tchan", "rchan", "rflow"; 1553 msi-parent = <&main_udmass_inta>; 1554 #dma-cells = <1>; 1555 1556 ti,sci = <&sms>; 1557 ti,sci-dev-id = <319>; 1558 ti,ringacc = <&main_ringacc>; 1559 1560 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1561 <0x0f>, /* TX_HCHAN */ 1562 <0x10>; /* TX_UHCHAN */ 1563 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1564 <0x0b>, /* RX_HCHAN */ 1565 <0x0c>; /* RX_UHCHAN */ 1566 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1567 }; 1568 1569 main_bcdma_csi: dma-controller@311a0000 { 1570 compatible = "ti,j721s2-dmss-bcdma-csi"; 1571 reg = <0x00 0x311a0000 0x00 0x100>, 1572 <0x00 0x35d00000 0x00 0x20000>, 1573 <0x00 0x35c00000 0x00 0x10000>, 1574 <0x00 0x35e00000 0x00 0x80000>; 1575 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1576 msi-parent = <&main_udmass_inta>; 1577 #dma-cells = <3>; 1578 ti,sci = <&sms>; 1579 ti,sci-dev-id = <281>; 1580 ti,sci-rm-range-rchan = <0x21>; 1581 ti,sci-rm-range-tchan = <0x22>; 1582 }; 1583 1584 cpts@310d0000 { 1585 compatible = "ti,j721e-cpts"; 1586 reg = <0x00 0x310d0000 0x00 0x400>; 1587 reg-names = "cpts"; 1588 clocks = <&k3_clks 282 0>; 1589 clock-names = "cpts"; 1590 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1591 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1592 interrupts-extended = <&main_navss_intr 391>; 1593 interrupt-names = "cpts"; 1594 ti,cpts-periodic-outputs = <6>; 1595 ti,cpts-ext-ts-inputs = <8>; 1596 }; 1597 }; 1598 1599 main_cpsw0: ethernet@c000000 { 1600 compatible = "ti,j784s4-cpswxg-nuss"; 1601 reg = <0x00 0xc000000 0x00 0x200000>; 1602 reg-names = "cpsw_nuss"; 1603 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 1604 #address-cells = <2>; 1605 #size-cells = <2>; 1606 dma-coherent; 1607 clocks = <&k3_clks 64 0>; 1608 clock-names = "fck"; 1609 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1610 1611 dmas = <&main_udmap 0xca00>, 1612 <&main_udmap 0xca01>, 1613 <&main_udmap 0xca02>, 1614 <&main_udmap 0xca03>, 1615 <&main_udmap 0xca04>, 1616 <&main_udmap 0xca05>, 1617 <&main_udmap 0xca06>, 1618 <&main_udmap 0xca07>, 1619 <&main_udmap 0x4a00>; 1620 dma-names = "tx0", "tx1", "tx2", "tx3", 1621 "tx4", "tx5", "tx6", "tx7", 1622 "rx"; 1623 1624 status = "disabled"; 1625 1626 ethernet-ports { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 main_cpsw0_port1: port@1 { 1631 reg = <1>; 1632 label = "port1"; 1633 ti,mac-only; 1634 status = "disabled"; 1635 }; 1636 1637 main_cpsw0_port2: port@2 { 1638 reg = <2>; 1639 label = "port2"; 1640 ti,mac-only; 1641 status = "disabled"; 1642 }; 1643 1644 main_cpsw0_port3: port@3 { 1645 reg = <3>; 1646 label = "port3"; 1647 ti,mac-only; 1648 status = "disabled"; 1649 }; 1650 1651 main_cpsw0_port4: port@4 { 1652 reg = <4>; 1653 label = "port4"; 1654 ti,mac-only; 1655 status = "disabled"; 1656 }; 1657 1658 main_cpsw0_port5: port@5 { 1659 reg = <5>; 1660 label = "port5"; 1661 ti,mac-only; 1662 status = "disabled"; 1663 }; 1664 1665 main_cpsw0_port6: port@6 { 1666 reg = <6>; 1667 label = "port6"; 1668 ti,mac-only; 1669 status = "disabled"; 1670 }; 1671 1672 main_cpsw0_port7: port@7 { 1673 reg = <7>; 1674 label = "port7"; 1675 ti,mac-only; 1676 status = "disabled"; 1677 }; 1678 1679 main_cpsw0_port8: port@8 { 1680 reg = <8>; 1681 label = "port8"; 1682 ti,mac-only; 1683 status = "disabled"; 1684 }; 1685 }; 1686 1687 main_cpsw0_mdio: mdio@f00 { 1688 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1689 reg = <0x00 0xf00 0x00 0x100>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 clocks = <&k3_clks 64 0>; 1693 clock-names = "fck"; 1694 bus_freq = <1000000>; 1695 status = "disabled"; 1696 }; 1697 1698 cpts@3d000 { 1699 compatible = "ti,am65-cpts"; 1700 reg = <0x00 0x3d000 0x00 0x400>; 1701 clocks = <&k3_clks 64 3>; 1702 clock-names = "cpts"; 1703 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1704 interrupt-names = "cpts"; 1705 ti,cpts-ext-ts-inputs = <4>; 1706 ti,cpts-periodic-outputs = <2>; 1707 }; 1708 }; 1709 1710 main_cpsw1: ethernet@c200000 { 1711 compatible = "ti,j721e-cpsw-nuss"; 1712 reg = <0x00 0xc200000 0x00 0x200000>; 1713 reg-names = "cpsw_nuss"; 1714 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; 1715 #address-cells = <2>; 1716 #size-cells = <2>; 1717 dma-coherent; 1718 clocks = <&k3_clks 62 0>; 1719 clock-names = "fck"; 1720 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1721 1722 dmas = <&main_udmap 0xc640>, 1723 <&main_udmap 0xc641>, 1724 <&main_udmap 0xc642>, 1725 <&main_udmap 0xc643>, 1726 <&main_udmap 0xc644>, 1727 <&main_udmap 0xc645>, 1728 <&main_udmap 0xc646>, 1729 <&main_udmap 0xc647>, 1730 <&main_udmap 0x4640>; 1731 dma-names = "tx0", "tx1", "tx2", "tx3", 1732 "tx4", "tx5", "tx6", "tx7", 1733 "rx"; 1734 1735 status = "disabled"; 1736 1737 ethernet-ports { 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 main_cpsw1_port1: port@1 { 1742 reg = <1>; 1743 label = "port1"; 1744 phys = <&cpsw1_phy_gmii_sel 1>; 1745 ti,mac-only; 1746 status = "disabled"; 1747 }; 1748 }; 1749 1750 main_cpsw1_mdio: mdio@f00 { 1751 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 1752 reg = <0x00 0xf00 0x00 0x100>; 1753 #address-cells = <1>; 1754 #size-cells = <0>; 1755 clocks = <&k3_clks 62 0>; 1756 clock-names = "fck"; 1757 bus_freq = <1000000>; 1758 status = "disabled"; 1759 }; 1760 1761 cpts@3d000 { 1762 compatible = "ti,am65-cpts"; 1763 reg = <0x00 0x3d000 0x00 0x400>; 1764 clocks = <&k3_clks 62 3>; 1765 clock-names = "cpts"; 1766 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1767 interrupt-names = "cpts"; 1768 ti,cpts-ext-ts-inputs = <4>; 1769 ti,cpts-periodic-outputs = <2>; 1770 }; 1771 }; 1772 1773 main_mcan0: can@2701000 { 1774 compatible = "bosch,m_can"; 1775 reg = <0x00 0x02701000 0x00 0x200>, 1776 <0x00 0x02708000 0x00 0x8000>; 1777 reg-names = "m_can", "message_ram"; 1778 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1779 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1780 clock-names = "hclk", "cclk"; 1781 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1783 interrupt-names = "int0", "int1"; 1784 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1785 status = "disabled"; 1786 }; 1787 1788 main_mcan1: can@2711000 { 1789 compatible = "bosch,m_can"; 1790 reg = <0x00 0x02711000 0x00 0x200>, 1791 <0x00 0x02718000 0x00 0x8000>; 1792 reg-names = "m_can", "message_ram"; 1793 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1794 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1795 clock-names = "hclk", "cclk"; 1796 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1798 interrupt-names = "int0", "int1"; 1799 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1800 status = "disabled"; 1801 }; 1802 1803 main_mcan2: can@2721000 { 1804 compatible = "bosch,m_can"; 1805 reg = <0x00 0x02721000 0x00 0x200>, 1806 <0x00 0x02728000 0x00 0x8000>; 1807 reg-names = "m_can", "message_ram"; 1808 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1809 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1810 clock-names = "hclk", "cclk"; 1811 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1813 interrupt-names = "int0", "int1"; 1814 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1815 status = "disabled"; 1816 }; 1817 1818 main_mcan3: can@2731000 { 1819 compatible = "bosch,m_can"; 1820 reg = <0x00 0x02731000 0x00 0x200>, 1821 <0x00 0x02738000 0x00 0x8000>; 1822 reg-names = "m_can", "message_ram"; 1823 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1824 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1825 clock-names = "hclk", "cclk"; 1826 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1828 interrupt-names = "int0", "int1"; 1829 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1830 status = "disabled"; 1831 }; 1832 1833 main_mcan4: can@2741000 { 1834 compatible = "bosch,m_can"; 1835 reg = <0x00 0x02741000 0x00 0x200>, 1836 <0x00 0x02748000 0x00 0x8000>; 1837 reg-names = "m_can", "message_ram"; 1838 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1839 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1840 clock-names = "hclk", "cclk"; 1841 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1843 interrupt-names = "int0", "int1"; 1844 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1845 status = "disabled"; 1846 }; 1847 1848 main_mcan5: can@2751000 { 1849 compatible = "bosch,m_can"; 1850 reg = <0x00 0x02751000 0x00 0x200>, 1851 <0x00 0x02758000 0x00 0x8000>; 1852 reg-names = "m_can", "message_ram"; 1853 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1854 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1855 clock-names = "hclk", "cclk"; 1856 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1858 interrupt-names = "int0", "int1"; 1859 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1860 status = "disabled"; 1861 }; 1862 1863 main_mcan6: can@2761000 { 1864 compatible = "bosch,m_can"; 1865 reg = <0x00 0x02761000 0x00 0x200>, 1866 <0x00 0x02768000 0x00 0x8000>; 1867 reg-names = "m_can", "message_ram"; 1868 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1869 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1870 clock-names = "hclk", "cclk"; 1871 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1873 interrupt-names = "int0", "int1"; 1874 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1875 status = "disabled"; 1876 }; 1877 1878 main_mcan7: can@2771000 { 1879 compatible = "bosch,m_can"; 1880 reg = <0x00 0x02771000 0x00 0x200>, 1881 <0x00 0x02778000 0x00 0x8000>; 1882 reg-names = "m_can", "message_ram"; 1883 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1884 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1885 clock-names = "hclk", "cclk"; 1886 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1888 interrupt-names = "int0", "int1"; 1889 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1890 status = "disabled"; 1891 }; 1892 1893 main_mcan8: can@2781000 { 1894 compatible = "bosch,m_can"; 1895 reg = <0x00 0x02781000 0x00 0x200>, 1896 <0x00 0x02788000 0x00 0x8000>; 1897 reg-names = "m_can", "message_ram"; 1898 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1899 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1900 clock-names = "hclk", "cclk"; 1901 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1903 interrupt-names = "int0", "int1"; 1904 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1905 status = "disabled"; 1906 }; 1907 1908 main_mcan9: can@2791000 { 1909 compatible = "bosch,m_can"; 1910 reg = <0x00 0x02791000 0x00 0x200>, 1911 <0x00 0x02798000 0x00 0x8000>; 1912 reg-names = "m_can", "message_ram"; 1913 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1914 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1915 clock-names = "hclk", "cclk"; 1916 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1918 interrupt-names = "int0", "int1"; 1919 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1920 status = "disabled"; 1921 }; 1922 1923 main_mcan10: can@27a1000 { 1924 compatible = "bosch,m_can"; 1925 reg = <0x00 0x027a1000 0x00 0x200>, 1926 <0x00 0x027a8000 0x00 0x8000>; 1927 reg-names = "m_can", "message_ram"; 1928 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1929 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1930 clock-names = "hclk", "cclk"; 1931 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1933 interrupt-names = "int0", "int1"; 1934 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1935 status = "disabled"; 1936 }; 1937 1938 main_mcan11: can@27b1000 { 1939 compatible = "bosch,m_can"; 1940 reg = <0x00 0x027b1000 0x00 0x200>, 1941 <0x00 0x027b8000 0x00 0x8000>; 1942 reg-names = "m_can", "message_ram"; 1943 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1944 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1945 clock-names = "hclk", "cclk"; 1946 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1948 interrupt-names = "int0", "int1"; 1949 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1950 status = "disabled"; 1951 }; 1952 1953 main_mcan12: can@27c1000 { 1954 compatible = "bosch,m_can"; 1955 reg = <0x00 0x027c1000 0x00 0x200>, 1956 <0x00 0x027c8000 0x00 0x8000>; 1957 reg-names = "m_can", "message_ram"; 1958 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1959 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1960 clock-names = "hclk", "cclk"; 1961 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1963 interrupt-names = "int0", "int1"; 1964 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1965 status = "disabled"; 1966 }; 1967 1968 main_mcan13: can@27d1000 { 1969 compatible = "bosch,m_can"; 1970 reg = <0x00 0x027d1000 0x00 0x200>, 1971 <0x00 0x027d8000 0x00 0x8000>; 1972 reg-names = "m_can", "message_ram"; 1973 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1974 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1975 clock-names = "hclk", "cclk"; 1976 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1978 interrupt-names = "int0", "int1"; 1979 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1980 status = "disabled"; 1981 }; 1982 1983 main_mcan14: can@2681000 { 1984 compatible = "bosch,m_can"; 1985 reg = <0x00 0x02681000 0x00 0x200>, 1986 <0x00 0x02688000 0x00 0x8000>; 1987 reg-names = "m_can", "message_ram"; 1988 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1989 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1990 clock-names = "hclk", "cclk"; 1991 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1993 interrupt-names = "int0", "int1"; 1994 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1995 status = "disabled"; 1996 }; 1997 1998 main_mcan15: can@2691000 { 1999 compatible = "bosch,m_can"; 2000 reg = <0x00 0x02691000 0x00 0x200>, 2001 <0x00 0x02698000 0x00 0x8000>; 2002 reg-names = "m_can", "message_ram"; 2003 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 2004 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 2005 clock-names = "hclk", "cclk"; 2006 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 2008 interrupt-names = "int0", "int1"; 2009 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2010 status = "disabled"; 2011 }; 2012 2013 main_mcan16: can@26a1000 { 2014 compatible = "bosch,m_can"; 2015 reg = <0x00 0x026a1000 0x00 0x200>, 2016 <0x00 0x026a8000 0x00 0x8000>; 2017 reg-names = "m_can", "message_ram"; 2018 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 2019 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 2020 clock-names = "hclk", "cclk"; 2021 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2023 interrupt-names = "int0", "int1"; 2024 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2025 status = "disabled"; 2026 }; 2027 2028 main_mcan17: can@26b1000 { 2029 compatible = "bosch,m_can"; 2030 reg = <0x00 0x026b1000 0x00 0x200>, 2031 <0x00 0x026b8000 0x00 0x8000>; 2032 reg-names = "m_can", "message_ram"; 2033 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 2034 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 2035 clock-names = "hclk", "cclk"; 2036 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "int0", "int1"; 2039 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2040 status = "disabled"; 2041 }; 2042 2043 main_spi0: spi@2100000 { 2044 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2045 reg = <0x00 0x02100000 0x00 0x400>; 2046 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 2050 clocks = <&k3_clks 376 0>; 2051 status = "disabled"; 2052 }; 2053 2054 main_spi1: spi@2110000 { 2055 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2056 reg = <0x00 0x02110000 0x00 0x400>; 2057 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2058 #address-cells = <1>; 2059 #size-cells = <0>; 2060 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 2061 clocks = <&k3_clks 377 0>; 2062 status = "disabled"; 2063 }; 2064 2065 main_spi2: spi@2120000 { 2066 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2067 reg = <0x00 0x02120000 0x00 0x400>; 2068 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2069 #address-cells = <1>; 2070 #size-cells = <0>; 2071 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 2072 clocks = <&k3_clks 378 0>; 2073 status = "disabled"; 2074 }; 2075 2076 main_spi3: spi@2130000 { 2077 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2078 reg = <0x00 0x02130000 0x00 0x400>; 2079 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2080 #address-cells = <1>; 2081 #size-cells = <0>; 2082 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 2083 clocks = <&k3_clks 379 0>; 2084 status = "disabled"; 2085 }; 2086 2087 main_spi4: spi@2140000 { 2088 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2089 reg = <0x00 0x02140000 0x00 0x400>; 2090 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 2094 clocks = <&k3_clks 380 0>; 2095 status = "disabled"; 2096 }; 2097 2098 main_spi5: spi@2150000 { 2099 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2100 reg = <0x00 0x02150000 0x00 0x400>; 2101 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2102 #address-cells = <1>; 2103 #size-cells = <0>; 2104 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 2105 clocks = <&k3_clks 381 0>; 2106 status = "disabled"; 2107 }; 2108 2109 main_spi6: spi@2160000 { 2110 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2111 reg = <0x00 0x02160000 0x00 0x400>; 2112 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 2116 clocks = <&k3_clks 382 0>; 2117 status = "disabled"; 2118 }; 2119 2120 main_spi7: spi@2170000 { 2121 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2122 reg = <0x00 0x02170000 0x00 0x400>; 2123 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2124 #address-cells = <1>; 2125 #size-cells = <0>; 2126 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 2127 clocks = <&k3_clks 383 0>; 2128 status = "disabled"; 2129 }; 2130 2131 ufs_wrapper: ufs-wrapper@4e80000 { 2132 compatible = "ti,j721e-ufs"; 2133 reg = <0x00 0x4e80000 0x00 0x100>; 2134 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 2135 clocks = <&k3_clks 387 3>; 2136 assigned-clocks = <&k3_clks 387 3>; 2137 assigned-clock-parents = <&k3_clks 387 6>; 2138 ranges; 2139 #address-cells = <2>; 2140 #size-cells = <2>; 2141 status = "disabled"; 2142 2143 ufs@4e84000 { 2144 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 2145 reg = <0x00 0x4e84000 0x00 0x10000>; 2146 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2147 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 2148 <19200000 19200000>; 2149 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 2150 clock-names = "core_clk", "phy_clk", "ref_clk"; 2151 dma-coherent; 2152 }; 2153 }; 2154 2155 main_r5fss0: r5fss@5c00000 { 2156 compatible = "ti,j721s2-r5fss"; 2157 ti,cluster-mode = <1>; 2158 #address-cells = <1>; 2159 #size-cells = <1>; 2160 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2161 <0x5d00000 0x00 0x5d00000 0x20000>; 2162 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 2163 2164 main_r5fss0_core0: r5f@5c00000 { 2165 compatible = "ti,j721s2-r5f"; 2166 reg = <0x5c00000 0x00010000>, 2167 <0x5c10000 0x00010000>; 2168 reg-names = "atcm", "btcm"; 2169 ti,sci = <&sms>; 2170 ti,sci-dev-id = <339>; 2171 ti,sci-proc-ids = <0x06 0xff>; 2172 resets = <&k3_reset 339 1>; 2173 firmware-name = "j784s4-main-r5f0_0-fw"; 2174 ti,atcm-enable = <1>; 2175 ti,btcm-enable = <1>; 2176 ti,loczrama = <1>; 2177 }; 2178 2179 main_r5fss0_core1: r5f@5d00000 { 2180 compatible = "ti,j721s2-r5f"; 2181 reg = <0x5d00000 0x00010000>, 2182 <0x5d10000 0x00010000>; 2183 reg-names = "atcm", "btcm"; 2184 ti,sci = <&sms>; 2185 ti,sci-dev-id = <340>; 2186 ti,sci-proc-ids = <0x07 0xff>; 2187 resets = <&k3_reset 340 1>; 2188 firmware-name = "j784s4-main-r5f0_1-fw"; 2189 ti,atcm-enable = <1>; 2190 ti,btcm-enable = <1>; 2191 ti,loczrama = <1>; 2192 }; 2193 }; 2194 2195 main_r5fss1: r5fss@5e00000 { 2196 compatible = "ti,j721s2-r5fss"; 2197 ti,cluster-mode = <1>; 2198 #address-cells = <1>; 2199 #size-cells = <1>; 2200 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2201 <0x5f00000 0x00 0x5f00000 0x20000>; 2202 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 2203 2204 main_r5fss1_core0: r5f@5e00000 { 2205 compatible = "ti,j721s2-r5f"; 2206 reg = <0x5e00000 0x00010000>, 2207 <0x5e10000 0x00010000>; 2208 reg-names = "atcm", "btcm"; 2209 ti,sci = <&sms>; 2210 ti,sci-dev-id = <341>; 2211 ti,sci-proc-ids = <0x08 0xff>; 2212 resets = <&k3_reset 341 1>; 2213 firmware-name = "j784s4-main-r5f1_0-fw"; 2214 ti,atcm-enable = <1>; 2215 ti,btcm-enable = <1>; 2216 ti,loczrama = <1>; 2217 }; 2218 2219 main_r5fss1_core1: r5f@5f00000 { 2220 compatible = "ti,j721s2-r5f"; 2221 reg = <0x5f00000 0x00010000>, 2222 <0x5f10000 0x00010000>; 2223 reg-names = "atcm", "btcm"; 2224 ti,sci = <&sms>; 2225 ti,sci-dev-id = <342>; 2226 ti,sci-proc-ids = <0x09 0xff>; 2227 resets = <&k3_reset 342 1>; 2228 firmware-name = "j784s4-main-r5f1_1-fw"; 2229 ti,atcm-enable = <1>; 2230 ti,btcm-enable = <1>; 2231 ti,loczrama = <1>; 2232 }; 2233 }; 2234 2235 main_r5fss2: r5fss@5900000 { 2236 compatible = "ti,j721s2-r5fss"; 2237 ti,cluster-mode = <1>; 2238 #address-cells = <1>; 2239 #size-cells = <1>; 2240 ranges = <0x5900000 0x00 0x5900000 0x20000>, 2241 <0x5a00000 0x00 0x5a00000 0x20000>; 2242 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 2243 2244 main_r5fss2_core0: r5f@5900000 { 2245 compatible = "ti,j721s2-r5f"; 2246 reg = <0x5900000 0x00010000>, 2247 <0x5910000 0x00010000>; 2248 reg-names = "atcm", "btcm"; 2249 ti,sci = <&sms>; 2250 ti,sci-dev-id = <343>; 2251 ti,sci-proc-ids = <0x0a 0xff>; 2252 resets = <&k3_reset 343 1>; 2253 firmware-name = "j784s4-main-r5f2_0-fw"; 2254 ti,atcm-enable = <1>; 2255 ti,btcm-enable = <1>; 2256 ti,loczrama = <1>; 2257 }; 2258 2259 main_r5fss2_core1: r5f@5a00000 { 2260 compatible = "ti,j721s2-r5f"; 2261 reg = <0x5a00000 0x00010000>, 2262 <0x5a10000 0x00010000>; 2263 reg-names = "atcm", "btcm"; 2264 ti,sci = <&sms>; 2265 ti,sci-dev-id = <344>; 2266 ti,sci-proc-ids = <0x0b 0xff>; 2267 resets = <&k3_reset 344 1>; 2268 firmware-name = "j784s4-main-r5f2_1-fw"; 2269 ti,atcm-enable = <1>; 2270 ti,btcm-enable = <1>; 2271 ti,loczrama = <1>; 2272 }; 2273 }; 2274 2275 c71_0: dsp@64800000 { 2276 compatible = "ti,j721s2-c71-dsp"; 2277 reg = <0x00 0x64800000 0x00 0x00080000>, 2278 <0x00 0x64e00000 0x00 0x0000c000>; 2279 reg-names = "l2sram", "l1dram"; 2280 ti,sci = <&sms>; 2281 ti,sci-dev-id = <30>; 2282 ti,sci-proc-ids = <0x30 0xff>; 2283 resets = <&k3_reset 30 1>; 2284 firmware-name = "j784s4-c71_0-fw"; 2285 status = "disabled"; 2286 }; 2287 2288 c71_1: dsp@65800000 { 2289 compatible = "ti,j721s2-c71-dsp"; 2290 reg = <0x00 0x65800000 0x00 0x00080000>, 2291 <0x00 0x65e00000 0x00 0x0000c000>; 2292 reg-names = "l2sram", "l1dram"; 2293 ti,sci = <&sms>; 2294 ti,sci-dev-id = <33>; 2295 ti,sci-proc-ids = <0x31 0xff>; 2296 resets = <&k3_reset 33 1>; 2297 firmware-name = "j784s4-c71_1-fw"; 2298 status = "disabled"; 2299 }; 2300 2301 c71_2: dsp@66800000 { 2302 compatible = "ti,j721s2-c71-dsp"; 2303 reg = <0x00 0x66800000 0x00 0x00080000>, 2304 <0x00 0x66e00000 0x00 0x0000c000>; 2305 reg-names = "l2sram", "l1dram"; 2306 ti,sci = <&sms>; 2307 ti,sci-dev-id = <37>; 2308 ti,sci-proc-ids = <0x32 0xff>; 2309 resets = <&k3_reset 37 1>; 2310 firmware-name = "j784s4-c71_2-fw"; 2311 status = "disabled"; 2312 }; 2313 2314 main_esm: esm@700000 { 2315 compatible = "ti,j721e-esm"; 2316 reg = <0x00 0x700000 0x00 0x1000>; 2317 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2318 <695>; 2319 bootph-pre-ram; 2320 }; 2321 2322 watchdog0: watchdog@2200000 { 2323 compatible = "ti,j7-rti-wdt"; 2324 reg = <0x00 0x2200000 0x00 0x100>; 2325 clocks = <&k3_clks 348 0>; 2326 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2327 assigned-clocks = <&k3_clks 348 0>; 2328 assigned-clock-parents = <&k3_clks 348 4>; 2329 }; 2330 2331 watchdog1: watchdog@2210000 { 2332 compatible = "ti,j7-rti-wdt"; 2333 reg = <0x00 0x2210000 0x00 0x100>; 2334 clocks = <&k3_clks 349 0>; 2335 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2336 assigned-clocks = <&k3_clks 349 0>; 2337 assigned-clock-parents = <&k3_clks 349 4>; 2338 }; 2339 2340 watchdog2: watchdog@2220000 { 2341 compatible = "ti,j7-rti-wdt"; 2342 reg = <0x00 0x2220000 0x00 0x100>; 2343 clocks = <&k3_clks 350 0>; 2344 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2345 assigned-clocks = <&k3_clks 350 0>; 2346 assigned-clock-parents = <&k3_clks 350 4>; 2347 }; 2348 2349 watchdog3: watchdog@2230000 { 2350 compatible = "ti,j7-rti-wdt"; 2351 reg = <0x00 0x2230000 0x00 0x100>; 2352 clocks = <&k3_clks 351 0>; 2353 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2354 assigned-clocks = <&k3_clks 351 0>; 2355 assigned-clock-parents = <&k3_clks 351 4>; 2356 }; 2357 2358 watchdog4: watchdog@2240000 { 2359 compatible = "ti,j7-rti-wdt"; 2360 reg = <0x00 0x2240000 0x00 0x100>; 2361 clocks = <&k3_clks 352 0>; 2362 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2363 assigned-clocks = <&k3_clks 352 0>; 2364 assigned-clock-parents = <&k3_clks 352 4>; 2365 }; 2366 2367 watchdog5: watchdog@2250000 { 2368 compatible = "ti,j7-rti-wdt"; 2369 reg = <0x00 0x2250000 0x00 0x100>; 2370 clocks = <&k3_clks 353 0>; 2371 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2372 assigned-clocks = <&k3_clks 353 0>; 2373 assigned-clock-parents = <&k3_clks 353 4>; 2374 }; 2375 2376 watchdog6: watchdog@2260000 { 2377 compatible = "ti,j7-rti-wdt"; 2378 reg = <0x00 0x2260000 0x00 0x100>; 2379 clocks = <&k3_clks 354 0>; 2380 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2381 assigned-clocks = <&k3_clks 354 0>; 2382 assigned-clock-parents = <&k3_clks 354 4>; 2383 }; 2384 2385 watchdog7: watchdog@2270000 { 2386 compatible = "ti,j7-rti-wdt"; 2387 reg = <0x00 0x2270000 0x00 0x100>; 2388 clocks = <&k3_clks 355 0>; 2389 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2390 assigned-clocks = <&k3_clks 355 0>; 2391 assigned-clock-parents = <&k3_clks 355 4>; 2392 }; 2393 2394 /* 2395 * The following RTI instances are coupled with MCU R5Fs, c7x and 2396 * GPU so keeping them reserved as these will be used by their 2397 * respective firmware 2398 */ 2399 watchdog8: watchdog@22f0000 { 2400 compatible = "ti,j7-rti-wdt"; 2401 reg = <0x00 0x22f0000 0x00 0x100>; 2402 clocks = <&k3_clks 360 0>; 2403 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2404 assigned-clocks = <&k3_clks 360 0>; 2405 assigned-clock-parents = <&k3_clks 360 4>; 2406 /* reserved for GPU */ 2407 status = "reserved"; 2408 }; 2409 2410 watchdog9: watchdog@2300000 { 2411 compatible = "ti,j7-rti-wdt"; 2412 reg = <0x00 0x2300000 0x00 0x100>; 2413 clocks = <&k3_clks 356 0>; 2414 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2415 assigned-clocks = <&k3_clks 356 0>; 2416 assigned-clock-parents = <&k3_clks 356 4>; 2417 /* reserved for C7X_0 DSP */ 2418 status = "reserved"; 2419 }; 2420 2421 watchdog10: watchdog@2310000 { 2422 compatible = "ti,j7-rti-wdt"; 2423 reg = <0x00 0x2310000 0x00 0x100>; 2424 clocks = <&k3_clks 357 0>; 2425 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2426 assigned-clocks = <&k3_clks 357 0>; 2427 assigned-clock-parents = <&k3_clks 357 4>; 2428 /* reserved for C7X_1 DSP */ 2429 status = "reserved"; 2430 }; 2431 2432 watchdog11: watchdog@2320000 { 2433 compatible = "ti,j7-rti-wdt"; 2434 reg = <0x00 0x2320000 0x00 0x100>; 2435 clocks = <&k3_clks 358 0>; 2436 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2437 assigned-clocks = <&k3_clks 358 0>; 2438 assigned-clock-parents = <&k3_clks 358 4>; 2439 /* reserved for C7X_2 DSP */ 2440 status = "reserved"; 2441 }; 2442 2443 watchdog12: watchdog@2330000 { 2444 compatible = "ti,j7-rti-wdt"; 2445 reg = <0x00 0x2330000 0x00 0x100>; 2446 clocks = <&k3_clks 359 0>; 2447 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2448 assigned-clocks = <&k3_clks 359 0>; 2449 assigned-clock-parents = <&k3_clks 359 4>; 2450 /* reserved for C7X_3 DSP */ 2451 status = "reserved"; 2452 }; 2453 2454 watchdog13: watchdog@23c0000 { 2455 compatible = "ti,j7-rti-wdt"; 2456 reg = <0x00 0x23c0000 0x00 0x100>; 2457 clocks = <&k3_clks 361 0>; 2458 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2459 assigned-clocks = <&k3_clks 361 0>; 2460 assigned-clock-parents = <&k3_clks 361 4>; 2461 /* reserved for MAIN_R5F0_0 */ 2462 status = "reserved"; 2463 }; 2464 2465 watchdog14: watchdog@23d0000 { 2466 compatible = "ti,j7-rti-wdt"; 2467 reg = <0x00 0x23d0000 0x00 0x100>; 2468 clocks = <&k3_clks 362 0>; 2469 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2470 assigned-clocks = <&k3_clks 362 0>; 2471 assigned-clock-parents = <&k3_clks 362 4>; 2472 /* reserved for MAIN_R5F0_1 */ 2473 status = "reserved"; 2474 }; 2475 2476 watchdog15: watchdog@23e0000 { 2477 compatible = "ti,j7-rti-wdt"; 2478 reg = <0x00 0x23e0000 0x00 0x100>; 2479 clocks = <&k3_clks 363 0>; 2480 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2481 assigned-clocks = <&k3_clks 363 0>; 2482 assigned-clock-parents = <&k3_clks 363 4>; 2483 /* reserved for MAIN_R5F1_0 */ 2484 status = "reserved"; 2485 }; 2486 2487 watchdog16: watchdog@23f0000 { 2488 compatible = "ti,j7-rti-wdt"; 2489 reg = <0x00 0x23f0000 0x00 0x100>; 2490 clocks = <&k3_clks 364 0>; 2491 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2492 assigned-clocks = <&k3_clks 364 0>; 2493 assigned-clock-parents = <&k3_clks 364 4>; 2494 /* reserved for MAIN_R5F1_1 */ 2495 status = "reserved"; 2496 }; 2497 2498 watchdog17: watchdog@2540000 { 2499 compatible = "ti,j7-rti-wdt"; 2500 reg = <0x00 0x2540000 0x00 0x100>; 2501 clocks = <&k3_clks 365 0>; 2502 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2503 assigned-clocks = <&k3_clks 365 0>; 2504 assigned-clock-parents = <&k3_clks 366 4>; 2505 /* reserved for MAIN_R5F2_0 */ 2506 status = "reserved"; 2507 }; 2508 2509 watchdog18: watchdog@2550000 { 2510 compatible = "ti,j7-rti-wdt"; 2511 reg = <0x00 0x2550000 0x00 0x100>; 2512 clocks = <&k3_clks 366 0>; 2513 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2514 assigned-clocks = <&k3_clks 366 0>; 2515 assigned-clock-parents = <&k3_clks 366 4>; 2516 /* reserved for MAIN_R5F2_1 */ 2517 status = "reserved"; 2518 }; 2519 2520 mhdp: bridge@a000000 { 2521 compatible = "ti,j721e-mhdp8546"; 2522 reg = <0x0 0xa000000 0x0 0x30a00>, 2523 <0x0 0x4f40000 0x0 0x20>; 2524 reg-names = "mhdptx", "j721e-intg"; 2525 clocks = <&k3_clks 217 11>; 2526 interrupt-parent = <&gic500>; 2527 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2528 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2529 status = "disabled"; 2530 2531 dp0_ports: ports { 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 /* Remote-endpoints are on the boards so 2535 * ports are defined in the platform dt file. 2536 */ 2537 }; 2538 }; 2539 2540 dss: dss@4a00000 { 2541 compatible = "ti,j721e-dss"; 2542 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2543 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2544 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2545 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2546 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2547 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2548 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2549 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2550 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2551 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2552 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2553 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2554 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2555 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2556 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2557 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2558 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2559 reg-names = "common_m", "common_s0", 2560 "common_s1", "common_s2", 2561 "vidl1", "vidl2","vid1","vid2", 2562 "ovr1", "ovr2", "ovr3", "ovr4", 2563 "vp1", "vp2", "vp3", "vp4", 2564 "wb"; 2565 clocks = <&k3_clks 218 0>, 2566 <&k3_clks 218 2>, 2567 <&k3_clks 218 5>, 2568 <&k3_clks 218 14>, 2569 <&k3_clks 218 18>; 2570 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2571 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2572 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2573 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2575 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2576 interrupt-names = "common_m", 2577 "common_s0", 2578 "common_s1", 2579 "common_s2"; 2580 status = "disabled"; 2581 2582 dss_ports: ports { 2583 /* Ports that DSS drives are platform specific 2584 * so they are defined in platform dt file. 2585 */ 2586 }; 2587 }; 2588 2589 mcasp0: mcasp@2b00000 { 2590 compatible = "ti,am33xx-mcasp-audio"; 2591 reg = <0x00 0x02b00000 0x00 0x2000>, 2592 <0x00 0x02b08000 0x00 0x1000>; 2593 reg-names = "mpu","dat"; 2594 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 2596 interrupt-names = "tx", "rx"; 2597 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 2598 dma-names = "tx", "rx"; 2599 clocks = <&k3_clks 265 0>; 2600 clock-names = "fck"; 2601 assigned-clocks = <&k3_clks 265 0>; 2602 assigned-clock-parents = <&k3_clks 265 1>; 2603 power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; 2604 status = "disabled"; 2605 }; 2606 2607 mcasp1: mcasp@2b10000 { 2608 compatible = "ti,am33xx-mcasp-audio"; 2609 reg = <0x00 0x02b10000 0x00 0x2000>, 2610 <0x00 0x02b18000 0x00 0x1000>; 2611 reg-names = "mpu","dat"; 2612 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2614 interrupt-names = "tx", "rx"; 2615 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2616 dma-names = "tx", "rx"; 2617 clocks = <&k3_clks 266 0>; 2618 clock-names = "fck"; 2619 assigned-clocks = <&k3_clks 266 0>; 2620 assigned-clock-parents = <&k3_clks 266 1>; 2621 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2622 status = "disabled"; 2623 }; 2624 2625 mcasp2: mcasp@2b20000 { 2626 compatible = "ti,am33xx-mcasp-audio"; 2627 reg = <0x00 0x02b20000 0x00 0x2000>, 2628 <0x00 0x02b28000 0x00 0x1000>; 2629 reg-names = "mpu","dat"; 2630 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2632 interrupt-names = "tx", "rx"; 2633 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2634 dma-names = "tx", "rx"; 2635 clocks = <&k3_clks 267 0>; 2636 clock-names = "fck"; 2637 assigned-clocks = <&k3_clks 267 0>; 2638 assigned-clock-parents = <&k3_clks 267 1>; 2639 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2640 status = "disabled"; 2641 }; 2642 2643 mcasp3: mcasp@2b30000 { 2644 compatible = "ti,am33xx-mcasp-audio"; 2645 reg = <0x00 0x02b30000 0x00 0x2000>, 2646 <0x00 0x02b38000 0x00 0x1000>; 2647 reg-names = "mpu","dat"; 2648 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2649 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2650 interrupt-names = "tx", "rx"; 2651 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; 2652 dma-names = "tx", "rx"; 2653 clocks = <&k3_clks 268 0>; 2654 clock-names = "fck"; 2655 assigned-clocks = <&k3_clks 268 0>; 2656 assigned-clock-parents = <&k3_clks 268 1>; 2657 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2658 status = "disabled"; 2659 }; 2660 2661 mcasp4: mcasp@2b40000 { 2662 compatible = "ti,am33xx-mcasp-audio"; 2663 reg = <0x00 0x02b40000 0x00 0x2000>, 2664 <0x00 0x02b48000 0x00 0x1000>; 2665 reg-names = "mpu","dat"; 2666 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2668 interrupt-names = "tx", "rx"; 2669 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; 2670 dma-names = "tx", "rx"; 2671 clocks = <&k3_clks 269 0>; 2672 clock-names = "fck"; 2673 assigned-clocks = <&k3_clks 269 0>; 2674 assigned-clock-parents = <&k3_clks 269 1>; 2675 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2676 status = "disabled"; 2677 }; 2678}; 2679