1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J722S SoC Family 4 * 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13#include "k3-pinctrl.h" 14 15/ { 16 model = "Texas Instruments K3 J722S SoC"; 17 compatible = "ti,j722s"; 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0: cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 }; 45 46 cpu0: cpu@0 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x000>; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 i-cache-size = <0x8000>; 52 i-cache-line-size = <64>; 53 i-cache-sets = <256>; 54 d-cache-size = <0x8000>; 55 d-cache-line-size = <64>; 56 d-cache-sets = <128>; 57 next-level-cache = <&l2_0>; 58 clocks = <&k3_clks 135 0>; 59 }; 60 61 cpu1: cpu@1 { 62 compatible = "arm,cortex-a53"; 63 reg = <0x001>; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 i-cache-size = <0x8000>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <256>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_0>; 73 clocks = <&k3_clks 136 0>; 74 }; 75 76 cpu2: cpu@2 { 77 compatible = "arm,cortex-a53"; 78 reg = <0x002>; 79 device_type = "cpu"; 80 enable-method = "psci"; 81 i-cache-size = <0x8000>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <256>; 84 d-cache-size = <0x8000>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 clocks = <&k3_clks 137 0>; 89 }; 90 91 cpu3: cpu@3 { 92 compatible = "arm,cortex-a53"; 93 reg = <0x003>; 94 device_type = "cpu"; 95 enable-method = "psci"; 96 i-cache-size = <0x8000>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <256>; 99 d-cache-size = <0x8000>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <128>; 102 next-level-cache = <&l2_0>; 103 clocks = <&k3_clks 138 0>; 104 }; 105 }; 106 107 l2_0: l2-cache0 { 108 compatible = "cache"; 109 cache-unified; 110 cache-level = <2>; 111 cache-size = <0x80000>; 112 cache-line-size = <64>; 113 cache-sets = <512>; 114 }; 115 116 firmware { 117 optee { 118 compatible = "linaro,optee-tz"; 119 method = "smc"; 120 }; 121 122 psci: psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 }; 127 128 a53_timer0: timer-cl0-cpu0 { 129 compatible = "arm,armv8-timer"; 130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 131 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 132 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 133 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 134 }; 135 136 pmu: pmu { 137 compatible = "arm,cortex-a53-pmu"; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 }; 140 141 cbass_main: bus@f0000 { 142 compatible = "simple-bus"; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 146 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 147 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 148 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 149 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 150 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 151 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 152 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 153 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 154 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ 155 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 156 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ 157 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ 158 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ 159 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 160 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 161 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ 162 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ 163 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 164 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ 165 <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ 166 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ 167 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ 168 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 169 <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ 170 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 171 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 172 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 173 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 174 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ 175 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 176 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ 177 <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ 178 <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ 179 <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ 180 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ 181 <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ 182 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 183 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 184 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ 185 186 /* MCU Domain Range */ 187 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 188 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, 189 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, 190 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, 191 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, 192 193 /* Wakeup Domain Range */ 194 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, 195 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 196 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, 197 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, 198 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; 199 200 cbass_mcu: bus@4000000 { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ 205 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ 206 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ 207 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ 208 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ 209 bootph-all; 210 }; 211 212 cbass_wakeup: bus@b00000 { 213 compatible = "simple-bus"; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 217 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 218 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ 219 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ 220 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ 221 bootph-all; 222 }; 223 }; 224 225 #include "k3-am62p-j722s-common-thermal.dtsi" 226}; 227 228/* Include peripherals shared with AM62P */ 229#include "k3-am62p-j722s-common-main.dtsi" 230#include "k3-am62p-j722s-common-mcu.dtsi" 231#include "k3-am62p-j722s-common-wakeup.dtsi" 232 233/* Include J722S specific peripherals */ 234#include "k3-j722s-main.dtsi" 235