1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 msmc_ram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x0 0x70000000 0x0 0x400000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 26 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 29 }; 30 31 tifs-sram@1f0000 { 32 reg = <0x1f0000 0x10000>; 33 }; 34 35 l3cache-sram@200000 { 36 reg = <0x200000 0x200000>; 37 }; 38 }; 39 40 scm_conf: syscon@104000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x00 0x00104000 0x00 0x18000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; 46 47 usb_serdes_mux: mux-controller@0 { 48 compatible = "reg-mux"; 49 reg = <0x0 0x4>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 }; 53 54 phy_gmii_sel_cpsw: phy@34 { 55 compatible = "ti,am654-phy-gmii-sel"; 56 reg = <0x34 0x4>; 57 #phy-cells = <1>; 58 }; 59 60 pcie1_ctrl: pcie-ctrl@74 { 61 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 62 reg = <0x74 0x4>; 63 }; 64 65 serdes_ln_ctrl: mux-controller@80 { 66 compatible = "reg-mux"; 67 reg = <0x80 0x10>; 68 #mux-control-cells = <1>; 69 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 70 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ 71 }; 72 73 ehrpwm_tbclk: clock-controller@140 { 74 compatible = "ti,am654-ehrpwm-tbclk"; 75 reg = <0x140 0x18>; 76 #clock-cells = <1>; 77 }; 78 }; 79 80 main_ehrpwm0: pwm@3000000 { 81 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 82 #pwm-cells = <3>; 83 reg = <0x00 0x3000000 0x00 0x100>; 84 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 85 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; 86 clock-names = "tbclk", "fck"; 87 status = "disabled"; 88 }; 89 90 main_ehrpwm1: pwm@3010000 { 91 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 92 #pwm-cells = <3>; 93 reg = <0x00 0x3010000 0x00 0x100>; 94 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; 96 clock-names = "tbclk", "fck"; 97 status = "disabled"; 98 }; 99 100 main_ehrpwm2: pwm@3020000 { 101 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 102 #pwm-cells = <3>; 103 reg = <0x00 0x3020000 0x00 0x100>; 104 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 105 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; 106 clock-names = "tbclk", "fck"; 107 status = "disabled"; 108 }; 109 110 main_ehrpwm3: pwm@3030000 { 111 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 112 #pwm-cells = <3>; 113 reg = <0x00 0x3030000 0x00 0x100>; 114 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 115 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; 116 clock-names = "tbclk", "fck"; 117 status = "disabled"; 118 }; 119 120 main_ehrpwm4: pwm@3040000 { 121 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 122 #pwm-cells = <3>; 123 reg = <0x00 0x3040000 0x00 0x100>; 124 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 125 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; 126 clock-names = "tbclk", "fck"; 127 status = "disabled"; 128 }; 129 130 main_ehrpwm5: pwm@3050000 { 131 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 132 #pwm-cells = <3>; 133 reg = <0x00 0x3050000 0x00 0x100>; 134 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 135 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; 136 clock-names = "tbclk", "fck"; 137 status = "disabled"; 138 }; 139 140 gic500: interrupt-controller@1800000 { 141 compatible = "arm,gic-v3"; 142 #address-cells = <2>; 143 #size-cells = <2>; 144 ranges; 145 #interrupt-cells = <3>; 146 interrupt-controller; 147 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 148 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 149 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 150 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 151 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 152 153 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 154 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 155 156 gic_its: msi-controller@1820000 { 157 compatible = "arm,gic-v3-its"; 158 reg = <0x00 0x01820000 0x00 0x10000>; 159 socionext,synquacer-pre-its = <0x1000000 0x400000>; 160 msi-controller; 161 #msi-cells = <1>; 162 }; 163 }; 164 165 main_gpio_intr: interrupt-controller@a00000 { 166 compatible = "ti,sci-intr"; 167 reg = <0x00 0x00a00000 0x00 0x800>; 168 ti,intr-trigger-type = <1>; 169 interrupt-controller; 170 interrupt-parent = <&gic500>; 171 #interrupt-cells = <1>; 172 ti,sci = <&sms>; 173 ti,sci-dev-id = <148>; 174 ti,interrupt-ranges = <8 392 56>; 175 }; 176 177 main_pmx0: pinctrl@11c000 { 178 compatible = "pinctrl-single"; 179 /* Proxy 0 addressing */ 180 reg = <0x0 0x11c000 0x0 0x120>; 181 #pinctrl-cells = <1>; 182 pinctrl-single,register-width = <32>; 183 pinctrl-single,function-mask = <0xffffffff>; 184 }; 185 186 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 187 main_timerio_input: pinctrl@104200 { 188 compatible = "pinctrl-single"; 189 reg = <0x00 0x104200 0x00 0x50>; 190 #pinctrl-cells = <1>; 191 pinctrl-single,register-width = <32>; 192 pinctrl-single,function-mask = <0x00000007>; 193 }; 194 195 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 196 main_timerio_output: pinctrl@104280 { 197 compatible = "pinctrl-single"; 198 reg = <0x00 0x104280 0x00 0x20>; 199 #pinctrl-cells = <1>; 200 pinctrl-single,register-width = <32>; 201 pinctrl-single,function-mask = <0x0000001f>; 202 }; 203 204 main_crypto: crypto@4e00000 { 205 compatible = "ti,j721e-sa2ul"; 206 reg = <0x00 0x04e00000 0x00 0x1200>; 207 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 208 #address-cells = <2>; 209 #size-cells = <2>; 210 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 211 212 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 213 <&main_udmap 0x4a41>; 214 dma-names = "tx", "rx1", "rx2"; 215 216 rng: rng@4e10000 { 217 compatible = "inside-secure,safexcel-eip76"; 218 reg = <0x00 0x04e10000 0x00 0x7d>; 219 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 220 }; 221 }; 222 223 main_timer0: timer@2400000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2400000 0x00 0x400>; 226 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 63 1>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 63 1>; 230 assigned-clock-parents = <&k3_clks 63 2>; 231 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer1: timer@2410000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2410000 0x00 0x400>; 238 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 64 1>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 64 1>; 242 assigned-clock-parents = <&k3_clks 64 2>; 243 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer2: timer@2420000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2420000 0x00 0x400>; 250 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 65 1>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 65 1>; 254 assigned-clock-parents = <&k3_clks 65 2>; 255 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer3: timer@2430000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2430000 0x00 0x400>; 262 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 66 1>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 66 1>; 266 assigned-clock-parents = <&k3_clks 66 2>; 267 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer4: timer@2440000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2440000 0x00 0x400>; 274 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 67 1>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 67 1>; 278 assigned-clock-parents = <&k3_clks 67 2>; 279 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer5: timer@2450000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x2450000 0x00 0x400>; 286 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 68 1>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 68 1>; 290 assigned-clock-parents = <&k3_clks 68 2>; 291 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer6: timer@2460000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x2460000 0x00 0x400>; 298 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 69 1>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 69 1>; 302 assigned-clock-parents = <&k3_clks 69 2>; 303 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer7: timer@2470000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x2470000 0x00 0x400>; 310 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 70 1>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 70 1>; 314 assigned-clock-parents = <&k3_clks 70 2>; 315 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer8: timer@2480000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x2480000 0x00 0x400>; 322 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 71 1>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 71 1>; 326 assigned-clock-parents = <&k3_clks 71 2>; 327 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer9: timer@2490000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x2490000 0x00 0x400>; 334 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 72 1>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 72 1>; 338 assigned-clock-parents = <&k3_clks 72 2>; 339 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer10: timer@24a0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24a0000 0x00 0x400>; 346 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 73 1>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 73 1>; 350 assigned-clock-parents = <&k3_clks 73 2>; 351 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer11: timer@24b0000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x24b0000 0x00 0x400>; 358 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 74 1>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 74 1>; 362 assigned-clock-parents = <&k3_clks 74 2>; 363 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer12: timer@24c0000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x24c0000 0x00 0x400>; 370 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 75 1>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 75 1>; 374 assigned-clock-parents = <&k3_clks 75 2>; 375 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer13: timer@24d0000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x24d0000 0x00 0x400>; 382 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 76 1>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 76 1>; 386 assigned-clock-parents = <&k3_clks 76 2>; 387 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_timer14: timer@24e0000 { 392 compatible = "ti,am654-timer"; 393 reg = <0x00 0x24e0000 0x00 0x400>; 394 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&k3_clks 77 1>; 396 clock-names = "fck"; 397 assigned-clocks = <&k3_clks 77 1>; 398 assigned-clock-parents = <&k3_clks 77 2>; 399 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 400 ti,timer-pwm; 401 }; 402 403 main_timer15: timer@24f0000 { 404 compatible = "ti,am654-timer"; 405 reg = <0x00 0x24f0000 0x00 0x400>; 406 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&k3_clks 78 1>; 408 clock-names = "fck"; 409 assigned-clocks = <&k3_clks 78 1>; 410 assigned-clock-parents = <&k3_clks 78 2>; 411 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 412 ti,timer-pwm; 413 }; 414 415 main_timer16: timer@2500000 { 416 compatible = "ti,am654-timer"; 417 reg = <0x00 0x2500000 0x00 0x400>; 418 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&k3_clks 79 1>; 420 clock-names = "fck"; 421 assigned-clocks = <&k3_clks 79 1>; 422 assigned-clock-parents = <&k3_clks 79 2>; 423 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 424 ti,timer-pwm; 425 }; 426 427 main_timer17: timer@2510000 { 428 compatible = "ti,am654-timer"; 429 reg = <0x00 0x2510000 0x00 0x400>; 430 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&k3_clks 80 1>; 432 clock-names = "fck"; 433 assigned-clocks = <&k3_clks 80 1>; 434 assigned-clock-parents = <&k3_clks 80 2>; 435 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 436 ti,timer-pwm; 437 }; 438 439 main_timer18: timer@2520000 { 440 compatible = "ti,am654-timer"; 441 reg = <0x00 0x2520000 0x00 0x400>; 442 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&k3_clks 81 1>; 444 clock-names = "fck"; 445 assigned-clocks = <&k3_clks 81 1>; 446 assigned-clock-parents = <&k3_clks 81 2>; 447 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 448 ti,timer-pwm; 449 }; 450 451 main_timer19: timer@2530000 { 452 compatible = "ti,am654-timer"; 453 reg = <0x00 0x2530000 0x00 0x400>; 454 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&k3_clks 82 1>; 456 clock-names = "fck"; 457 assigned-clocks = <&k3_clks 82 1>; 458 assigned-clock-parents = <&k3_clks 82 2>; 459 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 460 ti,timer-pwm; 461 }; 462 463 main_uart0: serial@2800000 { 464 compatible = "ti,j721e-uart", "ti,am654-uart"; 465 reg = <0x00 0x02800000 0x00 0x200>; 466 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&k3_clks 146 3>; 468 clock-names = "fclk"; 469 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 470 status = "disabled"; 471 }; 472 473 main_uart1: serial@2810000 { 474 compatible = "ti,j721e-uart", "ti,am654-uart"; 475 reg = <0x00 0x02810000 0x00 0x200>; 476 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&k3_clks 350 3>; 478 clock-names = "fclk"; 479 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 480 status = "disabled"; 481 }; 482 483 main_uart2: serial@2820000 { 484 compatible = "ti,j721e-uart", "ti,am654-uart"; 485 reg = <0x00 0x02820000 0x00 0x200>; 486 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&k3_clks 351 3>; 488 clock-names = "fclk"; 489 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 490 status = "disabled"; 491 }; 492 493 main_uart3: serial@2830000 { 494 compatible = "ti,j721e-uart", "ti,am654-uart"; 495 reg = <0x00 0x02830000 0x00 0x200>; 496 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&k3_clks 352 3>; 498 clock-names = "fclk"; 499 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 500 status = "disabled"; 501 }; 502 503 main_uart4: serial@2840000 { 504 compatible = "ti,j721e-uart", "ti,am654-uart"; 505 reg = <0x00 0x02840000 0x00 0x200>; 506 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&k3_clks 353 3>; 508 clock-names = "fclk"; 509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 510 status = "disabled"; 511 }; 512 513 main_uart5: serial@2850000 { 514 compatible = "ti,j721e-uart", "ti,am654-uart"; 515 reg = <0x00 0x02850000 0x00 0x200>; 516 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&k3_clks 354 3>; 518 clock-names = "fclk"; 519 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 520 status = "disabled"; 521 }; 522 523 main_uart6: serial@2860000 { 524 compatible = "ti,j721e-uart", "ti,am654-uart"; 525 reg = <0x00 0x02860000 0x00 0x200>; 526 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&k3_clks 355 3>; 528 clock-names = "fclk"; 529 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 530 status = "disabled"; 531 }; 532 533 main_uart7: serial@2870000 { 534 compatible = "ti,j721e-uart", "ti,am654-uart"; 535 reg = <0x00 0x02870000 0x00 0x200>; 536 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&k3_clks 356 3>; 538 clock-names = "fclk"; 539 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 540 status = "disabled"; 541 }; 542 543 main_uart8: serial@2880000 { 544 compatible = "ti,j721e-uart", "ti,am654-uart"; 545 reg = <0x00 0x02880000 0x00 0x200>; 546 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&k3_clks 357 3>; 548 clock-names = "fclk"; 549 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 550 status = "disabled"; 551 }; 552 553 main_uart9: serial@2890000 { 554 compatible = "ti,j721e-uart", "ti,am654-uart"; 555 reg = <0x00 0x02890000 0x00 0x200>; 556 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&k3_clks 358 3>; 558 clock-names = "fclk"; 559 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 560 status = "disabled"; 561 }; 562 563 main_gpio0: gpio@600000 { 564 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 565 reg = <0x00 0x00600000 0x00 0x100>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 interrupt-parent = <&main_gpio_intr>; 569 interrupts = <145>, <146>, <147>, <148>, <149>; 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 ti,ngpio = <66>; 573 ti,davinci-gpio-unbanked = <0>; 574 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 575 clocks = <&k3_clks 111 0>; 576 clock-names = "gpio"; 577 status = "disabled"; 578 }; 579 580 main_gpio2: gpio@610000 { 581 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 582 reg = <0x00 0x00610000 0x00 0x100>; 583 gpio-controller; 584 #gpio-cells = <2>; 585 interrupt-parent = <&main_gpio_intr>; 586 interrupts = <154>, <155>, <156>, <157>, <158>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 ti,ngpio = <66>; 590 ti,davinci-gpio-unbanked = <0>; 591 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 592 clocks = <&k3_clks 112 0>; 593 clock-names = "gpio"; 594 status = "disabled"; 595 }; 596 597 main_gpio4: gpio@620000 { 598 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 599 reg = <0x00 0x00620000 0x00 0x100>; 600 gpio-controller; 601 #gpio-cells = <2>; 602 interrupt-parent = <&main_gpio_intr>; 603 interrupts = <163>, <164>, <165>, <166>, <167>; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 ti,ngpio = <66>; 607 ti,davinci-gpio-unbanked = <0>; 608 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 609 clocks = <&k3_clks 113 0>; 610 clock-names = "gpio"; 611 status = "disabled"; 612 }; 613 614 main_gpio6: gpio@630000 { 615 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 616 reg = <0x00 0x00630000 0x00 0x100>; 617 gpio-controller; 618 #gpio-cells = <2>; 619 interrupt-parent = <&main_gpio_intr>; 620 interrupts = <172>, <173>, <174>, <175>, <176>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 ti,ngpio = <66>; 624 ti,davinci-gpio-unbanked = <0>; 625 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 626 clocks = <&k3_clks 114 0>; 627 clock-names = "gpio"; 628 status = "disabled"; 629 }; 630 631 main_i2c0: i2c@2000000 { 632 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 633 reg = <0x00 0x02000000 0x00 0x100>; 634 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 clocks = <&k3_clks 214 1>; 638 clock-names = "fck"; 639 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 640 }; 641 642 main_i2c1: i2c@2010000 { 643 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 644 reg = <0x00 0x02010000 0x00 0x100>; 645 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 clocks = <&k3_clks 215 1>; 649 clock-names = "fck"; 650 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 651 status = "disabled"; 652 }; 653 654 main_i2c2: i2c@2020000 { 655 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 656 reg = <0x00 0x02020000 0x00 0x100>; 657 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 clocks = <&k3_clks 216 1>; 661 clock-names = "fck"; 662 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 663 status = "disabled"; 664 }; 665 666 main_i2c3: i2c@2030000 { 667 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 668 reg = <0x00 0x02030000 0x00 0x100>; 669 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&k3_clks 217 1>; 673 clock-names = "fck"; 674 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 675 status = "disabled"; 676 }; 677 678 main_i2c4: i2c@2040000 { 679 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 680 reg = <0x00 0x02040000 0x00 0x100>; 681 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 clocks = <&k3_clks 218 1>; 685 clock-names = "fck"; 686 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 687 status = "disabled"; 688 }; 689 690 main_i2c5: i2c@2050000 { 691 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 692 reg = <0x00 0x02050000 0x00 0x100>; 693 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&k3_clks 219 1>; 697 clock-names = "fck"; 698 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 699 status = "disabled"; 700 }; 701 702 main_i2c6: i2c@2060000 { 703 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 704 reg = <0x00 0x02060000 0x00 0x100>; 705 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 clocks = <&k3_clks 220 1>; 709 clock-names = "fck"; 710 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 711 status = "disabled"; 712 }; 713 714 vpu: video-codec@4210000 { 715 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 716 reg = <0x00 0x4210000 0x00 0x10000>; 717 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&k3_clks 179 2>; 719 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 720 }; 721 722 main_sdhci0: mmc@4f80000 { 723 compatible = "ti,j721e-sdhci-8bit"; 724 reg = <0x00 0x04f80000 0x00 0x1000>, 725 <0x00 0x04f88000 0x00 0x400>; 726 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 727 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 728 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 729 clock-names = "clk_ahb", "clk_xin"; 730 assigned-clocks = <&k3_clks 98 1>; 731 assigned-clock-parents = <&k3_clks 98 2>; 732 bus-width = <8>; 733 ti,otap-del-sel-legacy = <0x0>; 734 ti,otap-del-sel-mmc-hs = <0x0>; 735 ti,otap-del-sel-ddr52 = <0x6>; 736 ti,otap-del-sel-hs200 = <0x8>; 737 ti,otap-del-sel-hs400 = <0x5>; 738 ti,itap-del-sel-legacy = <0x10>; 739 ti,itap-del-sel-mmc-hs = <0xa>; 740 ti,strobe-sel = <0x77>; 741 ti,clkbuf-sel = <0x7>; 742 ti,trm-icp = <0x8>; 743 mmc-ddr-1_8v; 744 mmc-hs200-1_8v; 745 mmc-hs400-1_8v; 746 dma-coherent; 747 status = "disabled"; 748 }; 749 750 main_sdhci1: mmc@4fb0000 { 751 compatible = "ti,j721e-sdhci-4bit"; 752 reg = <0x00 0x04fb0000 0x00 0x1000>, 753 <0x00 0x04fb8000 0x00 0x400>; 754 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 755 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 756 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 757 clock-names = "clk_ahb", "clk_xin"; 758 assigned-clocks = <&k3_clks 99 1>; 759 assigned-clock-parents = <&k3_clks 99 2>; 760 bus-width = <4>; 761 ti,otap-del-sel-legacy = <0x0>; 762 ti,otap-del-sel-sd-hs = <0x0>; 763 ti,otap-del-sel-sdr12 = <0xf>; 764 ti,otap-del-sel-sdr25 = <0xf>; 765 ti,otap-del-sel-sdr50 = <0xc>; 766 ti,otap-del-sel-sdr104 = <0x5>; 767 ti,otap-del-sel-ddr50 = <0xc>; 768 ti,itap-del-sel-legacy = <0x0>; 769 ti,itap-del-sel-sd-hs = <0x0>; 770 ti,itap-del-sel-sdr12 = <0x0>; 771 ti,itap-del-sel-sdr25 = <0x0>; 772 ti,itap-del-sel-ddr50 = <0x2>; 773 ti,clkbuf-sel = <0x7>; 774 ti,trm-icp = <0x8>; 775 dma-coherent; 776 status = "disabled"; 777 }; 778 779 main_navss: bus@30000000 { 780 compatible = "simple-bus"; 781 #address-cells = <2>; 782 #size-cells = <2>; 783 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 784 ti,sci-dev-id = <224>; 785 dma-coherent; 786 dma-ranges; 787 788 main_navss_intr: interrupt-controller@310e0000 { 789 compatible = "ti,sci-intr"; 790 reg = <0x00 0x310e0000 0x00 0x4000>; 791 ti,intr-trigger-type = <4>; 792 interrupt-controller; 793 interrupt-parent = <&gic500>; 794 #interrupt-cells = <1>; 795 ti,sci = <&sms>; 796 ti,sci-dev-id = <227>; 797 ti,interrupt-ranges = <0 64 64>, 798 <64 448 64>, 799 <128 672 64>; 800 }; 801 802 main_udmass_inta: msi-controller@33d00000 { 803 compatible = "ti,sci-inta"; 804 reg = <0x00 0x33d00000 0x00 0x100000>; 805 interrupt-controller; 806 #interrupt-cells = <0>; 807 interrupt-parent = <&main_navss_intr>; 808 msi-controller; 809 ti,sci = <&sms>; 810 ti,sci-dev-id = <265>; 811 ti,interrupt-ranges = <0 0 256>; 812 ti,unmapped-event-sources = <&main_bcdma_csi>; 813 }; 814 815 secure_proxy_main: mailbox@32c00000 { 816 compatible = "ti,am654-secure-proxy"; 817 #mbox-cells = <1>; 818 reg-names = "target_data", "rt", "scfg"; 819 reg = <0x00 0x32c00000 0x00 0x100000>, 820 <0x00 0x32400000 0x00 0x100000>, 821 <0x00 0x32800000 0x00 0x100000>; 822 interrupt-names = "rx_011"; 823 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 824 bootph-all; 825 }; 826 827 hwspinlock: spinlock@30e00000 { 828 compatible = "ti,am654-hwspinlock"; 829 reg = <0x00 0x30e00000 0x00 0x1000>; 830 #hwlock-cells = <1>; 831 }; 832 833 mailbox0_cluster0: mailbox@31f80000 { 834 compatible = "ti,am654-mailbox"; 835 reg = <0x00 0x31f80000 0x00 0x200>; 836 #mbox-cells = <1>; 837 ti,mbox-num-users = <4>; 838 ti,mbox-num-fifos = <16>; 839 interrupt-parent = <&main_navss_intr>; 840 status = "disabled"; 841 }; 842 843 mailbox0_cluster1: mailbox@31f81000 { 844 compatible = "ti,am654-mailbox"; 845 reg = <0x00 0x31f81000 0x00 0x200>; 846 #mbox-cells = <1>; 847 ti,mbox-num-users = <4>; 848 ti,mbox-num-fifos = <16>; 849 interrupt-parent = <&main_navss_intr>; 850 status = "disabled"; 851 }; 852 853 mailbox0_cluster2: mailbox@31f82000 { 854 compatible = "ti,am654-mailbox"; 855 reg = <0x00 0x31f82000 0x00 0x200>; 856 #mbox-cells = <1>; 857 ti,mbox-num-users = <4>; 858 ti,mbox-num-fifos = <16>; 859 interrupt-parent = <&main_navss_intr>; 860 status = "disabled"; 861 }; 862 863 mailbox0_cluster3: mailbox@31f83000 { 864 compatible = "ti,am654-mailbox"; 865 reg = <0x00 0x31f83000 0x00 0x200>; 866 #mbox-cells = <1>; 867 ti,mbox-num-users = <4>; 868 ti,mbox-num-fifos = <16>; 869 interrupt-parent = <&main_navss_intr>; 870 status = "disabled"; 871 }; 872 873 mailbox0_cluster4: mailbox@31f84000 { 874 compatible = "ti,am654-mailbox"; 875 reg = <0x00 0x31f84000 0x00 0x200>; 876 #mbox-cells = <1>; 877 ti,mbox-num-users = <4>; 878 ti,mbox-num-fifos = <16>; 879 interrupt-parent = <&main_navss_intr>; 880 status = "disabled"; 881 }; 882 883 mailbox0_cluster5: mailbox@31f85000 { 884 compatible = "ti,am654-mailbox"; 885 reg = <0x00 0x31f85000 0x00 0x200>; 886 #mbox-cells = <1>; 887 ti,mbox-num-users = <4>; 888 ti,mbox-num-fifos = <16>; 889 interrupt-parent = <&main_navss_intr>; 890 status = "disabled"; 891 }; 892 893 mailbox0_cluster6: mailbox@31f86000 { 894 compatible = "ti,am654-mailbox"; 895 reg = <0x00 0x31f86000 0x00 0x200>; 896 #mbox-cells = <1>; 897 ti,mbox-num-users = <4>; 898 ti,mbox-num-fifos = <16>; 899 interrupt-parent = <&main_navss_intr>; 900 status = "disabled"; 901 }; 902 903 mailbox0_cluster7: mailbox@31f87000 { 904 compatible = "ti,am654-mailbox"; 905 reg = <0x00 0x31f87000 0x00 0x200>; 906 #mbox-cells = <1>; 907 ti,mbox-num-users = <4>; 908 ti,mbox-num-fifos = <16>; 909 interrupt-parent = <&main_navss_intr>; 910 status = "disabled"; 911 }; 912 913 mailbox0_cluster8: mailbox@31f88000 { 914 compatible = "ti,am654-mailbox"; 915 reg = <0x00 0x31f88000 0x00 0x200>; 916 #mbox-cells = <1>; 917 ti,mbox-num-users = <4>; 918 ti,mbox-num-fifos = <16>; 919 interrupt-parent = <&main_navss_intr>; 920 status = "disabled"; 921 }; 922 923 mailbox0_cluster9: mailbox@31f89000 { 924 compatible = "ti,am654-mailbox"; 925 reg = <0x00 0x31f89000 0x00 0x200>; 926 #mbox-cells = <1>; 927 ti,mbox-num-users = <4>; 928 ti,mbox-num-fifos = <16>; 929 interrupt-parent = <&main_navss_intr>; 930 status = "disabled"; 931 }; 932 933 mailbox0_cluster10: mailbox@31f8a000 { 934 compatible = "ti,am654-mailbox"; 935 reg = <0x00 0x31f8a000 0x00 0x200>; 936 #mbox-cells = <1>; 937 ti,mbox-num-users = <4>; 938 ti,mbox-num-fifos = <16>; 939 interrupt-parent = <&main_navss_intr>; 940 status = "disabled"; 941 }; 942 943 mailbox0_cluster11: mailbox@31f8b000 { 944 compatible = "ti,am654-mailbox"; 945 reg = <0x00 0x31f8b000 0x00 0x200>; 946 #mbox-cells = <1>; 947 ti,mbox-num-users = <4>; 948 ti,mbox-num-fifos = <16>; 949 interrupt-parent = <&main_navss_intr>; 950 status = "disabled"; 951 }; 952 953 mailbox1_cluster0: mailbox@31f90000 { 954 compatible = "ti,am654-mailbox"; 955 reg = <0x00 0x31f90000 0x00 0x200>; 956 #mbox-cells = <1>; 957 ti,mbox-num-users = <4>; 958 ti,mbox-num-fifos = <16>; 959 interrupt-parent = <&main_navss_intr>; 960 status = "disabled"; 961 }; 962 963 mailbox1_cluster1: mailbox@31f91000 { 964 compatible = "ti,am654-mailbox"; 965 reg = <0x00 0x31f91000 0x00 0x200>; 966 #mbox-cells = <1>; 967 ti,mbox-num-users = <4>; 968 ti,mbox-num-fifos = <16>; 969 interrupt-parent = <&main_navss_intr>; 970 status = "disabled"; 971 }; 972 973 mailbox1_cluster2: mailbox@31f92000 { 974 compatible = "ti,am654-mailbox"; 975 reg = <0x00 0x31f92000 0x00 0x200>; 976 #mbox-cells = <1>; 977 ti,mbox-num-users = <4>; 978 ti,mbox-num-fifos = <16>; 979 interrupt-parent = <&main_navss_intr>; 980 status = "disabled"; 981 }; 982 983 mailbox1_cluster3: mailbox@31f93000 { 984 compatible = "ti,am654-mailbox"; 985 reg = <0x00 0x31f93000 0x00 0x200>; 986 #mbox-cells = <1>; 987 ti,mbox-num-users = <4>; 988 ti,mbox-num-fifos = <16>; 989 interrupt-parent = <&main_navss_intr>; 990 status = "disabled"; 991 }; 992 993 mailbox1_cluster4: mailbox@31f94000 { 994 compatible = "ti,am654-mailbox"; 995 reg = <0x00 0x31f94000 0x00 0x200>; 996 #mbox-cells = <1>; 997 ti,mbox-num-users = <4>; 998 ti,mbox-num-fifos = <16>; 999 interrupt-parent = <&main_navss_intr>; 1000 status = "disabled"; 1001 }; 1002 1003 mailbox1_cluster5: mailbox@31f95000 { 1004 compatible = "ti,am654-mailbox"; 1005 reg = <0x00 0x31f95000 0x00 0x200>; 1006 #mbox-cells = <1>; 1007 ti,mbox-num-users = <4>; 1008 ti,mbox-num-fifos = <16>; 1009 interrupt-parent = <&main_navss_intr>; 1010 status = "disabled"; 1011 }; 1012 1013 mailbox1_cluster6: mailbox@31f96000 { 1014 compatible = "ti,am654-mailbox"; 1015 reg = <0x00 0x31f96000 0x00 0x200>; 1016 #mbox-cells = <1>; 1017 ti,mbox-num-users = <4>; 1018 ti,mbox-num-fifos = <16>; 1019 interrupt-parent = <&main_navss_intr>; 1020 status = "disabled"; 1021 }; 1022 1023 mailbox1_cluster7: mailbox@31f97000 { 1024 compatible = "ti,am654-mailbox"; 1025 reg = <0x00 0x31f97000 0x00 0x200>; 1026 #mbox-cells = <1>; 1027 ti,mbox-num-users = <4>; 1028 ti,mbox-num-fifos = <16>; 1029 interrupt-parent = <&main_navss_intr>; 1030 status = "disabled"; 1031 }; 1032 1033 mailbox1_cluster8: mailbox@31f98000 { 1034 compatible = "ti,am654-mailbox"; 1035 reg = <0x00 0x31f98000 0x00 0x200>; 1036 #mbox-cells = <1>; 1037 ti,mbox-num-users = <4>; 1038 ti,mbox-num-fifos = <16>; 1039 interrupt-parent = <&main_navss_intr>; 1040 status = "disabled"; 1041 }; 1042 1043 mailbox1_cluster9: mailbox@31f99000 { 1044 compatible = "ti,am654-mailbox"; 1045 reg = <0x00 0x31f99000 0x00 0x200>; 1046 #mbox-cells = <1>; 1047 ti,mbox-num-users = <4>; 1048 ti,mbox-num-fifos = <16>; 1049 interrupt-parent = <&main_navss_intr>; 1050 status = "disabled"; 1051 }; 1052 1053 mailbox1_cluster10: mailbox@31f9a000 { 1054 compatible = "ti,am654-mailbox"; 1055 reg = <0x00 0x31f9a000 0x00 0x200>; 1056 #mbox-cells = <1>; 1057 ti,mbox-num-users = <4>; 1058 ti,mbox-num-fifos = <16>; 1059 interrupt-parent = <&main_navss_intr>; 1060 status = "disabled"; 1061 }; 1062 1063 mailbox1_cluster11: mailbox@31f9b000 { 1064 compatible = "ti,am654-mailbox"; 1065 reg = <0x00 0x31f9b000 0x00 0x200>; 1066 #mbox-cells = <1>; 1067 ti,mbox-num-users = <4>; 1068 ti,mbox-num-fifos = <16>; 1069 interrupt-parent = <&main_navss_intr>; 1070 status = "disabled"; 1071 }; 1072 1073 main_ringacc: ringacc@3c000000 { 1074 compatible = "ti,am654-navss-ringacc"; 1075 reg = <0x0 0x3c000000 0x0 0x400000>, 1076 <0x0 0x38000000 0x0 0x400000>, 1077 <0x0 0x31120000 0x0 0x100>, 1078 <0x0 0x33000000 0x0 0x40000>, 1079 <0x0 0x31080000 0x0 0x40000>; 1080 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1081 ti,num-rings = <1024>; 1082 ti,sci-rm-range-gp-rings = <0x1>; 1083 ti,sci = <&sms>; 1084 ti,sci-dev-id = <259>; 1085 msi-parent = <&main_udmass_inta>; 1086 }; 1087 1088 main_udmap: dma-controller@31150000 { 1089 compatible = "ti,j721e-navss-main-udmap"; 1090 reg = <0x0 0x31150000 0x0 0x100>, 1091 <0x0 0x34000000 0x0 0x80000>, 1092 <0x0 0x35000000 0x0 0x200000>, 1093 <0x0 0x30b00000 0x0 0x20000>, 1094 <0x0 0x30c00000 0x0 0x8000>, 1095 <0x0 0x30d00000 0x0 0x4000>; 1096 reg-names = "gcfg", "rchanrt", "tchanrt", 1097 "tchan", "rchan", "rflow"; 1098 msi-parent = <&main_udmass_inta>; 1099 #dma-cells = <1>; 1100 1101 ti,sci = <&sms>; 1102 ti,sci-dev-id = <263>; 1103 ti,ringacc = <&main_ringacc>; 1104 1105 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1106 <0x0f>, /* TX_HCHAN */ 1107 <0x10>; /* TX_UHCHAN */ 1108 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1109 <0x0b>, /* RX_HCHAN */ 1110 <0x0c>; /* RX_UHCHAN */ 1111 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1112 }; 1113 1114 main_bcdma_csi: dma-controller@311a0000 { 1115 compatible = "ti,j721s2-dmss-bcdma-csi"; 1116 reg = <0x00 0x311a0000 0x00 0x100>, 1117 <0x00 0x35d00000 0x00 0x20000>, 1118 <0x00 0x35c00000 0x00 0x10000>, 1119 <0x00 0x35e00000 0x00 0x80000>; 1120 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1121 msi-parent = <&main_udmass_inta>; 1122 #dma-cells = <3>; 1123 ti,sci = <&sms>; 1124 ti,sci-dev-id = <225>; 1125 ti,sci-rm-range-rchan = <0x21>; 1126 ti,sci-rm-range-tchan = <0x22>; 1127 }; 1128 1129 cpts@310d0000 { 1130 compatible = "ti,j721e-cpts"; 1131 reg = <0x0 0x310d0000 0x0 0x400>; 1132 reg-names = "cpts"; 1133 clocks = <&k3_clks 226 5>; 1134 clock-names = "cpts"; 1135 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1136 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1137 interrupts-extended = <&main_navss_intr 391>; 1138 interrupt-names = "cpts"; 1139 ti,cpts-periodic-outputs = <6>; 1140 ti,cpts-ext-ts-inputs = <8>; 1141 }; 1142 }; 1143 1144 main_cpsw: ethernet@c200000 { 1145 compatible = "ti,j721e-cpsw-nuss"; 1146 reg = <0x00 0xc200000 0x00 0x200000>; 1147 reg-names = "cpsw_nuss"; 1148 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; 1149 #address-cells = <2>; 1150 #size-cells = <2>; 1151 dma-coherent; 1152 clocks = <&k3_clks 28 28>; 1153 clock-names = "fck"; 1154 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 1155 1156 dmas = <&main_udmap 0xc640>, 1157 <&main_udmap 0xc641>, 1158 <&main_udmap 0xc642>, 1159 <&main_udmap 0xc643>, 1160 <&main_udmap 0xc644>, 1161 <&main_udmap 0xc645>, 1162 <&main_udmap 0xc646>, 1163 <&main_udmap 0xc647>, 1164 <&main_udmap 0x4640>; 1165 dma-names = "tx0", "tx1", "tx2", "tx3", 1166 "tx4", "tx5", "tx6", "tx7", 1167 "rx"; 1168 1169 status = "disabled"; 1170 1171 ethernet-ports { 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 main_cpsw_port1: port@1 { 1176 reg = <1>; 1177 ti,mac-only; 1178 label = "port1"; 1179 phys = <&phy_gmii_sel_cpsw 1>; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 main_cpsw_mdio: mdio@f00 { 1185 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1186 reg = <0x00 0xf00 0x00 0x100>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 clocks = <&k3_clks 28 28>; 1190 clock-names = "fck"; 1191 bus_freq = <1000000>; 1192 status = "disabled"; 1193 }; 1194 1195 cpts@3d000 { 1196 compatible = "ti,am65-cpts"; 1197 reg = <0x00 0x3d000 0x00 0x400>; 1198 clocks = <&k3_clks 28 3>; 1199 clock-names = "cpts"; 1200 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "cpts"; 1202 ti,cpts-ext-ts-inputs = <4>; 1203 ti,cpts-periodic-outputs = <2>; 1204 }; 1205 }; 1206 1207 usbss0: cdns-usb@4104000 { 1208 compatible = "ti,j721e-usb"; 1209 reg = <0x00 0x04104000 0x00 0x100>; 1210 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 1211 clock-names = "ref", "lpm"; 1212 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 1213 assigned-clock-parents = <&k3_clks 360 17>; 1214 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1215 #address-cells = <2>; 1216 #size-cells = <2>; 1217 ranges; 1218 dma-coherent; 1219 1220 status = "disabled"; /* Needs pinmux */ 1221 1222 usb0: usb@6000000 { 1223 compatible = "cdns,usb3"; 1224 reg = <0x00 0x06000000 0x00 0x10000>, 1225 <0x00 0x06010000 0x00 0x10000>, 1226 <0x00 0x06020000 0x00 0x10000>; 1227 reg-names = "otg", "xhci", "dev"; 1228 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "host", "peripheral", "otg"; 1232 maximum-speed = "super-speed"; 1233 dr_mode = "otg"; 1234 }; 1235 }; 1236 1237 ti_csi2rx0: ticsi2rx@4500000 { 1238 compatible = "ti,j721e-csi2rx-shim"; 1239 reg = <0x00 0x04500000 0x00 0x1000>; 1240 ranges; 1241 #address-cells = <2>; 1242 #size-cells = <2>; 1243 dmas = <&main_bcdma_csi 0 0x4940 0>; 1244 dma-names = "rx0"; 1245 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 1246 status = "disabled"; 1247 1248 cdns_csi2rx0: csi-bridge@4504000 { 1249 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1250 reg = <0x00 0x04504000 0x00 0x1000>; 1251 clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, 1252 <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; 1253 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1254 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1255 phys = <&dphy0>; 1256 phy-names = "dphy"; 1257 1258 ports { 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 1262 csi0_port0: port@0 { 1263 reg = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 csi0_port1: port@1 { 1268 reg = <1>; 1269 status = "disabled"; 1270 }; 1271 1272 csi0_port2: port@2 { 1273 reg = <2>; 1274 status = "disabled"; 1275 }; 1276 1277 csi0_port3: port@3 { 1278 reg = <3>; 1279 status = "disabled"; 1280 }; 1281 1282 csi0_port4: port@4 { 1283 reg = <4>; 1284 status = "disabled"; 1285 }; 1286 }; 1287 }; 1288 }; 1289 1290 ti_csi2rx1: ticsi2rx@4510000 { 1291 compatible = "ti,j721e-csi2rx-shim"; 1292 reg = <0x00 0x04510000 0x00 0x1000>; 1293 ranges; 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 dmas = <&main_bcdma_csi 0 0x4960 0>; 1297 dma-names = "rx0"; 1298 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 1299 status = "disabled"; 1300 1301 cdns_csi2rx1: csi-bridge@4514000 { 1302 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1303 reg = <0x00 0x04514000 0x00 0x1000>; 1304 clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, 1305 <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; 1306 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1307 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1308 phys = <&dphy1>; 1309 phy-names = "dphy"; 1310 1311 ports { 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 1315 csi1_port0: port@0 { 1316 reg = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 csi1_port1: port@1 { 1321 reg = <1>; 1322 status = "disabled"; 1323 }; 1324 1325 csi1_port2: port@2 { 1326 reg = <2>; 1327 status = "disabled"; 1328 }; 1329 1330 csi1_port3: port@3 { 1331 reg = <3>; 1332 status = "disabled"; 1333 }; 1334 1335 csi1_port4: port@4 { 1336 reg = <4>; 1337 status = "disabled"; 1338 }; 1339 }; 1340 }; 1341 }; 1342 1343 dphy0: phy@4580000 { 1344 compatible = "cdns,dphy-rx"; 1345 reg = <0x00 0x04580000 0x00 0x1100>; 1346 #phy-cells = <0>; 1347 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1348 status = "disabled"; 1349 }; 1350 1351 dphy1: phy@4590000 { 1352 compatible = "cdns,dphy-rx"; 1353 reg = <0x00 0x04590000 0x00 0x1100>; 1354 #phy-cells = <0>; 1355 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 1356 status = "disabled"; 1357 }; 1358 1359 serdes_wiz0: wiz@5060000 { 1360 compatible = "ti,j721s2-wiz-10g"; 1361 #address-cells = <1>; 1362 #size-cells = <1>; 1363 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1364 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1365 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1366 num-lanes = <4>; 1367 #reset-cells = <1>; 1368 #clock-cells = <1>; 1369 ranges = <0x5060000 0x0 0x5060000 0x10000>; 1370 1371 assigned-clocks = <&k3_clks 365 3>; 1372 assigned-clock-parents = <&k3_clks 365 7>; 1373 1374 serdes0: serdes@5060000 { 1375 compatible = "ti,j721e-serdes-10g"; 1376 reg = <0x05060000 0x00010000>; 1377 reg-names = "torrent_phy"; 1378 resets = <&serdes_wiz0 0>; 1379 reset-names = "torrent_reset"; 1380 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1381 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1382 clock-names = "refclk", "phy_en_refclk"; 1383 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1384 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1385 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1386 assigned-clock-parents = <&k3_clks 365 3>, 1387 <&k3_clks 365 3>, 1388 <&k3_clks 365 3>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 #clock-cells = <1>; 1392 1393 status = "disabled"; /* Needs lane config */ 1394 }; 1395 }; 1396 1397 pcie1_rc: pcie@2910000 { 1398 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1399 reg = <0x00 0x02910000 0x00 0x1000>, 1400 <0x00 0x02917000 0x00 0x400>, 1401 <0x00 0x0d800000 0x00 0x800000>, 1402 <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */ 1403 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1404 interrupt-names = "link_state"; 1405 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1406 device_type = "pci"; 1407 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1408 max-link-speed = <3>; 1409 num-lanes = <4>; 1410 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1411 clocks = <&k3_clks 276 41>; 1412 clock-names = "fck"; 1413 #address-cells = <3>; 1414 #size-cells = <2>; 1415 bus-range = <0x0 0xff>; 1416 vendor-id = <0x104c>; 1417 device-id = <0xb013>; 1418 msi-map = <0x0 &gic_its 0x0 0x10000>; 1419 dma-coherent; 1420 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1421 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1422 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1423 #interrupt-cells = <1>; 1424 interrupt-map-mask = <0 0 0 7>; 1425 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1426 <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1427 <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1428 <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1429 1430 status = "disabled"; /* Needs gpio and serdes info */ 1431 1432 pcie1_intc: interrupt-controller { 1433 interrupt-controller; 1434 #interrupt-cells = <1>; 1435 interrupt-parent = <&gic500>; 1436 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1437 }; 1438 }; 1439 1440 main_mcan0: can@2701000 { 1441 compatible = "bosch,m_can"; 1442 reg = <0x00 0x02701000 0x00 0x200>, 1443 <0x00 0x02708000 0x00 0x8000>; 1444 reg-names = "m_can", "message_ram"; 1445 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1446 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1447 clock-names = "hclk", "cclk"; 1448 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1450 interrupt-names = "int0", "int1"; 1451 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1452 status = "disabled"; 1453 }; 1454 1455 main_mcan1: can@2711000 { 1456 compatible = "bosch,m_can"; 1457 reg = <0x00 0x02711000 0x00 0x200>, 1458 <0x00 0x02718000 0x00 0x8000>; 1459 reg-names = "m_can", "message_ram"; 1460 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1461 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1462 clock-names = "hclk", "cclk"; 1463 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1465 interrupt-names = "int0", "int1"; 1466 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1467 status = "disabled"; 1468 }; 1469 1470 main_mcan2: can@2721000 { 1471 compatible = "bosch,m_can"; 1472 reg = <0x00 0x02721000 0x00 0x200>, 1473 <0x00 0x02728000 0x00 0x8000>; 1474 reg-names = "m_can", "message_ram"; 1475 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1476 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1477 clock-names = "hclk", "cclk"; 1478 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1480 interrupt-names = "int0", "int1"; 1481 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1482 status = "disabled"; 1483 }; 1484 1485 main_mcan3: can@2731000 { 1486 compatible = "bosch,m_can"; 1487 reg = <0x00 0x02731000 0x00 0x200>, 1488 <0x00 0x02738000 0x00 0x8000>; 1489 reg-names = "m_can", "message_ram"; 1490 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1491 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1492 clock-names = "hclk", "cclk"; 1493 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1495 interrupt-names = "int0", "int1"; 1496 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1497 status = "disabled"; 1498 }; 1499 1500 main_mcan4: can@2741000 { 1501 compatible = "bosch,m_can"; 1502 reg = <0x00 0x02741000 0x00 0x200>, 1503 <0x00 0x02748000 0x00 0x8000>; 1504 reg-names = "m_can", "message_ram"; 1505 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1506 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1507 clock-names = "hclk", "cclk"; 1508 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1510 interrupt-names = "int0", "int1"; 1511 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1512 status = "disabled"; 1513 }; 1514 1515 main_mcan5: can@2751000 { 1516 compatible = "bosch,m_can"; 1517 reg = <0x00 0x02751000 0x00 0x200>, 1518 <0x00 0x02758000 0x00 0x8000>; 1519 reg-names = "m_can", "message_ram"; 1520 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1521 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1522 clock-names = "hclk", "cclk"; 1523 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupt-names = "int0", "int1"; 1526 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1527 status = "disabled"; 1528 }; 1529 1530 main_mcan6: can@2761000 { 1531 compatible = "bosch,m_can"; 1532 reg = <0x00 0x02761000 0x00 0x200>, 1533 <0x00 0x02768000 0x00 0x8000>; 1534 reg-names = "m_can", "message_ram"; 1535 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1536 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1537 clock-names = "hclk", "cclk"; 1538 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "int0", "int1"; 1541 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1542 status = "disabled"; 1543 }; 1544 1545 main_mcan7: can@2771000 { 1546 compatible = "bosch,m_can"; 1547 reg = <0x00 0x02771000 0x00 0x200>, 1548 <0x00 0x02778000 0x00 0x8000>; 1549 reg-names = "m_can", "message_ram"; 1550 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1551 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1552 clock-names = "hclk", "cclk"; 1553 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "int0", "int1"; 1556 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1557 status = "disabled"; 1558 }; 1559 1560 main_mcan8: can@2781000 { 1561 compatible = "bosch,m_can"; 1562 reg = <0x00 0x02781000 0x00 0x200>, 1563 <0x00 0x02788000 0x00 0x8000>; 1564 reg-names = "m_can", "message_ram"; 1565 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1566 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1567 clock-names = "hclk", "cclk"; 1568 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1570 interrupt-names = "int0", "int1"; 1571 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1572 status = "disabled"; 1573 }; 1574 1575 main_mcan9: can@2791000 { 1576 compatible = "bosch,m_can"; 1577 reg = <0x00 0x02791000 0x00 0x200>, 1578 <0x00 0x02798000 0x00 0x8000>; 1579 reg-names = "m_can", "message_ram"; 1580 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1581 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1582 clock-names = "hclk", "cclk"; 1583 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1585 interrupt-names = "int0", "int1"; 1586 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1587 status = "disabled"; 1588 }; 1589 1590 main_mcan10: can@27a1000 { 1591 compatible = "bosch,m_can"; 1592 reg = <0x00 0x027a1000 0x00 0x200>, 1593 <0x00 0x027a8000 0x00 0x8000>; 1594 reg-names = "m_can", "message_ram"; 1595 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1596 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1597 clock-names = "hclk", "cclk"; 1598 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1600 interrupt-names = "int0", "int1"; 1601 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1602 status = "disabled"; 1603 }; 1604 1605 main_mcan11: can@27b1000 { 1606 compatible = "bosch,m_can"; 1607 reg = <0x00 0x027b1000 0x00 0x200>, 1608 <0x00 0x027b8000 0x00 0x8000>; 1609 reg-names = "m_can", "message_ram"; 1610 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1611 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1612 clock-names = "hclk", "cclk"; 1613 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1615 interrupt-names = "int0", "int1"; 1616 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1617 status = "disabled"; 1618 }; 1619 1620 main_mcan12: can@27c1000 { 1621 compatible = "bosch,m_can"; 1622 reg = <0x00 0x027c1000 0x00 0x200>, 1623 <0x00 0x027c8000 0x00 0x8000>; 1624 reg-names = "m_can", "message_ram"; 1625 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1626 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1627 clock-names = "hclk", "cclk"; 1628 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1630 interrupt-names = "int0", "int1"; 1631 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1632 status = "disabled"; 1633 }; 1634 1635 main_mcan13: can@27d1000 { 1636 compatible = "bosch,m_can"; 1637 reg = <0x00 0x027d1000 0x00 0x200>, 1638 <0x00 0x027d8000 0x00 0x8000>; 1639 reg-names = "m_can", "message_ram"; 1640 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1641 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1642 clock-names = "hclk", "cclk"; 1643 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1645 interrupt-names = "int0", "int1"; 1646 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1647 status = "disabled"; 1648 }; 1649 1650 main_mcan14: can@2681000 { 1651 compatible = "bosch,m_can"; 1652 reg = <0x00 0x02681000 0x00 0x200>, 1653 <0x00 0x02688000 0x00 0x8000>; 1654 reg-names = "m_can", "message_ram"; 1655 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1656 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1657 clock-names = "hclk", "cclk"; 1658 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1660 interrupt-names = "int0", "int1"; 1661 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1662 status = "disabled"; 1663 }; 1664 1665 main_mcan15: can@2691000 { 1666 compatible = "bosch,m_can"; 1667 reg = <0x00 0x02691000 0x00 0x200>, 1668 <0x00 0x02698000 0x00 0x8000>; 1669 reg-names = "m_can", "message_ram"; 1670 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1671 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1672 clock-names = "hclk", "cclk"; 1673 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "int0", "int1"; 1676 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1677 status = "disabled"; 1678 }; 1679 1680 main_mcan16: can@26a1000 { 1681 compatible = "bosch,m_can"; 1682 reg = <0x00 0x026a1000 0x00 0x200>, 1683 <0x00 0x026a8000 0x00 0x8000>; 1684 reg-names = "m_can", "message_ram"; 1685 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1686 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1687 clock-names = "hclk", "cclk"; 1688 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1690 interrupt-names = "int0", "int1"; 1691 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1692 status = "disabled"; 1693 }; 1694 1695 main_mcan17: can@26b1000 { 1696 compatible = "bosch,m_can"; 1697 reg = <0x00 0x026b1000 0x00 0x200>, 1698 <0x00 0x026b8000 0x00 0x8000>; 1699 reg-names = "m_can", "message_ram"; 1700 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1701 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1702 clock-names = "hclk", "cclk"; 1703 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1705 interrupt-names = "int0", "int1"; 1706 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1707 status = "disabled"; 1708 }; 1709 1710 main_spi0: spi@2100000 { 1711 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1712 reg = <0x00 0x02100000 0x00 0x400>; 1713 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1717 clocks = <&k3_clks 339 2>; 1718 status = "disabled"; 1719 }; 1720 1721 main_spi1: spi@2110000 { 1722 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1723 reg = <0x00 0x02110000 0x00 0x400>; 1724 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1728 clocks = <&k3_clks 340 2>; 1729 status = "disabled"; 1730 }; 1731 1732 main_spi2: spi@2120000 { 1733 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1734 reg = <0x00 0x02120000 0x00 0x400>; 1735 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1739 clocks = <&k3_clks 341 2>; 1740 status = "disabled"; 1741 }; 1742 1743 main_spi3: spi@2130000 { 1744 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1745 reg = <0x00 0x02130000 0x00 0x400>; 1746 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1750 clocks = <&k3_clks 342 2>; 1751 status = "disabled"; 1752 }; 1753 1754 main_spi4: spi@2140000 { 1755 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1756 reg = <0x00 0x02140000 0x00 0x400>; 1757 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1761 clocks = <&k3_clks 343 2>; 1762 status = "disabled"; 1763 }; 1764 1765 main_spi5: spi@2150000 { 1766 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1767 reg = <0x00 0x02150000 0x00 0x400>; 1768 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1772 clocks = <&k3_clks 344 2>; 1773 status = "disabled"; 1774 }; 1775 1776 main_spi6: spi@2160000 { 1777 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1778 reg = <0x00 0x02160000 0x00 0x400>; 1779 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1783 clocks = <&k3_clks 345 2>; 1784 status = "disabled"; 1785 }; 1786 1787 main_spi7: spi@2170000 { 1788 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1789 reg = <0x00 0x02170000 0x00 0x400>; 1790 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1794 clocks = <&k3_clks 346 2>; 1795 status = "disabled"; 1796 }; 1797 1798 dss: dss@4a00000 { 1799 compatible = "ti,j721e-dss"; 1800 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1801 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1802 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1803 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1804 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1805 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1806 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1807 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1808 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1809 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1810 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1811 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1812 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1813 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1814 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1815 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1816 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1817 reg-names = "common_m", "common_s0", 1818 "common_s1", "common_s2", 1819 "vidl1", "vidl2","vid1","vid2", 1820 "ovr1", "ovr2", "ovr3", "ovr4", 1821 "vp1", "vp2", "vp3", "vp4", 1822 "wb"; 1823 clocks = <&k3_clks 158 0>, 1824 <&k3_clks 158 2>, 1825 <&k3_clks 158 5>, 1826 <&k3_clks 158 14>, 1827 <&k3_clks 158 18>; 1828 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1829 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 1830 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1834 interrupt-names = "common_m", 1835 "common_s0", 1836 "common_s1", 1837 "common_s2"; 1838 status = "disabled"; 1839 1840 dss_ports: ports { 1841 }; 1842 }; 1843 1844 main_r5fss0: r5fss@5c00000 { 1845 compatible = "ti,j721s2-r5fss"; 1846 ti,cluster-mode = <1>; 1847 #address-cells = <1>; 1848 #size-cells = <1>; 1849 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1850 <0x5d00000 0x00 0x5d00000 0x20000>; 1851 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1852 1853 main_r5fss0_core0: r5f@5c00000 { 1854 compatible = "ti,j721s2-r5f"; 1855 reg = <0x5c00000 0x00010000>, 1856 <0x5c10000 0x00010000>; 1857 reg-names = "atcm", "btcm"; 1858 ti,sci = <&sms>; 1859 ti,sci-dev-id = <279>; 1860 ti,sci-proc-ids = <0x06 0xff>; 1861 resets = <&k3_reset 279 1>; 1862 firmware-name = "j721s2-main-r5f0_0-fw"; 1863 ti,atcm-enable = <1>; 1864 ti,btcm-enable = <1>; 1865 ti,loczrama = <1>; 1866 }; 1867 1868 main_r5fss0_core1: r5f@5d00000 { 1869 compatible = "ti,j721s2-r5f"; 1870 reg = <0x5d00000 0x00010000>, 1871 <0x5d10000 0x00010000>; 1872 reg-names = "atcm", "btcm"; 1873 ti,sci = <&sms>; 1874 ti,sci-dev-id = <280>; 1875 ti,sci-proc-ids = <0x07 0xff>; 1876 resets = <&k3_reset 280 1>; 1877 firmware-name = "j721s2-main-r5f0_1-fw"; 1878 ti,atcm-enable = <1>; 1879 ti,btcm-enable = <1>; 1880 ti,loczrama = <1>; 1881 }; 1882 }; 1883 1884 main_r5fss1: r5fss@5e00000 { 1885 compatible = "ti,j721s2-r5fss"; 1886 ti,cluster-mode = <1>; 1887 #address-cells = <1>; 1888 #size-cells = <1>; 1889 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1890 <0x5f00000 0x00 0x5f00000 0x20000>; 1891 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1892 1893 main_r5fss1_core0: r5f@5e00000 { 1894 compatible = "ti,j721s2-r5f"; 1895 reg = <0x5e00000 0x00010000>, 1896 <0x5e10000 0x00010000>; 1897 reg-names = "atcm", "btcm"; 1898 ti,sci = <&sms>; 1899 ti,sci-dev-id = <281>; 1900 ti,sci-proc-ids = <0x08 0xff>; 1901 resets = <&k3_reset 281 1>; 1902 firmware-name = "j721s2-main-r5f1_0-fw"; 1903 ti,atcm-enable = <1>; 1904 ti,btcm-enable = <1>; 1905 ti,loczrama = <1>; 1906 }; 1907 1908 main_r5fss1_core1: r5f@5f00000 { 1909 compatible = "ti,j721s2-r5f"; 1910 reg = <0x5f00000 0x00010000>, 1911 <0x5f10000 0x00010000>; 1912 reg-names = "atcm", "btcm"; 1913 ti,sci = <&sms>; 1914 ti,sci-dev-id = <282>; 1915 ti,sci-proc-ids = <0x09 0xff>; 1916 resets = <&k3_reset 282 1>; 1917 firmware-name = "j721s2-main-r5f1_1-fw"; 1918 ti,atcm-enable = <1>; 1919 ti,btcm-enable = <1>; 1920 ti,loczrama = <1>; 1921 }; 1922 }; 1923 1924 c71_0: dsp@64800000 { 1925 compatible = "ti,j721s2-c71-dsp"; 1926 reg = <0x00 0x64800000 0x00 0x00080000>, 1927 <0x00 0x64e00000 0x00 0x0000c000>; 1928 reg-names = "l2sram", "l1dram"; 1929 ti,sci = <&sms>; 1930 ti,sci-dev-id = <8>; 1931 ti,sci-proc-ids = <0x30 0xff>; 1932 resets = <&k3_reset 8 1>; 1933 firmware-name = "j721s2-c71_0-fw"; 1934 status = "disabled"; 1935 }; 1936 1937 c71_1: dsp@65800000 { 1938 compatible = "ti,j721s2-c71-dsp"; 1939 reg = <0x00 0x65800000 0x00 0x00080000>, 1940 <0x00 0x65e00000 0x00 0x0000c000>; 1941 reg-names = "l2sram", "l1dram"; 1942 ti,sci = <&sms>; 1943 ti,sci-dev-id = <11>; 1944 ti,sci-proc-ids = <0x31 0xff>; 1945 resets = <&k3_reset 11 1>; 1946 firmware-name = "j721s2-c71_1-fw"; 1947 status = "disabled"; 1948 }; 1949 1950 main_esm: esm@700000 { 1951 compatible = "ti,j721e-esm"; 1952 reg = <0x00 0x700000 0x00 0x1000>; 1953 ti,esm-pins = <688>, <689>; 1954 bootph-pre-ram; 1955 }; 1956 1957 watchdog0: watchdog@2200000 { 1958 compatible = "ti,j7-rti-wdt"; 1959 reg = <0x00 0x2200000 0x00 0x100>; 1960 clocks = <&k3_clks 286 1>; 1961 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1962 assigned-clocks = <&k3_clks 286 1>; 1963 assigned-clock-parents = <&k3_clks 286 5>; 1964 }; 1965 1966 watchdog1: watchdog@2210000 { 1967 compatible = "ti,j7-rti-wdt"; 1968 reg = <0x00 0x2210000 0x00 0x100>; 1969 clocks = <&k3_clks 287 1>; 1970 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 1971 assigned-clocks = <&k3_clks 287 1>; 1972 assigned-clock-parents = <&k3_clks 287 5>; 1973 }; 1974 1975 /* 1976 * The following RTI instances are coupled with MCU R5Fs, c7x and 1977 * GPU so keeping them reserved as these will be used by their 1978 * respective firmware 1979 */ 1980 watchdog2: watchdog@22f0000 { 1981 compatible = "ti,j7-rti-wdt"; 1982 reg = <0x00 0x22f0000 0x00 0x100>; 1983 clocks = <&k3_clks 290 1>; 1984 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; 1985 assigned-clocks = <&k3_clks 290 1>; 1986 assigned-clock-parents = <&k3_clks 290 5>; 1987 /* reserved for GPU */ 1988 status = "reserved"; 1989 }; 1990 1991 watchdog3: watchdog@2300000 { 1992 compatible = "ti,j7-rti-wdt"; 1993 reg = <0x00 0x2300000 0x00 0x100>; 1994 clocks = <&k3_clks 288 1>; 1995 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1996 assigned-clocks = <&k3_clks 288 1>; 1997 assigned-clock-parents = <&k3_clks 288 5>; 1998 /* reserved for C7X_0 */ 1999 status = "reserved"; 2000 }; 2001 2002 watchdog4: watchdog@2310000 { 2003 compatible = "ti,j7-rti-wdt"; 2004 reg = <0x00 0x2310000 0x00 0x100>; 2005 clocks = <&k3_clks 289 1>; 2006 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 2007 assigned-clocks = <&k3_clks 289 1>; 2008 assigned-clock-parents = <&k3_clks 289 5>; 2009 /* reserved for C7X_1 */ 2010 status = "reserved"; 2011 }; 2012 2013 watchdog5: watchdog@23c0000 { 2014 compatible = "ti,j7-rti-wdt"; 2015 reg = <0x00 0x23c0000 0x00 0x100>; 2016 clocks = <&k3_clks 291 1>; 2017 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; 2018 assigned-clocks = <&k3_clks 291 1>; 2019 assigned-clock-parents = <&k3_clks 291 5>; 2020 /* reserved for MAIN_R5F0_0 */ 2021 status = "reserved"; 2022 }; 2023 2024 watchdog6: watchdog@23d0000 { 2025 compatible = "ti,j7-rti-wdt"; 2026 reg = <0x00 0x23d0000 0x00 0x100>; 2027 clocks = <&k3_clks 292 1>; 2028 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 2029 assigned-clocks = <&k3_clks 292 1>; 2030 assigned-clock-parents = <&k3_clks 292 5>; 2031 /* reserved for MAIN_R5F0_1 */ 2032 status = "reserved"; 2033 }; 2034 2035 watchdog7: watchdog@23e0000 { 2036 compatible = "ti,j7-rti-wdt"; 2037 reg = <0x00 0x23e0000 0x00 0x100>; 2038 clocks = <&k3_clks 293 1>; 2039 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 2040 assigned-clocks = <&k3_clks 293 1>; 2041 assigned-clock-parents = <&k3_clks 293 5>; 2042 /* reserved for MAIN_R5F1_0 */ 2043 status = "reserved"; 2044 }; 2045 2046 watchdog8: watchdog@23f0000 { 2047 compatible = "ti,j7-rti-wdt"; 2048 reg = <0x00 0x23f0000 0x00 0x100>; 2049 clocks = <&k3_clks 294 1>; 2050 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 2051 assigned-clocks = <&k3_clks 294 1>; 2052 assigned-clock-parents = <&k3_clks 294 5>; 2053 /* reserved for MAIN_R5F1_1 */ 2054 status = "reserved"; 2055 }; 2056 2057 gpu: gpu@4e20000000 { 2058 compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; 2059 reg = <0x4e 0x20000000 0x00 0x80000>; 2060 clocks = <&k3_clks 130 1>; 2061 clock-names = "core"; 2062 assigned-clocks = <&k3_clks 130 1>; 2063 assigned-clock-rates = <800000000>; 2064 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 2065 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, 2066 <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; 2067 power-domain-names = "a", "b"; 2068 dma-coherent; 2069 }; 2070}; 2071