1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 pcie0_ctrl: pcie-ctrl@4070 { 55 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 56 reg = <0x4070 0x4>; 57 }; 58 59 serdes_ln_ctrl: mux-controller@4080 { 60 compatible = "reg-mux"; 61 reg = <0x4080 0x4>; 62 #mux-control-cells = <1>; 63 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ 64 }; 65 66 phy_gmii_sel: phy@4044 { 67 compatible = "ti,am654-phy-gmii-sel"; 68 reg = <0x4044 0x8>; 69 #phy-cells = <1>; 70 }; 71 72 epwm_tbclk: clock-controller@4130 { 73 compatible = "ti,am64-epwm-tbclk"; 74 reg = <0x4130 0x4>; 75 #clock-cells = <1>; 76 }; 77 }; 78 79 gic500: interrupt-controller@1800000 { 80 compatible = "arm,gic-v3"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 #interrupt-cells = <3>; 85 interrupt-controller; 86 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 87 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 88 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 89 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 90 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 91 /* 92 * vcpumntirq: 93 * virtual CPU interface maintenance interrupt 94 */ 95 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 96 97 gic_its: msi-controller@1820000 { 98 compatible = "arm,gic-v3-its"; 99 reg = <0x00 0x01820000 0x00 0x10000>; 100 socionext,synquacer-pre-its = <0x1000000 0x400000>; 101 msi-controller; 102 #msi-cells = <1>; 103 }; 104 }; 105 106 dmss: bus@48000000 { 107 bootph-all; 108 compatible = "simple-bus"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 dma-ranges; 112 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 113 114 ti,sci-dev-id = <25>; 115 116 secure_proxy_main: mailbox@4d000000 { 117 bootph-all; 118 compatible = "ti,am654-secure-proxy"; 119 #mbox-cells = <1>; 120 reg-names = "target_data", "rt", "scfg"; 121 reg = <0x00 0x4d000000 0x00 0x80000>, 122 <0x00 0x4a600000 0x00 0x80000>, 123 <0x00 0x4a400000 0x00 0x80000>; 124 interrupt-names = "rx_012"; 125 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 inta_main_dmss: interrupt-controller@48000000 { 129 compatible = "ti,sci-inta"; 130 reg = <0x00 0x48000000 0x00 0x100000>; 131 #interrupt-cells = <0>; 132 interrupt-controller; 133 interrupt-parent = <&gic500>; 134 msi-controller; 135 ti,sci = <&dmsc>; 136 ti,sci-dev-id = <28>; 137 ti,interrupt-ranges = <4 68 36>; 138 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 139 }; 140 141 main_bcdma: dma-controller@485c0100 { 142 compatible = "ti,am64-dmss-bcdma"; 143 reg = <0x00 0x485c0100 0x00 0x100>, 144 <0x00 0x4c000000 0x00 0x20000>, 145 <0x00 0x4a820000 0x00 0x20000>, 146 <0x00 0x4aa40000 0x00 0x20000>, 147 <0x00 0x4bc00000 0x00 0x100000>, 148 <0x00 0x48600000 0x00 0x8000>, 149 <0x00 0x484a4000 0x00 0x2000>, 150 <0x00 0x484c2000 0x00 0x2000>, 151 <0x00 0x48420000 0x00 0x2000>; 152 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 153 "ring", "tchan", "rchan", "bchan"; 154 msi-parent = <&inta_main_dmss>; 155 #dma-cells = <3>; 156 157 ti,sci = <&dmsc>; 158 ti,sci-dev-id = <26>; 159 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 160 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 161 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 162 }; 163 164 main_pktdma: dma-controller@485c0000 { 165 compatible = "ti,am64-dmss-pktdma"; 166 reg = <0x00 0x485c0000 0x00 0x100>, 167 <0x00 0x4a800000 0x00 0x20000>, 168 <0x00 0x4aa00000 0x00 0x40000>, 169 <0x00 0x4b800000 0x00 0x400000>, 170 <0x00 0x485e0000 0x00 0x20000>, 171 <0x00 0x484a0000 0x00 0x4000>, 172 <0x00 0x484c0000 0x00 0x2000>, 173 <0x00 0x48430000 0x00 0x4000>; 174 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 175 "ring", "tchan", "rchan", "rflow"; 176 msi-parent = <&inta_main_dmss>; 177 #dma-cells = <2>; 178 179 ti,sci = <&dmsc>; 180 ti,sci-dev-id = <30>; 181 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 182 <0x24>, /* CPSW_TX_CHAN */ 183 <0x25>, /* SAUL_TX_0_CHAN */ 184 <0x26>, /* SAUL_TX_1_CHAN */ 185 <0x27>, /* ICSSG_0_TX_CHAN */ 186 <0x28>; /* ICSSG_1_TX_CHAN */ 187 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 188 <0x11>, /* RING_CPSW_TX_CHAN */ 189 <0x12>, /* RING_SAUL_TX_0_CHAN */ 190 <0x13>, /* RING_SAUL_TX_1_CHAN */ 191 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 192 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 193 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 194 <0x2b>, /* CPSW_RX_CHAN */ 195 <0x2d>, /* SAUL_RX_0_CHAN */ 196 <0x2f>, /* SAUL_RX_1_CHAN */ 197 <0x31>, /* SAUL_RX_2_CHAN */ 198 <0x33>, /* SAUL_RX_3_CHAN */ 199 <0x35>, /* ICSSG_0_RX_CHAN */ 200 <0x37>; /* ICSSG_1_RX_CHAN */ 201 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 202 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 203 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 204 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 205 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 206 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 207 }; 208 }; 209 210 dmsc: system-controller@44043000 { 211 bootph-all; 212 compatible = "ti,k2g-sci"; 213 ti,host-id = <12>; 214 mbox-names = "rx", "tx"; 215 mboxes = <&secure_proxy_main 12>, 216 <&secure_proxy_main 13>; 217 reg-names = "debug_messages"; 218 reg = <0x00 0x44043000 0x00 0xfe0>; 219 220 k3_pds: power-controller { 221 bootph-all; 222 compatible = "ti,sci-pm-domain"; 223 #power-domain-cells = <2>; 224 }; 225 226 k3_clks: clock-controller { 227 bootph-all; 228 compatible = "ti,k2g-sci-clk"; 229 #clock-cells = <2>; 230 }; 231 232 k3_reset: reset-controller { 233 bootph-all; 234 compatible = "ti,sci-reset"; 235 #reset-cells = <2>; 236 }; 237 }; 238 239 main_pmx0: pinctrl@f4000 { 240 bootph-all; 241 compatible = "pinctrl-single"; 242 reg = <0x00 0xf4000 0x00 0x2d0>; 243 #pinctrl-cells = <1>; 244 pinctrl-single,register-width = <32>; 245 pinctrl-single,function-mask = <0xffffffff>; 246 }; 247 248 main_timer0: timer@2400000 { 249 bootph-all; 250 compatible = "ti,am654-timer"; 251 reg = <0x00 0x2400000 0x00 0x400>; 252 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&k3_clks 36 1>; 254 clock-names = "fck"; 255 assigned-clocks = <&k3_clks 36 1>; 256 assigned-clock-parents = <&k3_clks 36 2>; 257 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 258 ti,timer-pwm; 259 }; 260 261 main_timer1: timer@2410000 { 262 compatible = "ti,am654-timer"; 263 reg = <0x00 0x2410000 0x00 0x400>; 264 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&k3_clks 37 1>; 266 clock-names = "fck"; 267 assigned-clocks = <&k3_clks 37 1>; 268 assigned-clock-parents = <&k3_clks 37 2>; 269 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 270 ti,timer-pwm; 271 }; 272 273 main_timer2: timer@2420000 { 274 compatible = "ti,am654-timer"; 275 reg = <0x00 0x2420000 0x00 0x400>; 276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&k3_clks 38 1>; 278 clock-names = "fck"; 279 assigned-clocks = <&k3_clks 38 1>; 280 assigned-clock-parents = <&k3_clks 38 2>; 281 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 282 ti,timer-pwm; 283 }; 284 285 main_timer3: timer@2430000 { 286 compatible = "ti,am654-timer"; 287 reg = <0x00 0x2430000 0x00 0x400>; 288 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&k3_clks 39 1>; 290 clock-names = "fck"; 291 assigned-clocks = <&k3_clks 39 1>; 292 assigned-clock-parents = <&k3_clks 39 2>; 293 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 294 ti,timer-pwm; 295 }; 296 297 main_timer4: timer@2440000 { 298 compatible = "ti,am654-timer"; 299 reg = <0x00 0x2440000 0x00 0x400>; 300 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&k3_clks 40 1>; 302 clock-names = "fck"; 303 assigned-clocks = <&k3_clks 40 1>; 304 assigned-clock-parents = <&k3_clks 40 2>; 305 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 306 ti,timer-pwm; 307 }; 308 309 main_timer5: timer@2450000 { 310 compatible = "ti,am654-timer"; 311 reg = <0x00 0x2450000 0x00 0x400>; 312 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&k3_clks 41 1>; 314 clock-names = "fck"; 315 assigned-clocks = <&k3_clks 41 1>; 316 assigned-clock-parents = <&k3_clks 41 2>; 317 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 318 ti,timer-pwm; 319 }; 320 321 main_timer6: timer@2460000 { 322 compatible = "ti,am654-timer"; 323 reg = <0x00 0x2460000 0x00 0x400>; 324 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&k3_clks 42 1>; 326 clock-names = "fck"; 327 assigned-clocks = <&k3_clks 42 1>; 328 assigned-clock-parents = <&k3_clks 42 2>; 329 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 330 ti,timer-pwm; 331 }; 332 333 main_timer7: timer@2470000 { 334 compatible = "ti,am654-timer"; 335 reg = <0x00 0x2470000 0x00 0x400>; 336 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&k3_clks 43 1>; 338 clock-names = "fck"; 339 assigned-clocks = <&k3_clks 43 1>; 340 assigned-clock-parents = <&k3_clks 43 2>; 341 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 342 ti,timer-pwm; 343 }; 344 345 main_timer8: timer@2480000 { 346 compatible = "ti,am654-timer"; 347 reg = <0x00 0x2480000 0x00 0x400>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&k3_clks 44 1>; 350 clock-names = "fck"; 351 assigned-clocks = <&k3_clks 44 1>; 352 assigned-clock-parents = <&k3_clks 44 2>; 353 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 354 ti,timer-pwm; 355 }; 356 357 main_timer9: timer@2490000 { 358 compatible = "ti,am654-timer"; 359 reg = <0x00 0x2490000 0x00 0x400>; 360 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&k3_clks 45 1>; 362 clock-names = "fck"; 363 assigned-clocks = <&k3_clks 45 1>; 364 assigned-clock-parents = <&k3_clks 45 2>; 365 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 366 ti,timer-pwm; 367 }; 368 369 main_timer10: timer@24a0000 { 370 compatible = "ti,am654-timer"; 371 reg = <0x00 0x24a0000 0x00 0x400>; 372 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&k3_clks 46 1>; 374 clock-names = "fck"; 375 assigned-clocks = <&k3_clks 46 1>; 376 assigned-clock-parents = <&k3_clks 46 2>; 377 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 378 ti,timer-pwm; 379 }; 380 381 main_timer11: timer@24b0000 { 382 compatible = "ti,am654-timer"; 383 reg = <0x00 0x24b0000 0x00 0x400>; 384 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&k3_clks 47 1>; 386 clock-names = "fck"; 387 assigned-clocks = <&k3_clks 47 1>; 388 assigned-clock-parents = <&k3_clks 47 2>; 389 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 390 ti,timer-pwm; 391 }; 392 393 main_esm: esm@420000 { 394 bootph-pre-ram; 395 compatible = "ti,j721e-esm"; 396 reg = <0x00 0x420000 0x00 0x1000>; 397 /* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */ 398 ti,esm-pins = <160>, <161>, <162>, <163>, <164>, <165>; 399 }; 400 401 main_uart0: serial@2800000 { 402 compatible = "ti,am64-uart", "ti,am654-uart"; 403 reg = <0x00 0x02800000 0x00 0x100>; 404 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 405 clock-frequency = <48000000>; 406 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 146 0>; 408 clock-names = "fclk"; 409 status = "disabled"; 410 }; 411 412 main_uart1: serial@2810000 { 413 compatible = "ti,am64-uart", "ti,am654-uart"; 414 reg = <0x00 0x02810000 0x00 0x100>; 415 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 416 clock-frequency = <48000000>; 417 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 152 0>; 419 clock-names = "fclk"; 420 status = "disabled"; 421 }; 422 423 main_uart2: serial@2820000 { 424 compatible = "ti,am64-uart", "ti,am654-uart"; 425 reg = <0x00 0x02820000 0x00 0x100>; 426 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 427 clock-frequency = <48000000>; 428 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 153 0>; 430 clock-names = "fclk"; 431 status = "disabled"; 432 }; 433 434 main_uart3: serial@2830000 { 435 compatible = "ti,am64-uart", "ti,am654-uart"; 436 reg = <0x00 0x02830000 0x00 0x100>; 437 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 438 clock-frequency = <48000000>; 439 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 154 0>; 441 clock-names = "fclk"; 442 status = "disabled"; 443 }; 444 445 main_uart4: serial@2840000 { 446 compatible = "ti,am64-uart", "ti,am654-uart"; 447 reg = <0x00 0x02840000 0x00 0x100>; 448 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 449 clock-frequency = <48000000>; 450 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 155 0>; 452 clock-names = "fclk"; 453 status = "disabled"; 454 }; 455 456 main_uart5: serial@2850000 { 457 compatible = "ti,am64-uart", "ti,am654-uart"; 458 reg = <0x00 0x02850000 0x00 0x100>; 459 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 460 clock-frequency = <48000000>; 461 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 462 clocks = <&k3_clks 156 0>; 463 clock-names = "fclk"; 464 status = "disabled"; 465 }; 466 467 main_uart6: serial@2860000 { 468 compatible = "ti,am64-uart", "ti,am654-uart"; 469 reg = <0x00 0x02860000 0x00 0x100>; 470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 471 clock-frequency = <48000000>; 472 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 473 clocks = <&k3_clks 158 0>; 474 clock-names = "fclk"; 475 status = "disabled"; 476 }; 477 478 main_i2c0: i2c@20000000 { 479 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 480 reg = <0x00 0x20000000 0x00 0x100>; 481 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 485 clocks = <&k3_clks 102 2>; 486 clock-names = "fck"; 487 status = "disabled"; 488 }; 489 490 main_i2c1: i2c@20010000 { 491 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 492 reg = <0x00 0x20010000 0x00 0x100>; 493 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 497 clocks = <&k3_clks 103 2>; 498 clock-names = "fck"; 499 status = "disabled"; 500 }; 501 502 main_i2c2: i2c@20020000 { 503 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 504 reg = <0x00 0x20020000 0x00 0x100>; 505 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 509 clocks = <&k3_clks 104 2>; 510 clock-names = "fck"; 511 status = "disabled"; 512 }; 513 514 main_i2c3: i2c@20030000 { 515 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 516 reg = <0x00 0x20030000 0x00 0x100>; 517 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 521 clocks = <&k3_clks 105 2>; 522 clock-names = "fck"; 523 status = "disabled"; 524 }; 525 526 main_spi0: spi@20100000 { 527 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 528 reg = <0x00 0x20100000 0x00 0x400>; 529 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 533 clocks = <&k3_clks 141 0>; 534 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 535 dma-names = "tx0", "rx0"; 536 status = "disabled"; 537 }; 538 539 main_spi1: spi@20110000 { 540 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 541 reg = <0x00 0x20110000 0x00 0x400>; 542 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 546 clocks = <&k3_clks 142 0>; 547 status = "disabled"; 548 }; 549 550 main_spi2: spi@20120000 { 551 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 552 reg = <0x00 0x20120000 0x00 0x400>; 553 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 557 clocks = <&k3_clks 143 0>; 558 status = "disabled"; 559 }; 560 561 main_spi3: spi@20130000 { 562 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 563 reg = <0x00 0x20130000 0x00 0x400>; 564 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 568 clocks = <&k3_clks 144 0>; 569 status = "disabled"; 570 }; 571 572 main_spi4: spi@20140000 { 573 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 574 reg = <0x00 0x20140000 0x00 0x400>; 575 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 579 clocks = <&k3_clks 145 0>; 580 status = "disabled"; 581 }; 582 583 main_gpio_intr: interrupt-controller@a00000 { 584 compatible = "ti,sci-intr"; 585 reg = <0x00 0x00a00000 0x00 0x800>; 586 ti,intr-trigger-type = <1>; 587 interrupt-controller; 588 interrupt-parent = <&gic500>; 589 #interrupt-cells = <1>; 590 ti,sci = <&dmsc>; 591 ti,sci-dev-id = <3>; 592 ti,interrupt-ranges = <0 32 16>; 593 }; 594 595 main_gpio0: gpio@600000 { 596 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 597 reg = <0x0 0x00600000 0x0 0x100>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupt-parent = <&main_gpio_intr>; 601 interrupts = <190>, <191>, <192>, 602 <193>, <194>, <195>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 ti,ngpio = <87>; 606 ti,davinci-gpio-unbanked = <0>; 607 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 608 clocks = <&k3_clks 77 0>; 609 clock-names = "gpio"; 610 }; 611 612 main_gpio1: gpio@601000 { 613 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 614 reg = <0x0 0x00601000 0x0 0x100>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 interrupt-parent = <&main_gpio_intr>; 618 interrupts = <180>, <181>, <182>, 619 <183>, <184>, <185>; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 ti,ngpio = <88>; 623 ti,davinci-gpio-unbanked = <0>; 624 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 625 clocks = <&k3_clks 78 0>; 626 clock-names = "gpio"; 627 }; 628 629 sdhci0: mmc@fa10000 { 630 compatible = "ti,am64-sdhci-8bit"; 631 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 632 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 633 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 634 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 635 clock-names = "clk_ahb", "clk_xin"; 636 bus-width = <8>; 637 mmc-ddr-1_8v; 638 mmc-hs200-1_8v; 639 ti,clkbuf-sel = <0x7>; 640 ti,trm-icp = <0x2>; 641 ti,otap-del-sel-legacy = <0x0>; 642 ti,otap-del-sel-mmc-hs = <0x0>; 643 ti,otap-del-sel-ddr52 = <0x6>; 644 ti,otap-del-sel-hs200 = <0x7>; 645 ti,itap-del-sel-legacy = <0x10>; 646 ti,itap-del-sel-mmc-hs = <0xa>; 647 ti,itap-del-sel-ddr52 = <0x3>; 648 status = "disabled"; 649 }; 650 651 sdhci1: mmc@fa00000 { 652 compatible = "ti,am64-sdhci-4bit"; 653 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 654 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 655 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 656 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 657 clock-names = "clk_ahb", "clk_xin"; 658 bus-width = <4>; 659 ti,clkbuf-sel = <0x7>; 660 ti,otap-del-sel-legacy = <0x0>; 661 ti,otap-del-sel-sd-hs = <0x0>; 662 ti,otap-del-sel-sdr12 = <0xf>; 663 ti,otap-del-sel-sdr25 = <0xf>; 664 ti,otap-del-sel-sdr50 = <0xc>; 665 ti,otap-del-sel-sdr104 = <0x6>; 666 ti,otap-del-sel-ddr50 = <0x9>; 667 ti,itap-del-sel-legacy = <0x0>; 668 ti,itap-del-sel-sd-hs = <0x0>; 669 ti,itap-del-sel-sdr12 = <0x0>; 670 ti,itap-del-sel-sdr25 = <0x0>; 671 status = "disabled"; 672 }; 673 674 cpsw3g: ethernet@8000000 { 675 compatible = "ti,am642-cpsw-nuss"; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 reg = <0x0 0x8000000 0x0 0x200000>; 679 reg-names = "cpsw_nuss"; 680 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 681 clocks = <&k3_clks 13 0>; 682 assigned-clocks = <&k3_clks 13 1>; 683 assigned-clock-parents = <&k3_clks 13 9>; 684 clock-names = "fck"; 685 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 686 status = "disabled"; 687 688 dmas = <&main_pktdma 0xC500 15>, 689 <&main_pktdma 0xC501 15>, 690 <&main_pktdma 0xC502 15>, 691 <&main_pktdma 0xC503 15>, 692 <&main_pktdma 0xC504 15>, 693 <&main_pktdma 0xC505 15>, 694 <&main_pktdma 0xC506 15>, 695 <&main_pktdma 0xC507 15>, 696 <&main_pktdma 0x4500 15>; 697 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 698 "tx7", "rx"; 699 700 ethernet-ports { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 704 cpsw_port1: port@1 { 705 reg = <1>; 706 ti,mac-only; 707 label = "port1"; 708 phys = <&phy_gmii_sel 1>; 709 mac-address = [00 00 00 00 00 00]; 710 ti,syscon-efuse = <&main_conf 0x200>; 711 status = "disabled"; 712 }; 713 714 cpsw_port2: port@2 { 715 reg = <2>; 716 ti,mac-only; 717 label = "port2"; 718 phys = <&phy_gmii_sel 2>; 719 mac-address = [00 00 00 00 00 00]; 720 status = "disabled"; 721 }; 722 }; 723 724 cpsw3g_mdio: mdio@f00 { 725 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 726 reg = <0x0 0xf00 0x0 0x100>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&k3_clks 13 0>; 730 clock-names = "fck"; 731 bus_freq = <1000000>; 732 status = "disabled"; 733 }; 734 735 cpts@3d000 { 736 compatible = "ti,j721e-cpts"; 737 reg = <0x0 0x3d000 0x0 0x400>; 738 clocks = <&k3_clks 13 1>; 739 clock-names = "cpts"; 740 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 741 interrupt-names = "cpts"; 742 ti,cpts-ext-ts-inputs = <4>; 743 ti,cpts-periodic-outputs = <2>; 744 }; 745 }; 746 747 main_cpts0: cpts@39000000 { 748 compatible = "ti,j721e-cpts"; 749 reg = <0x0 0x39000000 0x0 0x400>; 750 reg-names = "cpts"; 751 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 752 clocks = <&k3_clks 84 0>; 753 clock-names = "cpts"; 754 assigned-clocks = <&k3_clks 84 0>; 755 assigned-clock-parents = <&k3_clks 84 8>; 756 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-names = "cpts"; 758 ti,cpts-periodic-outputs = <6>; 759 ti,cpts-ext-ts-inputs = <8>; 760 }; 761 762 timesync_router: pinctrl@a40000 { 763 compatible = "pinctrl-single"; 764 reg = <0x0 0xa40000 0x0 0x800>; 765 #pinctrl-cells = <1>; 766 pinctrl-single,register-width = <32>; 767 pinctrl-single,function-mask = <0x000107ff>; 768 }; 769 770 usbss0: cdns-usb@f900000 { 771 compatible = "ti,am64-usb", "ti,j721e-usb"; 772 reg = <0x00 0xf900000 0x00 0x100>; 773 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 775 clock-names = "ref", "lpm"; 776 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 777 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges; 781 usb0: usb@f400000 { 782 compatible = "cdns,usb3"; 783 reg = <0x00 0xf400000 0x00 0x10000>, 784 <0x00 0xf410000 0x00 0x10000>, 785 <0x00 0xf420000 0x00 0x10000>; 786 reg-names = "otg", 787 "xhci", 788 "dev"; 789 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 790 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 791 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 792 interrupt-names = "host", 793 "peripheral", 794 "otg"; 795 maximum-speed = "super-speed"; 796 dr_mode = "otg"; 797 }; 798 }; 799 800 tscadc0: tscadc@28001000 { 801 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 802 reg = <0x00 0x28001000 0x00 0x1000>; 803 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 804 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 0 0>; 806 assigned-clocks = <&k3_clks 0 0>; 807 assigned-clock-parents = <&k3_clks 0 3>; 808 assigned-clock-rates = <60000000>; 809 clock-names = "fck"; 810 status = "disabled"; 811 812 adc { 813 #io-channel-cells = <1>; 814 compatible = "ti,am654-adc", "ti,am3359-adc"; 815 }; 816 }; 817 818 fss: bus@fc00000 { 819 compatible = "simple-bus"; 820 reg = <0x00 0x0fc00000 0x00 0x70000>; 821 #address-cells = <2>; 822 #size-cells = <2>; 823 ranges; 824 825 ospi0: spi@fc40000 { 826 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 827 reg = <0x00 0x0fc40000 0x00 0x100>, 828 <0x05 0x00000000 0x01 0x00000000>; 829 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 830 cdns,fifo-depth = <256>; 831 cdns,fifo-width = <4>; 832 cdns,trigger-address = <0x0>; 833 #address-cells = <0x1>; 834 #size-cells = <0x0>; 835 clocks = <&k3_clks 75 6>; 836 assigned-clocks = <&k3_clks 75 6>; 837 assigned-clock-parents = <&k3_clks 75 7>; 838 assigned-clock-rates = <166666666>; 839 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 840 status = "disabled"; 841 }; 842 }; 843 844 hwspinlock: spinlock@2a000000 { 845 compatible = "ti,am64-hwspinlock"; 846 reg = <0x00 0x2a000000 0x00 0x1000>; 847 #hwlock-cells = <1>; 848 }; 849 850 mailbox0_cluster2: mailbox@29020000 { 851 compatible = "ti,am64-mailbox"; 852 reg = <0x00 0x29020000 0x00 0x200>; 853 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 855 #mbox-cells = <1>; 856 ti,mbox-num-users = <4>; 857 ti,mbox-num-fifos = <16>; 858 status = "disabled"; 859 }; 860 861 mailbox0_cluster3: mailbox@29030000 { 862 compatible = "ti,am64-mailbox"; 863 reg = <0x00 0x29030000 0x00 0x200>; 864 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 866 #mbox-cells = <1>; 867 ti,mbox-num-users = <4>; 868 ti,mbox-num-fifos = <16>; 869 status = "disabled"; 870 }; 871 872 mailbox0_cluster4: mailbox@29040000 { 873 compatible = "ti,am64-mailbox"; 874 reg = <0x00 0x29040000 0x00 0x200>; 875 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 877 #mbox-cells = <1>; 878 ti,mbox-num-users = <4>; 879 ti,mbox-num-fifos = <16>; 880 status = "disabled"; 881 }; 882 883 mailbox0_cluster5: mailbox@29050000 { 884 compatible = "ti,am64-mailbox"; 885 reg = <0x00 0x29050000 0x00 0x200>; 886 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 888 #mbox-cells = <1>; 889 ti,mbox-num-users = <4>; 890 ti,mbox-num-fifos = <16>; 891 status = "disabled"; 892 }; 893 894 mailbox0_cluster6: mailbox@29060000 { 895 compatible = "ti,am64-mailbox"; 896 reg = <0x00 0x29060000 0x00 0x200>; 897 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 898 #mbox-cells = <1>; 899 ti,mbox-num-users = <4>; 900 ti,mbox-num-fifos = <16>; 901 status = "disabled"; 902 }; 903 904 mailbox0_cluster7: mailbox@29070000 { 905 compatible = "ti,am64-mailbox"; 906 reg = <0x00 0x29070000 0x00 0x200>; 907 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 908 #mbox-cells = <1>; 909 ti,mbox-num-users = <4>; 910 ti,mbox-num-fifos = <16>; 911 status = "disabled"; 912 }; 913 914 main_r5fss0: r5fss@78000000 { 915 compatible = "ti,am64-r5fss"; 916 ti,cluster-mode = <0>; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges = <0x78000000 0x00 0x78000000 0x10000>, 920 <0x78100000 0x00 0x78100000 0x10000>, 921 <0x78200000 0x00 0x78200000 0x08000>, 922 <0x78300000 0x00 0x78300000 0x08000>; 923 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 924 925 main_r5fss0_core0: r5f@78000000 { 926 compatible = "ti,am64-r5f"; 927 reg = <0x78000000 0x00010000>, 928 <0x78100000 0x00010000>; 929 reg-names = "atcm", "btcm"; 930 ti,sci = <&dmsc>; 931 ti,sci-dev-id = <121>; 932 ti,sci-proc-ids = <0x01 0xff>; 933 resets = <&k3_reset 121 1>; 934 firmware-name = "am64-main-r5f0_0-fw"; 935 ti,atcm-enable = <1>; 936 ti,btcm-enable = <1>; 937 ti,loczrama = <1>; 938 }; 939 940 main_r5fss0_core1: r5f@78200000 { 941 compatible = "ti,am64-r5f"; 942 reg = <0x78200000 0x00008000>, 943 <0x78300000 0x00008000>; 944 reg-names = "atcm", "btcm"; 945 ti,sci = <&dmsc>; 946 ti,sci-dev-id = <122>; 947 ti,sci-proc-ids = <0x02 0xff>; 948 resets = <&k3_reset 122 1>; 949 firmware-name = "am64-main-r5f0_1-fw"; 950 ti,atcm-enable = <1>; 951 ti,btcm-enable = <1>; 952 ti,loczrama = <1>; 953 }; 954 }; 955 956 main_r5fss1: r5fss@78400000 { 957 compatible = "ti,am64-r5fss"; 958 ti,cluster-mode = <0>; 959 #address-cells = <1>; 960 #size-cells = <1>; 961 ranges = <0x78400000 0x00 0x78400000 0x10000>, 962 <0x78500000 0x00 0x78500000 0x10000>, 963 <0x78600000 0x00 0x78600000 0x08000>, 964 <0x78700000 0x00 0x78700000 0x08000>; 965 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 966 967 main_r5fss1_core0: r5f@78400000 { 968 compatible = "ti,am64-r5f"; 969 reg = <0x78400000 0x00010000>, 970 <0x78500000 0x00010000>; 971 reg-names = "atcm", "btcm"; 972 ti,sci = <&dmsc>; 973 ti,sci-dev-id = <123>; 974 ti,sci-proc-ids = <0x06 0xff>; 975 resets = <&k3_reset 123 1>; 976 firmware-name = "am64-main-r5f1_0-fw"; 977 ti,atcm-enable = <1>; 978 ti,btcm-enable = <1>; 979 ti,loczrama = <1>; 980 }; 981 982 main_r5fss1_core1: r5f@78600000 { 983 compatible = "ti,am64-r5f"; 984 reg = <0x78600000 0x00008000>, 985 <0x78700000 0x00008000>; 986 reg-names = "atcm", "btcm"; 987 ti,sci = <&dmsc>; 988 ti,sci-dev-id = <124>; 989 ti,sci-proc-ids = <0x07 0xff>; 990 resets = <&k3_reset 124 1>; 991 firmware-name = "am64-main-r5f1_1-fw"; 992 ti,atcm-enable = <1>; 993 ti,btcm-enable = <1>; 994 ti,loczrama = <1>; 995 }; 996 }; 997 998 serdes_wiz0: wiz@f000000 { 999 compatible = "ti,am64-wiz-10g"; 1000 #address-cells = <1>; 1001 #size-cells = <1>; 1002 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 1003 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 1004 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1005 num-lanes = <1>; 1006 #reset-cells = <1>; 1007 #clock-cells = <1>; 1008 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 1009 1010 assigned-clocks = <&k3_clks 162 1>; 1011 assigned-clock-parents = <&k3_clks 162 5>; 1012 1013 serdes0: serdes@f000000 { 1014 compatible = "ti,j721e-serdes-10g"; 1015 reg = <0x0f000000 0x00010000>; 1016 reg-names = "torrent_phy"; 1017 resets = <&serdes_wiz0 0>; 1018 reset-names = "torrent_reset"; 1019 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1020 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1021 clock-names = "refclk", "phy_en_refclk"; 1022 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1023 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1024 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1025 assigned-clock-parents = <&k3_clks 162 1>, 1026 <&k3_clks 162 1>, 1027 <&k3_clks 162 1>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 #clock-cells = <1>; 1031 }; 1032 }; 1033 1034 pcie0_rc: pcie@f102000 { 1035 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1036 reg = <0x00 0x0f102000 0x00 0x1000>, 1037 <0x00 0x0f100000 0x00 0x400>, 1038 <0x00 0x0d000000 0x00 0x00800000>, 1039 <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1040 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1041 interrupt-names = "link_state"; 1042 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1043 device_type = "pci"; 1044 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1045 max-link-speed = <2>; 1046 num-lanes = <1>; 1047 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1048 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1049 clock-names = "fck", "pcie_refclk"; 1050 #address-cells = <3>; 1051 #size-cells = <2>; 1052 bus-range = <0x0 0xff>; 1053 cdns,no-bar-match-nbits = <64>; 1054 vendor-id = <0x104c>; 1055 device-id = <0xb010>; 1056 msi-map = <0x0 &gic_its 0x0 0x10000>; 1057 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1058 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1059 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1060 status = "disabled"; 1061 }; 1062 1063 epwm0: pwm@23000000 { 1064 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1065 #pwm-cells = <3>; 1066 reg = <0x0 0x23000000 0x0 0x100>; 1067 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1068 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1069 clock-names = "tbclk", "fck"; 1070 status = "disabled"; 1071 }; 1072 1073 epwm1: pwm@23010000 { 1074 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1075 #pwm-cells = <3>; 1076 reg = <0x0 0x23010000 0x0 0x100>; 1077 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1078 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1079 clock-names = "tbclk", "fck"; 1080 status = "disabled"; 1081 }; 1082 1083 epwm2: pwm@23020000 { 1084 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1085 #pwm-cells = <3>; 1086 reg = <0x0 0x23020000 0x0 0x100>; 1087 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1088 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1089 clock-names = "tbclk", "fck"; 1090 status = "disabled"; 1091 }; 1092 1093 epwm3: pwm@23030000 { 1094 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1095 #pwm-cells = <3>; 1096 reg = <0x0 0x23030000 0x0 0x100>; 1097 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1098 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1099 clock-names = "tbclk", "fck"; 1100 status = "disabled"; 1101 }; 1102 1103 epwm4: pwm@23040000 { 1104 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1105 #pwm-cells = <3>; 1106 reg = <0x0 0x23040000 0x0 0x100>; 1107 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1108 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1109 clock-names = "tbclk", "fck"; 1110 status = "disabled"; 1111 }; 1112 1113 epwm5: pwm@23050000 { 1114 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1115 #pwm-cells = <3>; 1116 reg = <0x0 0x23050000 0x0 0x100>; 1117 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1118 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1119 clock-names = "tbclk", "fck"; 1120 status = "disabled"; 1121 }; 1122 1123 epwm6: pwm@23060000 { 1124 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1125 #pwm-cells = <3>; 1126 reg = <0x0 0x23060000 0x0 0x100>; 1127 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1128 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1129 clock-names = "tbclk", "fck"; 1130 status = "disabled"; 1131 }; 1132 1133 epwm7: pwm@23070000 { 1134 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1135 #pwm-cells = <3>; 1136 reg = <0x0 0x23070000 0x0 0x100>; 1137 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1138 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1139 clock-names = "tbclk", "fck"; 1140 status = "disabled"; 1141 }; 1142 1143 epwm8: pwm@23080000 { 1144 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1145 #pwm-cells = <3>; 1146 reg = <0x0 0x23080000 0x0 0x100>; 1147 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1148 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1149 clock-names = "tbclk", "fck"; 1150 status = "disabled"; 1151 }; 1152 1153 ecap0: pwm@23100000 { 1154 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1155 #pwm-cells = <3>; 1156 reg = <0x0 0x23100000 0x0 0x60>; 1157 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1158 clocks = <&k3_clks 51 0>; 1159 clock-names = "fck"; 1160 status = "disabled"; 1161 }; 1162 1163 ecap1: pwm@23110000 { 1164 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1165 #pwm-cells = <3>; 1166 reg = <0x0 0x23110000 0x0 0x60>; 1167 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1168 clocks = <&k3_clks 52 0>; 1169 clock-names = "fck"; 1170 status = "disabled"; 1171 }; 1172 1173 ecap2: pwm@23120000 { 1174 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1175 #pwm-cells = <3>; 1176 reg = <0x0 0x23120000 0x0 0x60>; 1177 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1178 clocks = <&k3_clks 53 0>; 1179 clock-names = "fck"; 1180 status = "disabled"; 1181 }; 1182 1183 eqep0: counter@23200000 { 1184 compatible = "ti,am62-eqep"; 1185 reg = <0x00 0x23200000 0x00 0x100>; 1186 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1187 clocks = <&k3_clks 59 0>; 1188 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 1189 status = "disabled"; 1190 }; 1191 1192 eqep1: counter@23210000 { 1193 compatible = "ti,am62-eqep"; 1194 reg = <0x00 0x23210000 0x00 0x100>; 1195 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1196 clocks = <&k3_clks 60 0>; 1197 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 1198 status = "disabled"; 1199 }; 1200 1201 eqep2: counter@23220000 { 1202 compatible = "ti,am62-eqep"; 1203 reg = <0x00 0x23220000 0x00 0x100>; 1204 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1205 clocks = <&k3_clks 62 0>; 1206 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 1207 status = "disabled"; 1208 }; 1209 1210 main_rti0: watchdog@e000000 { 1211 compatible = "ti,j7-rti-wdt"; 1212 reg = <0x00 0xe000000 0x00 0x100>; 1213 clocks = <&k3_clks 125 0>; 1214 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1215 assigned-clocks = <&k3_clks 125 0>; 1216 assigned-clock-parents = <&k3_clks 125 2>; 1217 }; 1218 1219 main_rti1: watchdog@e010000 { 1220 compatible = "ti,j7-rti-wdt"; 1221 reg = <0x00 0xe010000 0x00 0x100>; 1222 clocks = <&k3_clks 126 0>; 1223 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1224 assigned-clocks = <&k3_clks 126 0>; 1225 assigned-clock-parents = <&k3_clks 126 2>; 1226 }; 1227 1228 icssg0: icssg@30000000 { 1229 compatible = "ti,am642-icssg"; 1230 reg = <0x00 0x30000000 0x00 0x80000>; 1231 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1232 #address-cells = <1>; 1233 #size-cells = <1>; 1234 ranges = <0x0 0x00 0x30000000 0x80000>; 1235 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1236 <&k3_clks 81 3>, /* icssg0_iep_clk */ 1237 <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ 1238 <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ 1239 <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ 1240 <&k3_clks 81 19>, /* icssg0_uart_clk */ 1241 <&k3_clks 81 20>; /* icssg0_iclk */ 1242 assigned-clocks = <&k3_clks 81 0>; 1243 assigned-clock-parents = <&k3_clks 81 2>; 1244 1245 icssg0_mem: memories@0 { 1246 reg = <0x0 0x2000>, 1247 <0x2000 0x2000>, 1248 <0x10000 0x10000>; 1249 reg-names = "dram0", "dram1", "shrdram2"; 1250 }; 1251 1252 icssg0_cfg: cfg@26000 { 1253 compatible = "ti,pruss-cfg", "syscon"; 1254 reg = <0x26000 0x200>; 1255 #address-cells = <1>; 1256 #size-cells = <1>; 1257 ranges = <0x0 0x26000 0x2000>; 1258 1259 clocks { 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 1263 icssg0_coreclk_mux: coreclk-mux@3c { 1264 reg = <0x3c>; 1265 #clock-cells = <0>; 1266 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1267 <&k3_clks 81 20>; /* icssg0_iclk */ 1268 assigned-clocks = <&icssg0_coreclk_mux>; 1269 assigned-clock-parents = <&k3_clks 81 0>; 1270 }; 1271 1272 icssg0_iepclk_mux: iepclk-mux@30 { 1273 reg = <0x30>; 1274 #clock-cells = <0>; 1275 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1276 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1277 assigned-clocks = <&icssg0_iepclk_mux>; 1278 assigned-clock-parents = <&icssg0_coreclk_mux>; 1279 }; 1280 }; 1281 }; 1282 1283 icssg0_iep0: iep@2e000 { 1284 compatible = "ti,am654-icss-iep"; 1285 reg = <0x2e000 0x1000>; 1286 clocks = <&icssg0_iepclk_mux>; 1287 }; 1288 1289 icssg0_iep1: iep@2f000 { 1290 compatible = "ti,am654-icss-iep"; 1291 reg = <0x2f000 0x1000>; 1292 clocks = <&icssg0_iepclk_mux>; 1293 }; 1294 1295 icssg0_mii_rt: mii-rt@32000 { 1296 compatible = "ti,pruss-mii", "syscon"; 1297 reg = <0x32000 0x100>; 1298 }; 1299 1300 icssg0_mii_g_rt: mii-g-rt@33000 { 1301 compatible = "ti,pruss-mii-g", "syscon"; 1302 reg = <0x33000 0x1000>; 1303 }; 1304 1305 icssg0_pa_stats: pa-stats@2c000 { 1306 compatible = "ti,pruss-pa-st", "syscon"; 1307 reg = <0x2c000 0x1000>; 1308 }; 1309 1310 icssg0_intc: interrupt-controller@20000 { 1311 compatible = "ti,icssg-intc"; 1312 reg = <0x20000 0x2000>; 1313 interrupt-controller; 1314 #interrupt-cells = <3>; 1315 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1323 interrupt-names = "host_intr0", "host_intr1", 1324 "host_intr2", "host_intr3", 1325 "host_intr4", "host_intr5", 1326 "host_intr6", "host_intr7"; 1327 }; 1328 1329 pru0_0: pru@34000 { 1330 compatible = "ti,am642-pru"; 1331 reg = <0x34000 0x3000>, 1332 <0x22000 0x100>, 1333 <0x22400 0x100>; 1334 reg-names = "iram", "control", "debug"; 1335 firmware-name = "am64x-pru0_0-fw"; 1336 interrupt-parent = <&icssg0_intc>; 1337 interrupts = <16 2 2>; 1338 interrupt-names = "vring"; 1339 }; 1340 1341 rtu0_0: rtu@4000 { 1342 compatible = "ti,am642-rtu"; 1343 reg = <0x4000 0x2000>, 1344 <0x23000 0x100>, 1345 <0x23400 0x100>; 1346 reg-names = "iram", "control", "debug"; 1347 firmware-name = "am64x-rtu0_0-fw"; 1348 interrupt-parent = <&icssg0_intc>; 1349 interrupts = <20 4 4>; 1350 interrupt-names = "vring"; 1351 }; 1352 1353 tx_pru0_0: txpru@a000 { 1354 compatible = "ti,am642-tx-pru"; 1355 reg = <0xa000 0x1800>, 1356 <0x25000 0x100>, 1357 <0x25400 0x100>; 1358 reg-names = "iram", "control", "debug"; 1359 firmware-name = "am64x-txpru0_0-fw"; 1360 }; 1361 1362 pru0_1: pru@38000 { 1363 compatible = "ti,am642-pru"; 1364 reg = <0x38000 0x3000>, 1365 <0x24000 0x100>, 1366 <0x24400 0x100>; 1367 reg-names = "iram", "control", "debug"; 1368 firmware-name = "am64x-pru0_1-fw"; 1369 interrupt-parent = <&icssg0_intc>; 1370 interrupts = <18 3 3>; 1371 interrupt-names = "vring"; 1372 }; 1373 1374 rtu0_1: rtu@6000 { 1375 compatible = "ti,am642-rtu"; 1376 reg = <0x6000 0x2000>, 1377 <0x23800 0x100>, 1378 <0x23c00 0x100>; 1379 reg-names = "iram", "control", "debug"; 1380 firmware-name = "am64x-rtu0_1-fw"; 1381 interrupt-parent = <&icssg0_intc>; 1382 interrupts = <22 5 5>; 1383 interrupt-names = "vring"; 1384 }; 1385 1386 tx_pru0_1: txpru@c000 { 1387 compatible = "ti,am642-tx-pru"; 1388 reg = <0xc000 0x1800>, 1389 <0x25800 0x100>, 1390 <0x25c00 0x100>; 1391 reg-names = "iram", "control", "debug"; 1392 firmware-name = "am64x-txpru0_1-fw"; 1393 }; 1394 1395 icssg0_mdio: mdio@32400 { 1396 compatible = "ti,davinci_mdio"; 1397 reg = <0x32400 0x100>; 1398 clocks = <&k3_clks 62 3>; 1399 clock-names = "fck"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 bus_freq = <1000000>; 1403 status = "disabled"; 1404 }; 1405 }; 1406 1407 icssg1: icssg@30080000 { 1408 compatible = "ti,am642-icssg"; 1409 reg = <0x00 0x30080000 0x00 0x80000>; 1410 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1411 #address-cells = <1>; 1412 #size-cells = <1>; 1413 ranges = <0x0 0x00 0x30080000 0x80000>; 1414 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1415 <&k3_clks 82 3>, /* icssg1_iep_clk */ 1416 <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ 1417 <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ 1418 <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ 1419 <&k3_clks 82 19>, /* icssg1_uart_clk */ 1420 <&k3_clks 82 20>; /* icssg1_iclk */ 1421 assigned-clocks = <&k3_clks 82 0>; 1422 assigned-clock-parents = <&k3_clks 82 2>; 1423 1424 icssg1_mem: memories@0 { 1425 reg = <0x0 0x2000>, 1426 <0x2000 0x2000>, 1427 <0x10000 0x10000>; 1428 reg-names = "dram0", "dram1", "shrdram2"; 1429 }; 1430 1431 icssg1_cfg: cfg@26000 { 1432 compatible = "ti,pruss-cfg", "syscon"; 1433 reg = <0x26000 0x200>; 1434 #address-cells = <1>; 1435 #size-cells = <1>; 1436 ranges = <0x0 0x26000 0x2000>; 1437 1438 clocks { 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 1442 icssg1_coreclk_mux: coreclk-mux@3c { 1443 reg = <0x3c>; 1444 #clock-cells = <0>; 1445 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1446 <&k3_clks 82 20>; /* icssg1_iclk */ 1447 assigned-clocks = <&icssg1_coreclk_mux>; 1448 assigned-clock-parents = <&k3_clks 82 0>; 1449 }; 1450 1451 icssg1_iepclk_mux: iepclk-mux@30 { 1452 reg = <0x30>; 1453 #clock-cells = <0>; 1454 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1455 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1456 assigned-clocks = <&icssg1_iepclk_mux>; 1457 assigned-clock-parents = <&icssg1_coreclk_mux>; 1458 }; 1459 }; 1460 }; 1461 1462 icssg1_iep0: iep@2e000 { 1463 compatible = "ti,am654-icss-iep"; 1464 reg = <0x2e000 0x1000>; 1465 clocks = <&icssg1_iepclk_mux>; 1466 }; 1467 1468 icssg1_iep1: iep@2f000 { 1469 compatible = "ti,am654-icss-iep"; 1470 reg = <0x2f000 0x1000>; 1471 clocks = <&icssg1_iepclk_mux>; 1472 }; 1473 1474 icssg1_mii_rt: mii-rt@32000 { 1475 compatible = "ti,pruss-mii", "syscon"; 1476 reg = <0x32000 0x100>; 1477 }; 1478 1479 icssg1_mii_g_rt: mii-g-rt@33000 { 1480 compatible = "ti,pruss-mii-g", "syscon"; 1481 reg = <0x33000 0x1000>; 1482 }; 1483 1484 icssg1_pa_stats: pa-stats@2c000 { 1485 compatible = "ti,pruss-pa-st", "syscon"; 1486 reg = <0x2c000 0x1000>; 1487 }; 1488 1489 icssg1_intc: interrupt-controller@20000 { 1490 compatible = "ti,icssg-intc"; 1491 reg = <0x20000 0x2000>; 1492 interrupt-controller; 1493 #interrupt-cells = <3>; 1494 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1502 interrupt-names = "host_intr0", "host_intr1", 1503 "host_intr2", "host_intr3", 1504 "host_intr4", "host_intr5", 1505 "host_intr6", "host_intr7"; 1506 }; 1507 1508 pru1_0: pru@34000 { 1509 compatible = "ti,am642-pru"; 1510 reg = <0x34000 0x4000>, 1511 <0x22000 0x100>, 1512 <0x22400 0x100>; 1513 reg-names = "iram", "control", "debug"; 1514 firmware-name = "am64x-pru1_0-fw"; 1515 interrupt-parent = <&icssg1_intc>; 1516 interrupts = <16 2 2>; 1517 interrupt-names = "vring"; 1518 }; 1519 1520 rtu1_0: rtu@4000 { 1521 compatible = "ti,am642-rtu"; 1522 reg = <0x4000 0x2000>, 1523 <0x23000 0x100>, 1524 <0x23400 0x100>; 1525 reg-names = "iram", "control", "debug"; 1526 firmware-name = "am64x-rtu1_0-fw"; 1527 interrupt-parent = <&icssg1_intc>; 1528 interrupts = <20 4 4>; 1529 interrupt-names = "vring"; 1530 }; 1531 1532 tx_pru1_0: txpru@a000 { 1533 compatible = "ti,am642-tx-pru"; 1534 reg = <0xa000 0x1800>, 1535 <0x25000 0x100>, 1536 <0x25400 0x100>; 1537 reg-names = "iram", "control", "debug"; 1538 firmware-name = "am64x-txpru1_0-fw"; 1539 }; 1540 1541 pru1_1: pru@38000 { 1542 compatible = "ti,am642-pru"; 1543 reg = <0x38000 0x4000>, 1544 <0x24000 0x100>, 1545 <0x24400 0x100>; 1546 reg-names = "iram", "control", "debug"; 1547 firmware-name = "am64x-pru1_1-fw"; 1548 interrupt-parent = <&icssg1_intc>; 1549 interrupts = <18 3 3>; 1550 interrupt-names = "vring"; 1551 }; 1552 1553 rtu1_1: rtu@6000 { 1554 compatible = "ti,am642-rtu"; 1555 reg = <0x6000 0x2000>, 1556 <0x23800 0x100>, 1557 <0x23c00 0x100>; 1558 reg-names = "iram", "control", "debug"; 1559 firmware-name = "am64x-rtu1_1-fw"; 1560 interrupt-parent = <&icssg1_intc>; 1561 interrupts = <22 5 5>; 1562 interrupt-names = "vring"; 1563 }; 1564 1565 tx_pru1_1: txpru@c000 { 1566 compatible = "ti,am642-tx-pru"; 1567 reg = <0xc000 0x1800>, 1568 <0x25800 0x100>, 1569 <0x25c00 0x100>; 1570 reg-names = "iram", "control", "debug"; 1571 firmware-name = "am64x-txpru1_1-fw"; 1572 }; 1573 1574 icssg1_mdio: mdio@32400 { 1575 compatible = "ti,davinci_mdio"; 1576 reg = <0x32400 0x100>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 clocks = <&k3_clks 82 0>; 1580 clock-names = "fck"; 1581 bus_freq = <1000000>; 1582 status = "disabled"; 1583 }; 1584 }; 1585 1586 main_mcan0: can@20701000 { 1587 compatible = "bosch,m_can"; 1588 reg = <0x00 0x20701000 0x00 0x200>, 1589 <0x00 0x20708000 0x00 0x8000>; 1590 reg-names = "m_can", "message_ram"; 1591 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1592 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1593 clock-names = "hclk", "cclk"; 1594 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1596 interrupt-names = "int0", "int1"; 1597 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1598 status = "disabled"; 1599 }; 1600 1601 main_mcan1: can@20711000 { 1602 compatible = "bosch,m_can"; 1603 reg = <0x00 0x20711000 0x00 0x200>, 1604 <0x00 0x20718000 0x00 0x8000>; 1605 reg-names = "m_can", "message_ram"; 1606 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1607 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1608 clock-names = "hclk", "cclk"; 1609 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1611 interrupt-names = "int0", "int1"; 1612 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1613 status = "disabled"; 1614 }; 1615 1616 crypto: crypto@40900000 { 1617 compatible = "ti,am64-sa2ul"; 1618 reg = <0x00 0x40900000 0x00 0x1200>; 1619 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1620 #address-cells = <2>; 1621 #size-cells = <2>; 1622 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1623 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1624 <&main_pktdma 0x4003 0>; 1625 dma-names = "tx", "rx1", "rx2"; 1626 1627 rng: rng@40910000 { 1628 compatible = "inside-secure,safexcel-eip76"; 1629 reg = <0x00 0x40910000 0x00 0x7d>; 1630 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1631 status = "disabled"; /* Used by OP-TEE */ 1632 }; 1633 }; 1634 1635 gpmc0: memory-controller@3b000000 { 1636 compatible = "ti,am64-gpmc"; 1637 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1638 clocks = <&k3_clks 80 0>; 1639 clock-names = "fck"; 1640 reg = <0x00 0x3b000000 0x00 0x400>, 1641 <0x00 0x50000000 0x00 0x8000000>; 1642 reg-names = "cfg", "data"; 1643 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1644 gpmc,num-cs = <3>; 1645 gpmc,num-waitpins = <2>; 1646 #address-cells = <2>; 1647 #size-cells = <1>; 1648 interrupt-controller; 1649 #interrupt-cells = <2>; 1650 gpio-controller; 1651 #gpio-cells = <2>; 1652 status = "disabled"; 1653 }; 1654 1655 elm0: ecc@25010000 { 1656 compatible = "ti,am64-elm"; 1657 reg = <0x00 0x25010000 0x00 0x2000>; 1658 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1659 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1660 clocks = <&k3_clks 54 0>; 1661 clock-names = "fck"; 1662 status = "disabled"; 1663 }; 1664 1665 main_vtm0: temperature-sensor@b00000 { 1666 compatible = "ti,j7200-vtm"; 1667 reg = <0x00 0xb00000 0x00 0x400>, 1668 <0x00 0xb01000 0x00 0x400>; 1669 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1670 #thermal-sensor-cells = <1>; 1671 }; 1672}; 1673