1// SPDX-License-Identifier: GPL-2.0-only or MIT 2/* 3 * Device Tree file for the AM62L3 SoC family (Dual Core A53) 4 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 7 */ 8 9/dts-v1/; 10 11#include "k3-am62l.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0: cluster0 { 20 core0 { 21 cpu = <&cpu0>; 22 }; 23 24 core1 { 25 cpu = <&cpu1>; 26 }; 27 }; 28 }; 29 30 cpu0: cpu@0 { 31 compatible = "arm,cortex-a53"; 32 reg = <0x000>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 i-cache-size = <0x8000>; 36 i-cache-line-size = <64>; 37 i-cache-sets = <256>; 38 d-cache-size = <0x8000>; 39 d-cache-line-size = <64>; 40 d-cache-sets = <128>; 41 next-level-cache = <&l2_0>; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "arm,cortex-a53"; 46 reg = <0x001>; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 i-cache-size = <0x8000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_0>; 56 }; 57 }; 58 59 l2_0: l2-cache0 { 60 compatible = "cache"; 61 cache-unified; 62 cache-level = <2>; 63 cache-size = <0x40000>; 64 cache-line-size = <64>; 65 cache-sets = <256>; 66 }; 67}; 68