1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> 4 */ 5 6#include <dt-bindings/clock/spacemit,k1-syscon.h> 7 8/dts-v1/; 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 model = "SpacemiT K1"; 13 compatible = "spacemit,k1"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <24000000>; 19 20 cpu-map { 21 cluster0 { 22 core0 { 23 cpu = <&cpu_0>; 24 }; 25 core1 { 26 cpu = <&cpu_1>; 27 }; 28 core2 { 29 cpu = <&cpu_2>; 30 }; 31 core3 { 32 cpu = <&cpu_3>; 33 }; 34 }; 35 36 cluster1 { 37 core0 { 38 cpu = <&cpu_4>; 39 }; 40 core1 { 41 cpu = <&cpu_5>; 42 }; 43 core2 { 44 cpu = <&cpu_6>; 45 }; 46 core3 { 47 cpu = <&cpu_7>; 48 }; 49 }; 50 }; 51 52 cpu_0: cpu@0 { 53 compatible = "spacemit,x60", "riscv"; 54 device_type = "cpu"; 55 reg = <0>; 56 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 57 riscv,isa-base = "rv64i"; 58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 59 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 60 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 61 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 62 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 63 riscv,cbom-block-size = <64>; 64 riscv,cbop-block-size = <64>; 65 riscv,cboz-block-size = <64>; 66 i-cache-block-size = <64>; 67 i-cache-size = <32768>; 68 i-cache-sets = <128>; 69 d-cache-block-size = <64>; 70 d-cache-size = <32768>; 71 d-cache-sets = <128>; 72 next-level-cache = <&cluster0_l2_cache>; 73 mmu-type = "riscv,sv39"; 74 75 cpu0_intc: interrupt-controller { 76 compatible = "riscv,cpu-intc"; 77 interrupt-controller; 78 #interrupt-cells = <1>; 79 }; 80 }; 81 82 cpu_1: cpu@1 { 83 compatible = "spacemit,x60", "riscv"; 84 device_type = "cpu"; 85 reg = <1>; 86 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 87 riscv,isa-base = "rv64i"; 88 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 89 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 90 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 91 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 92 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 93 riscv,cbom-block-size = <64>; 94 riscv,cbop-block-size = <64>; 95 riscv,cboz-block-size = <64>; 96 i-cache-block-size = <64>; 97 i-cache-size = <32768>; 98 i-cache-sets = <128>; 99 d-cache-block-size = <64>; 100 d-cache-size = <32768>; 101 d-cache-sets = <128>; 102 next-level-cache = <&cluster0_l2_cache>; 103 mmu-type = "riscv,sv39"; 104 105 cpu1_intc: interrupt-controller { 106 compatible = "riscv,cpu-intc"; 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 }; 110 }; 111 112 cpu_2: cpu@2 { 113 compatible = "spacemit,x60", "riscv"; 114 device_type = "cpu"; 115 reg = <2>; 116 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 117 riscv,isa-base = "rv64i"; 118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 119 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 120 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 121 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 122 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 123 riscv,cbom-block-size = <64>; 124 riscv,cbop-block-size = <64>; 125 riscv,cboz-block-size = <64>; 126 i-cache-block-size = <64>; 127 i-cache-size = <32768>; 128 i-cache-sets = <128>; 129 d-cache-block-size = <64>; 130 d-cache-size = <32768>; 131 d-cache-sets = <128>; 132 next-level-cache = <&cluster0_l2_cache>; 133 mmu-type = "riscv,sv39"; 134 135 cpu2_intc: interrupt-controller { 136 compatible = "riscv,cpu-intc"; 137 interrupt-controller; 138 #interrupt-cells = <1>; 139 }; 140 }; 141 142 cpu_3: cpu@3 { 143 compatible = "spacemit,x60", "riscv"; 144 device_type = "cpu"; 145 reg = <3>; 146 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 147 riscv,isa-base = "rv64i"; 148 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 149 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 150 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 151 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 152 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 153 riscv,cbom-block-size = <64>; 154 riscv,cbop-block-size = <64>; 155 riscv,cboz-block-size = <64>; 156 i-cache-block-size = <64>; 157 i-cache-size = <32768>; 158 i-cache-sets = <128>; 159 d-cache-block-size = <64>; 160 d-cache-size = <32768>; 161 d-cache-sets = <128>; 162 next-level-cache = <&cluster0_l2_cache>; 163 mmu-type = "riscv,sv39"; 164 165 cpu3_intc: interrupt-controller { 166 compatible = "riscv,cpu-intc"; 167 interrupt-controller; 168 #interrupt-cells = <1>; 169 }; 170 }; 171 172 cpu_4: cpu@4 { 173 compatible = "spacemit,x60", "riscv"; 174 device_type = "cpu"; 175 reg = <4>; 176 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 177 riscv,isa-base = "rv64i"; 178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 179 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 180 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 181 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 182 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 183 riscv,cbom-block-size = <64>; 184 riscv,cbop-block-size = <64>; 185 riscv,cboz-block-size = <64>; 186 i-cache-block-size = <64>; 187 i-cache-size = <32768>; 188 i-cache-sets = <128>; 189 d-cache-block-size = <64>; 190 d-cache-size = <32768>; 191 d-cache-sets = <128>; 192 next-level-cache = <&cluster1_l2_cache>; 193 mmu-type = "riscv,sv39"; 194 195 cpu4_intc: interrupt-controller { 196 compatible = "riscv,cpu-intc"; 197 interrupt-controller; 198 #interrupt-cells = <1>; 199 }; 200 }; 201 202 cpu_5: cpu@5 { 203 compatible = "spacemit,x60", "riscv"; 204 device_type = "cpu"; 205 reg = <5>; 206 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 207 riscv,isa-base = "rv64i"; 208 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 209 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 210 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 211 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 212 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 213 riscv,cbom-block-size = <64>; 214 riscv,cbop-block-size = <64>; 215 riscv,cboz-block-size = <64>; 216 i-cache-block-size = <64>; 217 i-cache-size = <32768>; 218 i-cache-sets = <128>; 219 d-cache-block-size = <64>; 220 d-cache-size = <32768>; 221 d-cache-sets = <128>; 222 next-level-cache = <&cluster1_l2_cache>; 223 mmu-type = "riscv,sv39"; 224 225 cpu5_intc: interrupt-controller { 226 compatible = "riscv,cpu-intc"; 227 interrupt-controller; 228 #interrupt-cells = <1>; 229 }; 230 }; 231 232 cpu_6: cpu@6 { 233 compatible = "spacemit,x60", "riscv"; 234 device_type = "cpu"; 235 reg = <6>; 236 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 237 riscv,isa-base = "rv64i"; 238 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 239 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 240 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 241 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 242 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 243 riscv,cbom-block-size = <64>; 244 riscv,cbop-block-size = <64>; 245 riscv,cboz-block-size = <64>; 246 i-cache-block-size = <64>; 247 i-cache-size = <32768>; 248 i-cache-sets = <128>; 249 d-cache-block-size = <64>; 250 d-cache-size = <32768>; 251 d-cache-sets = <128>; 252 next-level-cache = <&cluster1_l2_cache>; 253 mmu-type = "riscv,sv39"; 254 255 cpu6_intc: interrupt-controller { 256 compatible = "riscv,cpu-intc"; 257 interrupt-controller; 258 #interrupt-cells = <1>; 259 }; 260 }; 261 262 cpu_7: cpu@7 { 263 compatible = "spacemit,x60", "riscv"; 264 device_type = "cpu"; 265 reg = <7>; 266 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 267 riscv,isa-base = "rv64i"; 268 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 269 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 270 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 271 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 272 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 273 riscv,cbom-block-size = <64>; 274 riscv,cbop-block-size = <64>; 275 riscv,cboz-block-size = <64>; 276 i-cache-block-size = <64>; 277 i-cache-size = <32768>; 278 i-cache-sets = <128>; 279 d-cache-block-size = <64>; 280 d-cache-size = <32768>; 281 d-cache-sets = <128>; 282 next-level-cache = <&cluster1_l2_cache>; 283 mmu-type = "riscv,sv39"; 284 285 cpu7_intc: interrupt-controller { 286 compatible = "riscv,cpu-intc"; 287 interrupt-controller; 288 #interrupt-cells = <1>; 289 }; 290 }; 291 292 cluster0_l2_cache: l2-cache0 { 293 compatible = "cache"; 294 cache-block-size = <64>; 295 cache-level = <2>; 296 cache-size = <524288>; 297 cache-sets = <512>; 298 cache-unified; 299 }; 300 301 cluster1_l2_cache: l2-cache1 { 302 compatible = "cache"; 303 cache-block-size = <64>; 304 cache-level = <2>; 305 cache-size = <524288>; 306 cache-sets = <512>; 307 cache-unified; 308 }; 309 }; 310 311 clocks { 312 vctcxo_1m: clock-1m { 313 compatible = "fixed-clock"; 314 clock-frequency = <1000000>; 315 clock-output-names = "vctcxo_1m"; 316 #clock-cells = <0>; 317 }; 318 319 vctcxo_24m: clock-24m { 320 compatible = "fixed-clock"; 321 clock-frequency = <24000000>; 322 clock-output-names = "vctcxo_24m"; 323 #clock-cells = <0>; 324 }; 325 326 vctcxo_3m: clock-3m { 327 compatible = "fixed-clock"; 328 clock-frequency = <3000000>; 329 clock-output-names = "vctcxo_3m"; 330 #clock-cells = <0>; 331 }; 332 333 osc_32k: clock-32k { 334 compatible = "fixed-clock"; 335 clock-frequency = <32000>; 336 clock-output-names = "osc_32k"; 337 #clock-cells = <0>; 338 }; 339 }; 340 341 soc { 342 compatible = "simple-bus"; 343 interrupt-parent = <&plic>; 344 #address-cells = <2>; 345 #size-cells = <2>; 346 dma-noncoherent; 347 ranges; 348 349 syscon_rcpu: system-controller@c0880000 { 350 compatible = "spacemit,k1-syscon-rcpu"; 351 reg = <0x0 0xc0880000 0x0 0x2048>; 352 #reset-cells = <1>; 353 }; 354 355 syscon_rcpu2: system-controller@c0888000 { 356 compatible = "spacemit,k1-syscon-rcpu2"; 357 reg = <0x0 0xc0888000 0x0 0x28>; 358 #reset-cells = <1>; 359 }; 360 361 i2c0: i2c@d4010800 { 362 compatible = "spacemit,k1-i2c"; 363 reg = <0x0 0xd4010800 0x0 0x38>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 clocks = <&syscon_apbc CLK_TWSI0>, 367 <&syscon_apbc CLK_TWSI0_BUS>; 368 clock-names = "func", "bus"; 369 clock-frequency = <400000>; 370 interrupts = <36>; 371 status = "disabled"; 372 }; 373 374 i2c1: i2c@d4011000 { 375 compatible = "spacemit,k1-i2c"; 376 reg = <0x0 0xd4011000 0x0 0x38>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&syscon_apbc CLK_TWSI1>, 380 <&syscon_apbc CLK_TWSI1_BUS>; 381 clock-names = "func", "bus"; 382 clock-frequency = <400000>; 383 interrupts = <37>; 384 status = "disabled"; 385 }; 386 387 i2c2: i2c@d4012000 { 388 compatible = "spacemit,k1-i2c"; 389 reg = <0x0 0xd4012000 0x0 0x38>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&syscon_apbc CLK_TWSI2>, 393 <&syscon_apbc CLK_TWSI2_BUS>; 394 clock-names = "func", "bus"; 395 clock-frequency = <400000>; 396 interrupts = <38>; 397 status = "disabled"; 398 }; 399 400 i2c4: i2c@d4012800 { 401 compatible = "spacemit,k1-i2c"; 402 reg = <0x0 0xd4012800 0x0 0x38>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&syscon_apbc CLK_TWSI4>, 406 <&syscon_apbc CLK_TWSI4_BUS>; 407 clock-names = "func", "bus"; 408 clock-frequency = <400000>; 409 interrupts = <40>; 410 status = "disabled"; 411 }; 412 413 i2c5: i2c@d4013800 { 414 compatible = "spacemit,k1-i2c"; 415 reg = <0x0 0xd4013800 0x0 0x38>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&syscon_apbc CLK_TWSI5>, 419 <&syscon_apbc CLK_TWSI5_BUS>; 420 clock-names = "func", "bus"; 421 clock-frequency = <400000>; 422 interrupts = <41>; 423 status = "disabled"; 424 }; 425 426 syscon_apbc: system-controller@d4015000 { 427 compatible = "spacemit,k1-syscon-apbc"; 428 reg = <0x0 0xd4015000 0x0 0x1000>; 429 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 430 <&vctcxo_24m>; 431 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 432 "vctcxo_24m"; 433 #clock-cells = <1>; 434 #reset-cells = <1>; 435 }; 436 437 i2c6: i2c@d4018800 { 438 compatible = "spacemit,k1-i2c"; 439 reg = <0x0 0xd4018800 0x0 0x38>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&syscon_apbc CLK_TWSI6>, 443 <&syscon_apbc CLK_TWSI6_BUS>; 444 clock-names = "func", "bus"; 445 clock-frequency = <400000>; 446 interrupts = <70>; 447 status = "disabled"; 448 }; 449 450 gpio: gpio@d4019000 { 451 compatible = "spacemit,k1-gpio"; 452 reg = <0x0 0xd4019000 0x0 0x100>; 453 clocks = <&syscon_apbc CLK_GPIO>, 454 <&syscon_apbc CLK_GPIO_BUS>; 455 clock-names = "core", "bus"; 456 gpio-controller; 457 #gpio-cells = <3>; 458 interrupts = <58>; 459 interrupt-parent = <&plic>; 460 interrupt-controller; 461 #interrupt-cells = <3>; 462 gpio-ranges = <&pinctrl 0 0 0 32>, 463 <&pinctrl 1 0 32 32>, 464 <&pinctrl 2 0 64 32>, 465 <&pinctrl 3 0 96 32>; 466 }; 467 468 pwm0: pwm@d401a000 { 469 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 470 reg = <0x0 0xd401a000 0x0 0x10>; 471 #pwm-cells = <3>; 472 clocks = <&syscon_apbc CLK_PWM0>; 473 resets = <&syscon_apbc RESET_PWM0>; 474 status = "disabled"; 475 }; 476 477 pwm1: pwm@d401a400 { 478 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 479 reg = <0x0 0xd401a400 0x0 0x10>; 480 #pwm-cells = <3>; 481 clocks = <&syscon_apbc CLK_PWM1>; 482 resets = <&syscon_apbc RESET_PWM1>; 483 status = "disabled"; 484 }; 485 486 pwm2: pwm@d401a800 { 487 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 488 reg = <0x0 0xd401a800 0x0 0x10>; 489 #pwm-cells = <3>; 490 clocks = <&syscon_apbc CLK_PWM2>; 491 resets = <&syscon_apbc RESET_PWM2>; 492 status = "disabled"; 493 }; 494 495 pwm3: pwm@d401ac00 { 496 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 497 reg = <0x0 0xd401ac00 0x0 0x10>; 498 #pwm-cells = <3>; 499 clocks = <&syscon_apbc CLK_PWM3>; 500 resets = <&syscon_apbc RESET_PWM3>; 501 status = "disabled"; 502 }; 503 504 pwm4: pwm@d401b000 { 505 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 506 reg = <0x0 0xd401b000 0x0 0x10>; 507 #pwm-cells = <3>; 508 clocks = <&syscon_apbc CLK_PWM4>; 509 resets = <&syscon_apbc RESET_PWM4>; 510 status = "disabled"; 511 }; 512 513 pwm5: pwm@d401b400 { 514 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 515 reg = <0x0 0xd401b400 0x0 0x10>; 516 #pwm-cells = <3>; 517 clocks = <&syscon_apbc CLK_PWM5>; 518 resets = <&syscon_apbc RESET_PWM5>; 519 status = "disabled"; 520 }; 521 522 pwm6: pwm@d401b800 { 523 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 524 reg = <0x0 0xd401b800 0x0 0x10>; 525 #pwm-cells = <3>; 526 clocks = <&syscon_apbc CLK_PWM6>; 527 resets = <&syscon_apbc RESET_PWM6>; 528 status = "disabled"; 529 }; 530 531 pwm7: pwm@d401bc00 { 532 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 533 reg = <0x0 0xd401bc00 0x0 0x10>; 534 #pwm-cells = <3>; 535 clocks = <&syscon_apbc CLK_PWM7>; 536 resets = <&syscon_apbc RESET_PWM7>; 537 status = "disabled"; 538 }; 539 540 i2c7: i2c@d401d000 { 541 compatible = "spacemit,k1-i2c"; 542 reg = <0x0 0xd401d000 0x0 0x38>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&syscon_apbc CLK_TWSI7>, 546 <&syscon_apbc CLK_TWSI7_BUS>; 547 clock-names = "func", "bus"; 548 clock-frequency = <400000>; 549 interrupts = <18>; 550 status = "disabled"; 551 }; 552 553 i2c8: i2c@d401d800 { 554 compatible = "spacemit,k1-i2c"; 555 reg = <0x0 0xd401d800 0x0 0x38>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clocks = <&syscon_apbc CLK_TWSI8>, 559 <&syscon_apbc CLK_TWSI8_BUS>; 560 clock-names = "func", "bus"; 561 clock-frequency = <400000>; 562 interrupts = <19>; 563 status = "disabled"; 564 }; 565 566 pinctrl: pinctrl@d401e000 { 567 compatible = "spacemit,k1-pinctrl"; 568 reg = <0x0 0xd401e000 0x0 0x400>; 569 clocks = <&syscon_apbc CLK_AIB>, 570 <&syscon_apbc CLK_AIB_BUS>; 571 clock-names = "func", "bus"; 572 }; 573 574 pwm8: pwm@d4020000 { 575 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 576 reg = <0x0 0xd4020000 0x0 0x10>; 577 #pwm-cells = <3>; 578 clocks = <&syscon_apbc CLK_PWM8>; 579 resets = <&syscon_apbc RESET_PWM8>; 580 status = "disabled"; 581 }; 582 583 pwm9: pwm@d4020400 { 584 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 585 reg = <0x0 0xd4020400 0x0 0x10>; 586 #pwm-cells = <3>; 587 clocks = <&syscon_apbc CLK_PWM9>; 588 resets = <&syscon_apbc RESET_PWM9>; 589 status = "disabled"; 590 }; 591 592 pwm10: pwm@d4020800 { 593 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 594 reg = <0x0 0xd4020800 0x0 0x10>; 595 #pwm-cells = <3>; 596 clocks = <&syscon_apbc CLK_PWM10>; 597 resets = <&syscon_apbc RESET_PWM10>; 598 status = "disabled"; 599 }; 600 601 pwm11: pwm@d4020c00 { 602 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 603 reg = <0x0 0xd4020c00 0x0 0x10>; 604 #pwm-cells = <3>; 605 clocks = <&syscon_apbc CLK_PWM11>; 606 resets = <&syscon_apbc RESET_PWM11>; 607 status = "disabled"; 608 }; 609 610 pwm12: pwm@d4021000 { 611 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 612 reg = <0x0 0xd4021000 0x0 0x10>; 613 #pwm-cells = <3>; 614 clocks = <&syscon_apbc CLK_PWM12>; 615 resets = <&syscon_apbc RESET_PWM12>; 616 status = "disabled"; 617 }; 618 619 pwm13: pwm@d4021400 { 620 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 621 reg = <0x0 0xd4021400 0x0 0x10>; 622 #pwm-cells = <3>; 623 clocks = <&syscon_apbc CLK_PWM13>; 624 resets = <&syscon_apbc RESET_PWM13>; 625 status = "disabled"; 626 }; 627 628 pwm14: pwm@d4021800 { 629 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 630 reg = <0x0 0xd4021800 0x0 0x10>; 631 #pwm-cells = <3>; 632 clocks = <&syscon_apbc CLK_PWM14>; 633 resets = <&syscon_apbc RESET_PWM14>; 634 status = "disabled"; 635 }; 636 637 pwm15: pwm@d4021c00 { 638 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 639 reg = <0x0 0xd4021c00 0x0 0x10>; 640 #pwm-cells = <3>; 641 clocks = <&syscon_apbc CLK_PWM15>; 642 resets = <&syscon_apbc RESET_PWM15>; 643 status = "disabled"; 644 }; 645 646 pwm16: pwm@d4022000 { 647 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 648 reg = <0x0 0xd4022000 0x0 0x10>; 649 #pwm-cells = <3>; 650 clocks = <&syscon_apbc CLK_PWM16>; 651 resets = <&syscon_apbc RESET_PWM16>; 652 status = "disabled"; 653 }; 654 655 pwm17: pwm@d4022400 { 656 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 657 reg = <0x0 0xd4022400 0x0 0x10>; 658 #pwm-cells = <3>; 659 clocks = <&syscon_apbc CLK_PWM17>; 660 resets = <&syscon_apbc RESET_PWM17>; 661 status = "disabled"; 662 }; 663 664 pwm18: pwm@d4022800 { 665 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 666 reg = <0x0 0xd4022800 0x0 0x10>; 667 #pwm-cells = <3>; 668 clocks = <&syscon_apbc CLK_PWM18>; 669 resets = <&syscon_apbc RESET_PWM18>; 670 status = "disabled"; 671 }; 672 673 pwm19: pwm@d4022c00 { 674 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 675 reg = <0x0 0xd4022c00 0x0 0x10>; 676 #pwm-cells = <3>; 677 clocks = <&syscon_apbc CLK_PWM19>; 678 resets = <&syscon_apbc RESET_PWM19>; 679 status = "disabled"; 680 }; 681 682 syscon_mpmu: system-controller@d4050000 { 683 compatible = "spacemit,k1-syscon-mpmu"; 684 reg = <0x0 0xd4050000 0x0 0x209c>; 685 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 686 <&vctcxo_24m>; 687 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 688 "vctcxo_24m"; 689 #clock-cells = <1>; 690 #power-domain-cells = <1>; 691 #reset-cells = <1>; 692 }; 693 694 pll: clock-controller@d4090000 { 695 compatible = "spacemit,k1-pll"; 696 reg = <0x0 0xd4090000 0x0 0x1000>; 697 clocks = <&vctcxo_24m>; 698 spacemit,mpmu = <&syscon_mpmu>; 699 #clock-cells = <1>; 700 }; 701 702 syscon_apmu: system-controller@d4282800 { 703 compatible = "spacemit,k1-syscon-apmu"; 704 reg = <0x0 0xd4282800 0x0 0x400>; 705 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 706 <&vctcxo_24m>; 707 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 708 "vctcxo_24m"; 709 #clock-cells = <1>; 710 #power-domain-cells = <1>; 711 #reset-cells = <1>; 712 }; 713 714 plic: interrupt-controller@e0000000 { 715 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; 716 reg = <0x0 0xe0000000 0x0 0x4000000>; 717 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 718 <&cpu1_intc 11>, <&cpu1_intc 9>, 719 <&cpu2_intc 11>, <&cpu2_intc 9>, 720 <&cpu3_intc 11>, <&cpu3_intc 9>, 721 <&cpu4_intc 11>, <&cpu4_intc 9>, 722 <&cpu5_intc 11>, <&cpu5_intc 9>, 723 <&cpu6_intc 11>, <&cpu6_intc 9>, 724 <&cpu7_intc 11>, <&cpu7_intc 9>; 725 interrupt-controller; 726 #address-cells = <0>; 727 #interrupt-cells = <1>; 728 riscv,ndev = <159>; 729 }; 730 731 clint: timer@e4000000 { 732 compatible = "spacemit,k1-clint", "sifive,clint0"; 733 reg = <0x0 0xe4000000 0x0 0x10000>; 734 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 735 <&cpu1_intc 3>, <&cpu1_intc 7>, 736 <&cpu2_intc 3>, <&cpu2_intc 7>, 737 <&cpu3_intc 3>, <&cpu3_intc 7>, 738 <&cpu4_intc 3>, <&cpu4_intc 7>, 739 <&cpu5_intc 3>, <&cpu5_intc 7>, 740 <&cpu6_intc 3>, <&cpu6_intc 7>, 741 <&cpu7_intc 3>, <&cpu7_intc 7>; 742 }; 743 744 syscon_apbc2: system-controller@f0610000 { 745 compatible = "spacemit,k1-syscon-apbc2"; 746 reg = <0x0 0xf0610000 0x0 0x20>; 747 #reset-cells = <1>; 748 }; 749 750 /* sec_i2c3: 0xf0614000, not available from Linux */ 751 752 camera-bus { 753 compatible = "simple-bus"; 754 ranges; 755 #address-cells = <2>; 756 #size-cells = <2>; 757 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 758 <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>; 759 }; 760 761 dma-bus { 762 compatible = "simple-bus"; 763 ranges; 764 #address-cells = <2>; 765 #size-cells = <2>; 766 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 767 <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; 768 769 pdma: dma-controller@d4000000 { 770 compatible = "spacemit,k1-pdma"; 771 reg = <0x0 0xd4000000 0x0 0x4000>; 772 clocks = <&syscon_apmu CLK_DMA>; 773 resets = <&syscon_apmu RESET_DMA>; 774 interrupts = <72>; 775 dma-channels = <16>; 776 #dma-cells= <1>; 777 status = "disabled"; 778 }; 779 780 uart0: serial@d4017000 { 781 compatible = "spacemit,k1-uart", 782 "intel,xscale-uart"; 783 reg = <0x0 0xd4017000 0x0 0x100>; 784 clocks = <&syscon_apbc CLK_UART0>, 785 <&syscon_apbc CLK_UART0_BUS>; 786 clock-names = "core", "bus"; 787 resets = <&syscon_apbc RESET_UART0>; 788 interrupts = <42>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 status = "disabled"; 792 }; 793 794 uart2: serial@d4017100 { 795 compatible = "spacemit,k1-uart", 796 "intel,xscale-uart"; 797 reg = <0x0 0xd4017100 0x0 0x100>; 798 clocks = <&syscon_apbc CLK_UART2>, 799 <&syscon_apbc CLK_UART2_BUS>; 800 clock-names = "core", "bus"; 801 resets = <&syscon_apbc RESET_UART2>; 802 interrupts = <44>; 803 reg-shift = <2>; 804 reg-io-width = <4>; 805 status = "disabled"; 806 }; 807 808 uart3: serial@d4017200 { 809 compatible = "spacemit,k1-uart", 810 "intel,xscale-uart"; 811 reg = <0x0 0xd4017200 0x0 0x100>; 812 clocks = <&syscon_apbc CLK_UART3>, 813 <&syscon_apbc CLK_UART3_BUS>; 814 clock-names = "core", "bus"; 815 resets = <&syscon_apbc RESET_UART3>; 816 interrupts = <45>; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 status = "disabled"; 820 }; 821 822 uart4: serial@d4017300 { 823 compatible = "spacemit,k1-uart", 824 "intel,xscale-uart"; 825 reg = <0x0 0xd4017300 0x0 0x100>; 826 clocks = <&syscon_apbc CLK_UART4>, 827 <&syscon_apbc CLK_UART4_BUS>; 828 clock-names = "core", "bus"; 829 resets = <&syscon_apbc RESET_UART4>; 830 interrupts = <46>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 status = "disabled"; 834 }; 835 836 uart5: serial@d4017400 { 837 compatible = "spacemit,k1-uart", 838 "intel,xscale-uart"; 839 reg = <0x0 0xd4017400 0x0 0x100>; 840 clocks = <&syscon_apbc CLK_UART5>, 841 <&syscon_apbc CLK_UART5_BUS>; 842 clock-names = "core", "bus"; 843 resets = <&syscon_apbc RESET_UART5>; 844 interrupts = <47>; 845 reg-shift = <2>; 846 reg-io-width = <4>; 847 status = "disabled"; 848 }; 849 850 uart6: serial@d4017500 { 851 compatible = "spacemit,k1-uart", 852 "intel,xscale-uart"; 853 reg = <0x0 0xd4017500 0x0 0x100>; 854 clocks = <&syscon_apbc CLK_UART6>, 855 <&syscon_apbc CLK_UART6_BUS>; 856 clock-names = "core", "bus"; 857 resets = <&syscon_apbc RESET_UART6>; 858 interrupts = <48>; 859 reg-shift = <2>; 860 reg-io-width = <4>; 861 status = "disabled"; 862 }; 863 864 uart7: serial@d4017600 { 865 compatible = "spacemit,k1-uart", 866 "intel,xscale-uart"; 867 reg = <0x0 0xd4017600 0x0 0x100>; 868 clocks = <&syscon_apbc CLK_UART7>, 869 <&syscon_apbc CLK_UART7_BUS>; 870 clock-names = "core", "bus"; 871 resets = <&syscon_apbc RESET_UART7>; 872 interrupts = <49>; 873 reg-shift = <2>; 874 reg-io-width = <4>; 875 status = "disabled"; 876 }; 877 878 uart8: serial@d4017700 { 879 compatible = "spacemit,k1-uart", 880 "intel,xscale-uart"; 881 reg = <0x0 0xd4017700 0x0 0x100>; 882 clocks = <&syscon_apbc CLK_UART8>, 883 <&syscon_apbc CLK_UART8_BUS>; 884 clock-names = "core", "bus"; 885 resets = <&syscon_apbc RESET_UART8>; 886 interrupts = <50>; 887 reg-shift = <2>; 888 reg-io-width = <4>; 889 status = "disabled"; 890 }; 891 892 uart9: serial@d4017800 { 893 compatible = "spacemit,k1-uart", 894 "intel,xscale-uart"; 895 reg = <0x0 0xd4017800 0x0 0x100>; 896 clocks = <&syscon_apbc CLK_UART9>, 897 <&syscon_apbc CLK_UART9_BUS>; 898 clock-names = "core", "bus"; 899 resets = <&syscon_apbc RESET_UART9>; 900 interrupts = <51>; 901 reg-shift = <2>; 902 reg-io-width = <4>; 903 status = "disabled"; 904 }; 905 906 qspi: spi@d420c000 { 907 compatible = "spacemit,k1-qspi"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 reg = <0x0 0xd420c000 0x0 0x1000>, 911 <0x0 0xb8000000 0x0 0xc00000>; 912 reg-names = "QuadSPI", "QuadSPI-memory"; 913 clocks = <&syscon_apmu CLK_QSPI_BUS>, 914 <&syscon_apmu CLK_QSPI>; 915 clock-names = "qspi_en", "qspi"; 916 resets = <&syscon_apmu RESET_QSPI>, 917 <&syscon_apmu RESET_QSPI_BUS>; 918 interrupts = <117>; 919 status = "disabled"; 920 }; 921 922 /* sec_uart1: 0xf0612000, not available from Linux */ 923 }; 924 925 multimedia-bus { 926 compatible = "simple-bus"; 927 ranges; 928 #address-cells = <2>; 929 #size-cells = <2>; 930 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 931 <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>; 932 }; 933 934 network-bus { 935 compatible = "simple-bus"; 936 ranges; 937 #address-cells = <2>; 938 #size-cells = <2>; 939 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 940 <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>; 941 942 eth0: ethernet@cac80000 { 943 compatible = "spacemit,k1-emac"; 944 reg = <0x0 0xcac80000 0x0 0x420>; 945 clocks = <&syscon_apmu CLK_EMAC0_BUS>; 946 interrupts = <131>; 947 mac-address = [ 00 00 00 00 00 00 ]; 948 resets = <&syscon_apmu RESET_EMAC0>; 949 spacemit,apmu = <&syscon_apmu 0x3e4>; 950 status = "disabled"; 951 }; 952 953 eth1: ethernet@cac81000 { 954 compatible = "spacemit,k1-emac"; 955 reg = <0x0 0xcac81000 0x0 0x420>; 956 clocks = <&syscon_apmu CLK_EMAC1_BUS>; 957 interrupts = <133>; 958 mac-address = [ 00 00 00 00 00 00 ]; 959 resets = <&syscon_apmu RESET_EMAC1>; 960 spacemit,apmu = <&syscon_apmu 0x3ec>; 961 status = "disabled"; 962 }; 963 }; 964 965 pcie-bus { 966 compatible = "simple-bus"; 967 ranges; 968 #address-cells = <2>; 969 #size-cells = <2>; 970 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 971 <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; 972 }; 973 974 storage-bus { 975 compatible = "simple-bus"; 976 ranges; 977 #address-cells = <2>; 978 #size-cells = <2>; 979 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; 980 981 emmc: mmc@d4281000 { 982 compatible = "spacemit,k1-sdhci"; 983 reg = <0x0 0xd4281000 0x0 0x200>; 984 clocks = <&syscon_apmu CLK_SDH_AXI>, 985 <&syscon_apmu CLK_SDH2>; 986 clock-names = "core", "io"; 987 interrupts = <101>; 988 status = "disabled"; 989 }; 990 }; 991 }; 992}; 993