xref: /linux/arch/riscv/boot/dts/starfive/jh7110-common.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include "jh7110.dtsi"
9#include "jh7110-pinfunc.h"
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
13
14/ {
15	aliases {
16		ethernet0 = &gmac0;
17		i2c0 = &i2c0;
18		i2c2 = &i2c2;
19		i2c5 = &i2c5;
20		i2c6 = &i2c6;
21		mmc0 = &mmc0;
22		mmc1 = &mmc1;
23		serial0 = &uart0;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0x1 0x0>;
33		bootph-pre-ram;
34	};
35
36	gpio-restart {
37		compatible = "gpio-restart";
38		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
39		priority = <224>;
40	};
41
42	leds {
43		compatible = "gpio-leds";
44
45		led_status_power: led-0 {
46			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
47		};
48	};
49
50	pwmdac_codec: audio-codec {
51		compatible = "linux,spdif-dit";
52		#sound-dai-cells = <0>;
53	};
54
55	sound {
56		compatible = "simple-audio-card";
57		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
58		#address-cells = <1>;
59		#size-cells = <0>;
60
61		simple-audio-card,dai-link@0 {
62			reg = <0>;
63			format = "left_j";
64			bitclock-master = <&sndcpu0>;
65			frame-master = <&sndcpu0>;
66
67			sndcpu0: cpu {
68				sound-dai = <&pwmdac>;
69			};
70
71			codec {
72				sound-dai = <&pwmdac_codec>;
73			};
74		};
75	};
76};
77
78&cpus {
79	timebase-frequency = <4000000>;
80};
81
82&dvp_clk {
83	clock-frequency = <74250000>;
84};
85
86&gmac0_rgmii_rxin {
87	clock-frequency = <125000000>;
88};
89
90&gmac0_rmii_refin {
91	clock-frequency = <50000000>;
92};
93
94&gmac1_rgmii_rxin {
95	clock-frequency = <125000000>;
96};
97
98&gmac1_rmii_refin {
99	clock-frequency = <50000000>;
100};
101
102&hdmitx0_pixelclk {
103	clock-frequency = <297000000>;
104};
105
106&i2srx_bclk_ext {
107	clock-frequency = <12288000>;
108};
109
110&i2srx_lrck_ext {
111	clock-frequency = <192000>;
112};
113
114&i2stx_bclk_ext {
115	clock-frequency = <12288000>;
116};
117
118&i2stx_lrck_ext {
119	clock-frequency = <192000>;
120};
121
122&mclk_ext {
123	clock-frequency = <12288000>;
124};
125
126&osc {
127	clock-frequency = <24000000>;
128};
129
130&rtc_osc {
131	clock-frequency = <32768>;
132};
133
134&tdm_ext {
135	clock-frequency = <49152000>;
136};
137
138&camss {
139	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
140			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
141	assigned-clock-rates = <49500000>, <198000000>;
142
143	ports {
144		#address-cells = <1>;
145		#size-cells = <0>;
146
147		port@0 {
148			reg = <0>;
149		};
150
151		port@1 {
152			reg = <1>;
153
154			camss_from_csi2rx: endpoint {
155				remote-endpoint = <&csi2rx_to_camss>;
156			};
157		};
158	};
159};
160
161&csi2rx {
162	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
163	assigned-clock-rates = <297000000>;
164
165	ports {
166		#address-cells = <1>;
167		#size-cells = <0>;
168
169		port@0 {
170			reg = <0>;
171
172			/* remote MIPI sensor endpoint */
173		};
174
175		port@1 {
176			reg = <1>;
177
178			csi2rx_to_camss: endpoint {
179				remote-endpoint = <&camss_from_csi2rx>;
180			};
181		};
182	};
183};
184
185&gmac0 {
186	phy-handle = <&phy0>;
187	phy-mode = "rgmii-id";
188
189	mdio {
190		#address-cells = <1>;
191		#size-cells = <0>;
192		compatible = "snps,dwmac-mdio";
193
194		phy0: ethernet-phy@0 {
195			reg = <0>;
196		};
197	};
198};
199
200&i2c0 {
201	clock-frequency = <100000>;
202	i2c-sda-hold-time-ns = <300>;
203	i2c-sda-falling-time-ns = <510>;
204	i2c-scl-falling-time-ns = <510>;
205	pinctrl-names = "default";
206	pinctrl-0 = <&i2c0_pins>;
207};
208
209&i2c2 {
210	clock-frequency = <100000>;
211	i2c-sda-hold-time-ns = <300>;
212	i2c-sda-falling-time-ns = <510>;
213	i2c-scl-falling-time-ns = <510>;
214	pinctrl-names = "default";
215	pinctrl-0 = <&i2c2_pins>;
216	status = "okay";
217};
218
219&i2c5 {
220	clock-frequency = <100000>;
221	i2c-sda-hold-time-ns = <300>;
222	i2c-sda-falling-time-ns = <510>;
223	i2c-scl-falling-time-ns = <510>;
224	pinctrl-names = "default";
225	pinctrl-0 = <&i2c5_pins>;
226	status = "okay";
227
228	axp15060: pmic@36 {
229		compatible = "x-powers,axp15060";
230		reg = <0x36>;
231		interrupt-controller;
232		#interrupt-cells = <1>;
233
234		regulators {
235			vcc_3v3: dcdc1 {
236				regulator-boot-on;
237				regulator-always-on;
238				regulator-min-microvolt = <3300000>;
239				regulator-max-microvolt = <3300000>;
240				regulator-name = "vcc_3v3";
241			};
242
243			vdd_cpu: dcdc2 {
244				regulator-always-on;
245				regulator-min-microvolt = <500000>;
246				regulator-max-microvolt = <1540000>;
247				regulator-name = "vdd_cpu";
248			};
249
250			emmc_vdd: aldo4 {
251				regulator-boot-on;
252				regulator-always-on;
253				regulator-min-microvolt = <1800000>;
254				regulator-max-microvolt = <3300000>;
255				regulator-name = "emmc_vdd";
256			};
257		};
258	};
259
260	eeprom@50 {
261		compatible = "atmel,24c04";
262		reg = <0x50>;
263		bootph-pre-ram;
264		pagesize = <16>;
265	};
266};
267
268&i2c6 {
269	clock-frequency = <100000>;
270	i2c-sda-hold-time-ns = <300>;
271	i2c-sda-falling-time-ns = <510>;
272	i2c-scl-falling-time-ns = <510>;
273	pinctrl-names = "default";
274	pinctrl-0 = <&i2c6_pins>;
275	status = "okay";
276};
277
278&mmc0 {
279	max-frequency = <100000000>;
280	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
281	assigned-clock-rates = <50000000>;
282	bus-width = <8>;
283	bootph-pre-ram;
284	pinctrl-names = "default";
285	pinctrl-0 = <&mmc0_pins>;
286	status = "okay";
287};
288
289&mmc1 {
290	max-frequency = <100000000>;
291	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
292	assigned-clock-rates = <50000000>;
293	bus-width = <4>;
294	bootph-pre-ram;
295	cap-sd-highspeed;
296	pinctrl-names = "default";
297	pinctrl-0 = <&mmc1_pins>;
298	status = "okay";
299};
300
301&pcie0 {
302	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
303	phys = <&pciephy0>;
304	pinctrl-names = "default";
305	pinctrl-0 = <&pcie0_pins>;
306};
307
308&pcie1 {
309	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
310	phys = <&pciephy1>;
311	pinctrl-names = "default";
312	pinctrl-0 = <&pcie1_pins>;
313};
314
315&pwmdac {
316	pinctrl-names = "default";
317	pinctrl-0 = <&pwmdac_pins>;
318};
319
320&qspi {
321	#address-cells = <1>;
322	#size-cells = <0>;
323	status = "okay";
324
325	nor_flash: flash@0 {
326		compatible = "jedec,spi-nor";
327		reg = <0>;
328		bootph-pre-ram;
329		cdns,read-delay = <2>;
330		spi-max-frequency = <100000000>;
331		cdns,tshsl-ns = <1>;
332		cdns,tsd2d-ns = <1>;
333		cdns,tchsh-ns = <1>;
334		cdns,tslch-ns = <1>;
335
336		partitions {
337			compatible = "fixed-partitions";
338			#address-cells = <1>;
339			#size-cells = <1>;
340
341			spl@0 {
342				reg = <0x0 0xf0000>;
343			};
344			uboot-env@f0000 {
345				reg = <0xf0000 0x10000>;
346			};
347			uboot@100000 {
348				reg = <0x100000 0xf00000>;
349			};
350		};
351	};
352};
353
354&pwm {
355	pinctrl-names = "default";
356	pinctrl-0 = <&pwm_pins>;
357};
358
359&spi0 {
360	pinctrl-names = "default";
361	pinctrl-0 = <&spi0_pins>;
362};
363
364&syscrg {
365	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
366			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
367			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
368			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
369			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
370			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
371	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
372				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
373				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
374				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
375	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
376};
377
378&sysgpio {
379	i2c0_pins: i2c0-0 {
380		i2c-pins {
381			pinmux = <GPIOMUX(57, GPOUT_LOW,
382					      GPOEN_SYS_I2C0_CLK,
383					      GPI_SYS_I2C0_CLK)>,
384				 <GPIOMUX(58, GPOUT_LOW,
385					      GPOEN_SYS_I2C0_DATA,
386					      GPI_SYS_I2C0_DATA)>;
387			bias-disable; /* external pull-up */
388			input-enable;
389			input-schmitt-enable;
390		};
391	};
392
393	i2c2_pins: i2c2-0 {
394		i2c-pins {
395			pinmux = <GPIOMUX(3, GPOUT_LOW,
396					     GPOEN_SYS_I2C2_CLK,
397					     GPI_SYS_I2C2_CLK)>,
398				 <GPIOMUX(2, GPOUT_LOW,
399					     GPOEN_SYS_I2C2_DATA,
400					     GPI_SYS_I2C2_DATA)>;
401			bias-disable; /* external pull-up */
402			input-enable;
403			input-schmitt-enable;
404		};
405	};
406
407	i2c5_pins: i2c5-0 {
408		bootph-pre-ram;
409
410		i2c-pins {
411			pinmux = <GPIOMUX(19, GPOUT_LOW,
412					      GPOEN_SYS_I2C5_CLK,
413					      GPI_SYS_I2C5_CLK)>,
414				 <GPIOMUX(20, GPOUT_LOW,
415					      GPOEN_SYS_I2C5_DATA,
416					      GPI_SYS_I2C5_DATA)>;
417			bias-disable; /* external pull-up */
418			bootph-pre-ram;
419			input-enable;
420			input-schmitt-enable;
421		};
422	};
423
424	i2c6_pins: i2c6-0 {
425		i2c-pins {
426			pinmux = <GPIOMUX(16, GPOUT_LOW,
427					      GPOEN_SYS_I2C6_CLK,
428					      GPI_SYS_I2C6_CLK)>,
429				 <GPIOMUX(17, GPOUT_LOW,
430					      GPOEN_SYS_I2C6_DATA,
431					      GPI_SYS_I2C6_DATA)>;
432			bias-disable; /* external pull-up */
433			input-enable;
434			input-schmitt-enable;
435		};
436	};
437
438	mmc0_pins: mmc0-0 {
439		mmc-pins {
440			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
441				 <PINMUX(PAD_SD0_CMD, 0)>,
442				 <PINMUX(PAD_SD0_DATA0, 0)>,
443				 <PINMUX(PAD_SD0_DATA1, 0)>,
444				 <PINMUX(PAD_SD0_DATA2, 0)>,
445				 <PINMUX(PAD_SD0_DATA3, 0)>,
446				 <PINMUX(PAD_SD0_DATA4, 0)>,
447				 <PINMUX(PAD_SD0_DATA5, 0)>,
448				 <PINMUX(PAD_SD0_DATA6, 0)>,
449				 <PINMUX(PAD_SD0_DATA7, 0)>;
450			bias-pull-up;
451			drive-strength = <12>;
452			input-enable;
453		};
454	};
455
456	mmc1_pins: mmc1-0 {
457		clk-pins {
458			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
459					      GPOEN_ENABLE,
460					      GPI_NONE)>;
461			bias-pull-up;
462			drive-strength = <12>;
463			input-disable;
464			input-schmitt-disable;
465			slew-rate = <0>;
466		};
467
468		mmc-pins {
469			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
470					     GPOEN_SYS_SDIO1_CMD,
471					     GPI_SYS_SDIO1_CMD)>,
472				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
473					      GPOEN_SYS_SDIO1_DATA0,
474					      GPI_SYS_SDIO1_DATA0)>,
475				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
476					      GPOEN_SYS_SDIO1_DATA1,
477					      GPI_SYS_SDIO1_DATA1)>,
478				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
479					     GPOEN_SYS_SDIO1_DATA2,
480					     GPI_SYS_SDIO1_DATA2)>,
481				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
482					     GPOEN_SYS_SDIO1_DATA3,
483					     GPI_SYS_SDIO1_DATA3)>;
484			bias-pull-up;
485			drive-strength = <12>;
486			input-enable;
487			input-schmitt-enable;
488			slew-rate = <0>;
489		};
490	};
491
492	pcie0_pins: pcie0-0 {
493		clkreq-pins {
494			pinmux = <GPIOMUX(27, GPOUT_LOW,
495					      GPOEN_DISABLE,
496					      GPI_NONE)>;
497			bias-pull-down;
498			drive-strength = <2>;
499			input-enable;
500			input-schmitt-disable;
501			slew-rate = <0>;
502		};
503
504		wake-pins {
505			pinmux = <GPIOMUX(32, GPOUT_LOW,
506					      GPOEN_DISABLE,
507					      GPI_NONE)>;
508			bias-pull-up;
509			drive-strength = <2>;
510			input-enable;
511			input-schmitt-disable;
512			slew-rate = <0>;
513		};
514	};
515
516	pcie1_pins: pcie1-0 {
517		clkreq-pins {
518			pinmux = <GPIOMUX(29, GPOUT_LOW,
519					      GPOEN_DISABLE,
520					      GPI_NONE)>;
521			bias-pull-down;
522			drive-strength = <2>;
523			input-enable;
524			input-schmitt-disable;
525			slew-rate = <0>;
526		};
527
528		wake-pins {
529			pinmux = <GPIOMUX(21, GPOUT_LOW,
530				      GPOEN_DISABLE,
531					      GPI_NONE)>;
532			bias-pull-up;
533			drive-strength = <2>;
534			input-enable;
535			input-schmitt-disable;
536			slew-rate = <0>;
537		};
538	};
539
540	pwmdac_pins: pwmdac-0 {
541		pwmdac-pins {
542			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
543					      GPOEN_ENABLE,
544					      GPI_NONE)>,
545				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
546					      GPOEN_ENABLE,
547					      GPI_NONE)>;
548			bias-disable;
549			drive-strength = <2>;
550			input-disable;
551			input-schmitt-disable;
552			slew-rate = <0>;
553		};
554	};
555
556	pwm_pins: pwm-0 {
557		pwm-pins {
558			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
559					      GPOEN_SYS_PWM0_CHANNEL0,
560					      GPI_NONE)>,
561				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
562					      GPOEN_SYS_PWM0_CHANNEL1,
563					      GPI_NONE)>;
564			bias-disable;
565			drive-strength = <12>;
566			input-disable;
567			input-schmitt-disable;
568			slew-rate = <0>;
569		};
570	};
571
572	spi0_pins: spi0-0 {
573		mosi-pins {
574			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
575					      GPOEN_ENABLE,
576					      GPI_NONE)>;
577			bias-disable;
578			input-disable;
579			input-schmitt-disable;
580		};
581
582		miso-pins {
583			pinmux = <GPIOMUX(53, GPOUT_LOW,
584					      GPOEN_DISABLE,
585					      GPI_SYS_SPI0_RXD)>;
586			bias-pull-up;
587			input-enable;
588			input-schmitt-enable;
589		};
590
591		sck-pins {
592			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
593					      GPOEN_ENABLE,
594					      GPI_SYS_SPI0_CLK)>;
595			bias-disable;
596			input-disable;
597			input-schmitt-disable;
598		};
599
600		ss-pins {
601			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
602					      GPOEN_ENABLE,
603					      GPI_SYS_SPI0_FSS)>;
604			bias-disable;
605			input-disable;
606			input-schmitt-disable;
607		};
608	};
609
610	uart0_pins: uart0-0 {
611		tx-pins {
612			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
613					     GPOEN_ENABLE,
614					     GPI_NONE)>;
615			bias-disable;
616			drive-strength = <12>;
617			input-disable;
618			input-schmitt-disable;
619			slew-rate = <0>;
620		};
621
622		rx-pins {
623			pinmux = <GPIOMUX(6, GPOUT_LOW,
624					     GPOEN_DISABLE,
625					     GPI_SYS_UART0_RX)>;
626			bias-disable; /* external pull-up */
627			drive-strength = <2>;
628			input-enable;
629			input-schmitt-enable;
630			slew-rate = <0>;
631		};
632	};
633};
634
635&uart0 {
636	bootph-pre-ram;
637	pinctrl-names = "default";
638	pinctrl-0 = <&uart0_pins>;
639	status = "okay";
640};
641
642&U74_1 {
643	cpu-supply = <&vdd_cpu>;
644};
645
646&U74_2 {
647	cpu-supply = <&vdd_cpu>;
648};
649
650&U74_3 {
651	cpu-supply = <&vdd_cpu>;
652};
653
654&U74_4 {
655	cpu-supply = <&vdd_cpu>;
656};
657