1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 RDP board common device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/leds/common.h> 14#include "ipq9574.dtsi" 15 16/ { 17 aliases { 18 serial0 = &blsp1_uart2; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 regulator_fixed_3p3: s3300 { 26 compatible = "regulator-fixed"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 regulator-boot-on; 30 regulator-always-on; 31 regulator-name = "fixed_3p3"; 32 }; 33 34 regulator_fixed_0p925: s0925 { 35 compatible = "regulator-fixed"; 36 regulator-min-microvolt = <925000>; 37 regulator-max-microvolt = <925000>; 38 regulator-boot-on; 39 regulator-always-on; 40 regulator-name = "fixed_0p925"; 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 pinctrl-0 = <&gpio_keys_default>; 46 pinctrl-names = "default"; 47 48 button-wps { 49 label = "wps"; 50 linux,code = <KEY_WPS_BUTTON>; 51 gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; 52 debounce-interval = <60>; 53 }; 54 }; 55 56 leds { 57 compatible = "gpio-leds"; 58 pinctrl-0 = <&gpio_leds_default>; 59 pinctrl-names = "default"; 60 61 led-0 { 62 color = <LED_COLOR_ID_GREEN>; 63 function = LED_FUNCTION_WLAN; 64 gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 65 linux,default-trigger = "phy0tx"; 66 default-state = "off"; 67 }; 68 }; 69}; 70 71&blsp1_spi0 { 72 pinctrl-0 = <&spi_0_pins>; 73 pinctrl-names = "default"; 74 status = "okay"; 75 76 flash@0 { 77 compatible = "micron,n25q128a11", "jedec,spi-nor"; 78 reg = <0>; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 spi-max-frequency = <50000000>; 82 }; 83}; 84 85&blsp1_uart2 { 86 pinctrl-0 = <&uart2_pins>; 87 pinctrl-names = "default"; 88 status = "okay"; 89}; 90 91&rpm_requests { 92 regulators { 93 compatible = "qcom,rpm-mp5496-regulators"; 94 95 ipq9574_s1: s1 { 96 /* 97 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. 98 * During regulator registration, kernel not knowing the initial voltage, 99 * considers it as zero and brings up the regulators with minimum supported voltage. 100 * Update the regulator-min-microvolt with SVS voltage of 725mV so that 101 * the regulators are brought up with 725mV which is sufficient for all the 102 * corner parts to operate at 800MHz 103 */ 104 regulator-min-microvolt = <725000>; 105 regulator-max-microvolt = <1075000>; 106 }; 107 108 mp5496_l2: l2 { 109 regulator-min-microvolt = <1800000>; 110 regulator-max-microvolt = <1800000>; 111 regulator-always-on; 112 regulator-boot-on; 113 }; 114 115 mp5496_l5: l5 { 116 regulator-min-microvolt = <1800000>; 117 regulator-max-microvolt = <1800000>; 118 regulator-always-on; 119 regulator-boot-on; 120 }; 121 }; 122}; 123 124&sleep_clk { 125 clock-frequency = <32000>; 126}; 127 128&tlmm { 129 spi_0_pins: spi-0-state { 130 pins = "gpio11", "gpio12", "gpio13", "gpio14"; 131 function = "blsp0_spi"; 132 drive-strength = <8>; 133 bias-disable; 134 }; 135 136 gpio_keys_default: gpio-keys-default-state { 137 pins = "gpio37"; 138 function = "gpio"; 139 drive-strength = <8>; 140 bias-pull-up; 141 }; 142 143 gpio_leds_default: gpio-leds-default-state { 144 pins = "gpio64"; 145 function = "gpio"; 146 drive-strength = <8>; 147 bias-pull-up; 148 }; 149 150 qpic_snand_default_state: qpic-snand-default-state { 151 clock-pins { 152 pins = "gpio5"; 153 function = "qspi_clk"; 154 drive-strength = <8>; 155 bias-disable; 156 }; 157 158 cs-pins { 159 pins = "gpio4"; 160 function = "qspi_cs"; 161 drive-strength = <8>; 162 bias-disable; 163 }; 164 165 data-pins { 166 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 167 function = "qspi_data"; 168 drive-strength = <8>; 169 bias-disable; 170 }; 171 }; 172}; 173 174&qpic_bam { 175 status = "okay"; 176}; 177 178&qpic_nand { 179 pinctrl-0 = <&qpic_snand_default_state>; 180 pinctrl-names = "default"; 181 182 status = "okay"; 183 184 flash@0 { 185 compatible = "spi-nand"; 186 reg = <0>; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 nand-ecc-engine = <&qpic_nand>; 190 nand-ecc-strength = <4>; 191 nand-ecc-step-size = <512>; 192 }; 193}; 194 195&usb_0_dwc3 { 196 dr_mode = "host"; 197}; 198 199&usb_0_qmpphy { 200 vdda-pll-supply = <&mp5496_l5>; 201 vdda-phy-supply = <®ulator_fixed_0p925>; 202 203 status = "okay"; 204}; 205 206&usb_0_qusbphy { 207 vdd-supply = <®ulator_fixed_0p925>; 208 vdda-pll-supply = <&mp5496_l5>; 209 vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; 210 211 status = "okay"; 212}; 213 214&usb3 { 215 status = "okay"; 216}; 217 218/* 219 * The bootstrap pins for the board select the XO clock frequency 220 * (48 MHZ or 96 MHZ used for different RDP type board). This setting 221 * automatically enables the right dividers, to ensure the reference 222 * clock output from WiFi to the CMN PLL is 48 MHZ. 223 */ 224&ref_48mhz_clk { 225 clock-div = <1>; 226 clock-mult = <1>; 227}; 228 229/* 230 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed 231 * from WiFi output clock 48 MHZ divided by 2. 232 */ 233&xo_board_clk { 234 clock-div = <2>; 235 clock-mult = <1>; 236}; 237 238&xo_clk { 239 clock-frequency = <48000000>; 240}; 241