1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 2 /* Do not edit directly, auto-generated from: */ 3 /* Documentation/netlink/specs/dpll.yaml */ 4 /* YNL-GEN uapi header */ 5 /* To regenerate run: tools/net/ynl/ynl-regen.sh */ 6 7 #ifndef _UAPI_LINUX_DPLL_H 8 #define _UAPI_LINUX_DPLL_H 9 10 #define DPLL_FAMILY_NAME "dpll" 11 #define DPLL_FAMILY_VERSION 1 12 13 /** 14 * enum dpll_mode - working modes a dpll can support, differentiates if and how 15 * dpll selects one of its inputs to syntonize with it, valid values for 16 * DPLL_A_MODE attribute 17 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll 18 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll 19 */ 20 enum dpll_mode { 21 DPLL_MODE_MANUAL = 1, 22 DPLL_MODE_AUTOMATIC, 23 24 /* private: */ 25 __DPLL_MODE_MAX, 26 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1) 27 }; 28 29 /** 30 * enum dpll_lock_status - provides information of dpll device lock status, 31 * valid values for DPLL_A_LOCK_STATUS attribute 32 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or 33 * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED) 34 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover 35 * available 36 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired 37 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or 38 * was forced by disconnecting all the pins (latter possible only when dpll 39 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state 40 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain 41 * DPLL_LOCK_STATUS_UNLOCKED) 42 */ 43 enum dpll_lock_status { 44 DPLL_LOCK_STATUS_UNLOCKED = 1, 45 DPLL_LOCK_STATUS_LOCKED, 46 DPLL_LOCK_STATUS_LOCKED_HO_ACQ, 47 DPLL_LOCK_STATUS_HOLDOVER, 48 49 /* private: */ 50 __DPLL_LOCK_STATUS_MAX, 51 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1) 52 }; 53 54 /** 55 * enum dpll_lock_status_error - if previous status change was done due to a 56 * failure, this provides information of dpll device lock status error. Valid 57 * values for DPLL_A_LOCK_STATUS_ERROR attribute 58 * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without 59 * any error 60 * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due 61 * to undefined error. Driver fills this value up in case it is not able to 62 * obtain suitable exact error type. 63 * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed 64 * because of associated media got down. This may happen for example if dpll 65 * device was previously locked on an input pin of type 66 * PIN_TYPE_SYNCE_ETH_PORT. 67 * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO 68 * (Fractional Frequency Offset) between the RX and TX symbol rate on the 69 * media got too high. This may happen for example if dpll device was 70 * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. 71 */ 72 enum dpll_lock_status_error { 73 DPLL_LOCK_STATUS_ERROR_NONE = 1, 74 DPLL_LOCK_STATUS_ERROR_UNDEFINED, 75 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN, 76 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH, 77 78 /* private: */ 79 __DPLL_LOCK_STATUS_ERROR_MAX, 80 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1) 81 }; 82 83 /* 84 * level of quality of a clock device. This mainly applies when the dpll 85 * lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined 86 * according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One 87 * may extend this list freely by other ITU-T defined clock qualities, or 88 * different ones defined by another standardization body (for those, please 89 * use different prefix). 90 */ 91 enum dpll_clock_quality_level { 92 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1, 93 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A, 94 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B, 95 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1, 96 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC, 97 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRTC, 98 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEEC, 99 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRC, 100 101 /* private: */ 102 __DPLL_CLOCK_QUALITY_LEVEL_MAX, 103 DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1) 104 }; 105 106 #define DPLL_TEMP_DIVIDER 1000 107 108 /** 109 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute 110 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal 111 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock 112 * @DPLL_TYPE_GENERIC: generic dpll type for devices outside PPS/EEC classes 113 */ 114 enum dpll_type { 115 DPLL_TYPE_PPS = 1, 116 DPLL_TYPE_EEC, 117 DPLL_TYPE_GENERIC, 118 119 /* private: */ 120 __DPLL_TYPE_MAX, 121 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1) 122 }; 123 124 /** 125 * enum dpll_pin_type - defines possible types of a pin, valid values for 126 * DPLL_A_PIN_TYPE attribute 127 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins 128 * @DPLL_PIN_TYPE_EXT: external input 129 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock 130 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator 131 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock 132 * @DPLL_PIN_TYPE_INT_NCO: Device internal numerically controlled oscillator. 133 * When connected as a DPLL input, the DPLL enters NCO mode where the output 134 * frequency is adjusted by the host via the PTP clock interface. 135 */ 136 enum dpll_pin_type { 137 DPLL_PIN_TYPE_MUX = 1, 138 DPLL_PIN_TYPE_EXT, 139 DPLL_PIN_TYPE_SYNCE_ETH_PORT, 140 DPLL_PIN_TYPE_INT_OSCILLATOR, 141 DPLL_PIN_TYPE_GNSS, 142 DPLL_PIN_TYPE_INT_NCO, 143 144 /* private: */ 145 __DPLL_PIN_TYPE_MAX, 146 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1) 147 }; 148 149 /** 150 * enum dpll_pin_direction - defines possible direction of a pin, valid values 151 * for DPLL_A_PIN_DIRECTION attribute 152 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal 153 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal 154 */ 155 enum dpll_pin_direction { 156 DPLL_PIN_DIRECTION_INPUT = 1, 157 DPLL_PIN_DIRECTION_OUTPUT, 158 159 /* private: */ 160 __DPLL_PIN_DIRECTION_MAX, 161 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1) 162 }; 163 164 #define DPLL_PIN_FREQUENCY_1_HZ 1 165 #define DPLL_PIN_FREQUENCY_10_KHZ 10000 166 #define DPLL_PIN_FREQUENCY_77_5_KHZ 77500 167 #define DPLL_PIN_FREQUENCY_10_MHZ 10000000 168 169 /** 170 * enum dpll_pin_state - defines possible states of a pin, valid values for 171 * DPLL_A_PIN_STATE attribute 172 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop 173 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid 174 * input 175 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection 176 */ 177 enum dpll_pin_state { 178 DPLL_PIN_STATE_CONNECTED = 1, 179 DPLL_PIN_STATE_DISCONNECTED, 180 DPLL_PIN_STATE_SELECTABLE, 181 182 /* private: */ 183 __DPLL_PIN_STATE_MAX, 184 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1) 185 }; 186 187 /** 188 * enum dpll_pin_operstate - defines possible operational states of a pin with 189 * respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE 190 * attribute 191 * @DPLL_PIN_OPERSTATE_ACTIVE: pin is qualified and actively used by the DPLL 192 * @DPLL_PIN_OPERSTATE_STANDBY: pin is qualified but not actively used by the 193 * DPLL 194 * @DPLL_PIN_OPERSTATE_NO_SIGNAL: pin does not have a valid signal 195 * @DPLL_PIN_OPERSTATE_QUAL_FAILED: pin signal failed qualification (e.g. 196 * frequency or phase monitor) 197 */ 198 enum dpll_pin_operstate { 199 DPLL_PIN_OPERSTATE_ACTIVE = 1, 200 DPLL_PIN_OPERSTATE_STANDBY, 201 DPLL_PIN_OPERSTATE_NO_SIGNAL, 202 DPLL_PIN_OPERSTATE_QUAL_FAILED, 203 204 /* private: */ 205 __DPLL_PIN_OPERSTATE_MAX, 206 DPLL_PIN_OPERSTATE_MAX = (__DPLL_PIN_OPERSTATE_MAX - 1) 207 }; 208 209 /** 210 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid 211 * flags on DPLL_A_PIN_CAPABILITIES attribute 212 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed 213 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed 214 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed 215 * @DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE: pin state can be set to 216 * connected regardless of current DPLL device mode, overriding the active 217 * input selection. Requires state-can-change to be set as well. 218 */ 219 enum dpll_pin_capabilities { 220 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1, 221 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2, 222 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4, 223 DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE = 8, 224 }; 225 226 #define DPLL_PHASE_OFFSET_DIVIDER 1000 227 #define DPLL_PIN_MEASURED_FREQUENCY_DIVIDER 1000 228 229 /** 230 * enum dpll_feature_state - Allow control (enable/disable) and status checking 231 * over features. 232 * @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled 233 * @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled 234 */ 235 enum dpll_feature_state { 236 DPLL_FEATURE_STATE_DISABLE, 237 DPLL_FEATURE_STATE_ENABLE, 238 }; 239 240 enum dpll_a { 241 DPLL_A_ID = 1, 242 DPLL_A_MODULE_NAME, 243 DPLL_A_PAD, 244 DPLL_A_CLOCK_ID, 245 DPLL_A_MODE, 246 DPLL_A_MODE_SUPPORTED, 247 DPLL_A_LOCK_STATUS, 248 DPLL_A_TEMP, 249 DPLL_A_TYPE, 250 DPLL_A_LOCK_STATUS_ERROR, 251 DPLL_A_CLOCK_QUALITY_LEVEL, 252 DPLL_A_PHASE_OFFSET_MONITOR, 253 DPLL_A_PHASE_OFFSET_AVG_FACTOR, 254 DPLL_A_FREQUENCY_MONITOR, 255 256 __DPLL_A_MAX, 257 DPLL_A_MAX = (__DPLL_A_MAX - 1) 258 }; 259 260 enum dpll_a_pin { 261 DPLL_A_PIN_ID = 1, 262 DPLL_A_PIN_PARENT_ID, 263 DPLL_A_PIN_MODULE_NAME, 264 DPLL_A_PIN_PAD, 265 DPLL_A_PIN_CLOCK_ID, 266 DPLL_A_PIN_BOARD_LABEL, 267 DPLL_A_PIN_PANEL_LABEL, 268 DPLL_A_PIN_PACKAGE_LABEL, 269 DPLL_A_PIN_TYPE, 270 DPLL_A_PIN_DIRECTION, 271 DPLL_A_PIN_FREQUENCY, 272 DPLL_A_PIN_FREQUENCY_SUPPORTED, 273 DPLL_A_PIN_FREQUENCY_MIN, 274 DPLL_A_PIN_FREQUENCY_MAX, 275 DPLL_A_PIN_PRIO, 276 DPLL_A_PIN_STATE, 277 DPLL_A_PIN_CAPABILITIES, 278 DPLL_A_PIN_PARENT_DEVICE, 279 DPLL_A_PIN_PARENT_PIN, 280 DPLL_A_PIN_PHASE_ADJUST_MIN, 281 DPLL_A_PIN_PHASE_ADJUST_MAX, 282 DPLL_A_PIN_PHASE_ADJUST, 283 DPLL_A_PIN_PHASE_OFFSET, 284 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 285 DPLL_A_PIN_ESYNC_FREQUENCY, 286 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, 287 DPLL_A_PIN_ESYNC_PULSE, 288 DPLL_A_PIN_REFERENCE_SYNC, 289 DPLL_A_PIN_PHASE_ADJUST_GRAN, 290 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 291 DPLL_A_PIN_MEASURED_FREQUENCY, 292 DPLL_A_PIN_OPERSTATE, 293 294 __DPLL_A_PIN_MAX, 295 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) 296 }; 297 298 enum dpll_cmd { 299 DPLL_CMD_DEVICE_ID_GET = 1, 300 DPLL_CMD_DEVICE_GET, 301 DPLL_CMD_DEVICE_SET, 302 DPLL_CMD_DEVICE_CREATE_NTF, 303 DPLL_CMD_DEVICE_DELETE_NTF, 304 DPLL_CMD_DEVICE_CHANGE_NTF, 305 DPLL_CMD_PIN_ID_GET, 306 DPLL_CMD_PIN_GET, 307 DPLL_CMD_PIN_SET, 308 DPLL_CMD_PIN_CREATE_NTF, 309 DPLL_CMD_PIN_DELETE_NTF, 310 DPLL_CMD_PIN_CHANGE_NTF, 311 312 __DPLL_CMD_MAX, 313 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1) 314 }; 315 316 #define DPLL_MCGRP_MONITOR "monitor" 317 318 #endif /* _UAPI_LINUX_DPLL_H */ 319