1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx95-clock.h" 13#include "imx95-pinfunc.h" 14#include "imx95-power.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 idle-states { 26 entry-method = "psci"; 27 28 cpu_pd_wait: cpu-pd-wait { 29 compatible = "arm,idle-state"; 30 arm,psci-suspend-param = <0x0010033>; 31 local-timer-stop; 32 entry-latency-us = <10000>; 33 exit-latency-us = <7000>; 34 min-residency-us = <27000>; 35 wakeup-latency-us = <15000>; 36 }; 37 }; 38 39 A55_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x0>; 43 enable-method = "psci"; 44 #cooling-cells = <2>; 45 cpu-idle-states = <&cpu_pd_wait>; 46 power-domains = <&scmi_perf IMX95_PERF_A55>; 47 power-domain-names = "perf"; 48 i-cache-size = <32768>; 49 i-cache-line-size = <64>; 50 i-cache-sets = <128>; 51 d-cache-size = <32768>; 52 d-cache-line-size = <64>; 53 d-cache-sets = <128>; 54 next-level-cache = <&l2_cache_l0>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 cpu-idle-states = <&cpu_pd_wait>; 64 power-domains = <&scmi_perf IMX95_PERF_A55>; 65 power-domain-names = "perf"; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l1>; 73 }; 74 75 A55_2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x200>; 79 enable-method = "psci"; 80 #cooling-cells = <2>; 81 cpu-idle-states = <&cpu_pd_wait>; 82 power-domains = <&scmi_perf IMX95_PERF_A55>; 83 power-domain-names = "perf"; 84 i-cache-size = <32768>; 85 i-cache-line-size = <64>; 86 i-cache-sets = <128>; 87 d-cache-size = <32768>; 88 d-cache-line-size = <64>; 89 d-cache-sets = <128>; 90 next-level-cache = <&l2_cache_l2>; 91 }; 92 93 A55_3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 enable-method = "psci"; 98 #cooling-cells = <2>; 99 cpu-idle-states = <&cpu_pd_wait>; 100 power-domains = <&scmi_perf IMX95_PERF_A55>; 101 power-domain-names = "perf"; 102 i-cache-size = <32768>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <128>; 105 d-cache-size = <32768>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <128>; 108 next-level-cache = <&l2_cache_l3>; 109 }; 110 111 A55_4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 power-domains = <&scmi_perf IMX95_PERF_A55>; 116 power-domain-names = "perf"; 117 enable-method = "psci"; 118 #cooling-cells = <2>; 119 cpu-idle-states = <&cpu_pd_wait>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l4>; 127 }; 128 129 A55_5: cpu@500 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a55"; 132 reg = <0x500>; 133 power-domains = <&scmi_perf IMX95_PERF_A55>; 134 power-domain-names = "perf"; 135 enable-method = "psci"; 136 #cooling-cells = <2>; 137 cpu-idle-states = <&cpu_pd_wait>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l5>; 145 }; 146 147 l2_cache_l0: l2-cache-l0 { 148 compatible = "cache"; 149 cache-size = <65536>; 150 cache-line-size = <64>; 151 cache-sets = <256>; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_cache>; 155 }; 156 157 l2_cache_l1: l2-cache-l1 { 158 compatible = "cache"; 159 cache-size = <65536>; 160 cache-line-size = <64>; 161 cache-sets = <256>; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_cache>; 165 }; 166 167 l2_cache_l2: l2-cache-l2 { 168 compatible = "cache"; 169 cache-size = <65536>; 170 cache-line-size = <64>; 171 cache-sets = <256>; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_cache>; 175 }; 176 177 l2_cache_l3: l2-cache-l3 { 178 compatible = "cache"; 179 cache-size = <65536>; 180 cache-line-size = <64>; 181 cache-sets = <256>; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&l3_cache>; 185 }; 186 187 l2_cache_l4: l2-cache-l4 { 188 compatible = "cache"; 189 cache-size = <65536>; 190 cache-line-size = <64>; 191 cache-sets = <256>; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_cache>; 195 }; 196 197 l2_cache_l5: l2-cache-l5 { 198 compatible = "cache"; 199 cache-size = <65536>; 200 cache-line-size = <64>; 201 cache-sets = <256>; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&l3_cache>; 205 }; 206 207 l3_cache: l3-cache { 208 compatible = "cache"; 209 cache-size = <524288>; 210 cache-line-size = <64>; 211 cache-sets = <512>; 212 cache-level = <3>; 213 cache-unified; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&A55_0>; 220 }; 221 222 core1 { 223 cpu = <&A55_1>; 224 }; 225 226 core2 { 227 cpu = <&A55_2>; 228 }; 229 230 core3 { 231 cpu = <&A55_3>; 232 }; 233 234 core4 { 235 cpu = <&A55_4>; 236 }; 237 238 core5 { 239 cpu = <&A55_5>; 240 }; 241 }; 242 }; 243 }; 244 245 dummy: clock-dummy { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <0>; 249 clock-output-names = "dummy"; 250 }; 251 252 clk_ext1: clock-ext1 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <133000000>; 256 clock-output-names = "clk_ext1"; 257 }; 258 259 sai1_mclk: clock-sai-mclk1 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency= <0>; 263 clock-output-names = "sai1_mclk"; 264 }; 265 266 sai2_mclk: clock-sai-mclk2 { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 clock-frequency= <0>; 270 clock-output-names = "sai2_mclk"; 271 }; 272 273 sai3_mclk: clock-sai-mclk3 { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 clock-frequency= <0>; 277 clock-output-names = "sai3_mclk"; 278 }; 279 280 sai4_mclk: clock-sai-mclk4 { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency= <0>; 284 clock-output-names = "sai4_mclk"; 285 }; 286 287 sai5_mclk: clock-sai-mclk5 { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency= <0>; 291 clock-output-names = "sai5_mclk"; 292 }; 293 294 clk_sys100m: clock-sys100m { 295 compatible = "fixed-clock"; 296 #clock-cells = <0>; 297 clock-frequency = <100000000>; 298 clock-output-names = "clk_sys100m"; 299 }; 300 301 osc_24m: clock-24m { 302 compatible = "fixed-clock"; 303 #clock-cells = <0>; 304 clock-frequency = <24000000>; 305 clock-output-names = "osc_24m"; 306 }; 307 308 sram1: sram@204c0000 { 309 compatible = "mmio-sram"; 310 reg = <0x0 0x204c0000 0x0 0x18000>; 311 ranges = <0x0 0x0 0x204c0000 0x18000>; 312 #address-cells = <1>; 313 #size-cells = <1>; 314 }; 315 316 firmware { 317 scmi { 318 compatible = "arm,scmi"; 319 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 320 shmem = <&scmi_buf0>, <&scmi_buf1>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 arm,max-rx-timeout-ms = <5000>; 324 325 scmi_devpd: protocol@11 { 326 reg = <0x11>; 327 #power-domain-cells = <1>; 328 }; 329 330 scmi_sys_power: protocol@12 { 331 reg = <0x12>; 332 }; 333 334 scmi_perf: protocol@13 { 335 reg = <0x13>; 336 #power-domain-cells = <1>; 337 }; 338 339 scmi_clk: protocol@14 { 340 reg = <0x14>; 341 #clock-cells = <1>; 342 }; 343 344 scmi_sensor: protocol@15 { 345 reg = <0x15>; 346 #thermal-sensor-cells = <1>; 347 }; 348 349 scmi_iomuxc: protocol@19 { 350 reg = <0x19>; 351 }; 352 353 scmi_bbm: protocol@81 { 354 reg = <0x81>; 355 }; 356 357 scmi_misc: protocol@84 { 358 reg = <0x84>; 359 }; 360 }; 361 }; 362 363 pmu { 364 compatible = "arm,cortex-a55-pmu"; 365 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 366 }; 367 368 thermal_zones: thermal-zones { 369 a55-thermal { 370 polling-delay-passive = <250>; 371 polling-delay = <2000>; 372 thermal-sensors = <&scmi_sensor 1>; 373 374 trips { 375 cpu_alert0: trip0 { 376 temperature = <105000>; 377 hysteresis = <2000>; 378 type = "passive"; 379 }; 380 381 cpu_crit0: trip1 { 382 temperature = <125000>; 383 hysteresis = <2000>; 384 type = "critical"; 385 }; 386 }; 387 388 cooling-maps { 389 map0 { 390 trip = <&cpu_alert0>; 391 cooling-device = 392 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 393 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 397 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 398 }; 399 }; 400 }; 401 402 ana-thermal { 403 polling-delay-passive = <250>; 404 polling-delay = <2000>; 405 thermal-sensors = <&scmi_sensor 0>; 406 trips { 407 ana_alert: trip0 { 408 temperature = <105000>; 409 hysteresis = <2000>; 410 type = "passive"; 411 }; 412 413 ana_crit0: trip1 { 414 temperature = <125000>; 415 hysteresis = <2000>; 416 type = "critical"; 417 }; 418 }; 419 420 cooling-maps { 421 map0 { 422 trip = <&ana_alert>; 423 cooling-device = 424 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 425 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 426 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 427 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 428 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 429 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 430 }; 431 }; 432 }; 433 }; 434 435 psci { 436 compatible = "arm,psci-1.0"; 437 method = "smc"; 438 }; 439 440 timer { 441 compatible = "arm,armv8-timer"; 442 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 443 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 444 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 445 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 446 clock-frequency = <24000000>; 447 arm,no-tick-in-suspend; 448 interrupt-parent = <&gic>; 449 }; 450 451 gic: interrupt-controller@48000000 { 452 compatible = "arm,gic-v3"; 453 reg = <0 0x48000000 0 0x10000>, 454 <0 0x48060000 0 0xc0000>; 455 #address-cells = <2>; 456 #size-cells = <2>; 457 #interrupt-cells = <3>; 458 interrupt-controller; 459 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-parent = <&gic>; 461 dma-noncoherent; 462 ranges; 463 464 its: msi-controller@48040000 { 465 compatible = "arm,gic-v3-its"; 466 reg = <0 0x48040000 0 0x20000>; 467 msi-controller; 468 #msi-cells = <1>; 469 dma-noncoherent; 470 }; 471 }; 472 473 usbphynop: usbphynop { 474 compatible = "usb-nop-xceiv"; 475 clocks = <&scmi_clk IMX95_CLK_HSIO>; 476 clock-names = "main_clk"; 477 #phy-cells = <0>; 478 }; 479 480 soc { 481 compatible = "simple-bus"; 482 #address-cells = <2>; 483 #size-cells = <2>; 484 ranges; 485 486 aips2: bus@42000000 { 487 compatible = "fsl,aips-bus", "simple-bus"; 488 reg = <0x0 0x42000000 0x0 0x800000>; 489 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 490 <0x28000000 0x0 0x28000000 0x10000000>; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 494 edma2: dma-controller@42000000 { 495 compatible = "fsl,imx95-edma5"; 496 reg = <0x42000000 0x210000>; 497 #dma-cells = <3>; 498 dma-channels = <64>; 499 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 564 clock-names = "dma"; 565 }; 566 567 edma3: dma-controller@42210000 { 568 compatible = "fsl,imx95-edma5"; 569 reg = <0x42210000 0x210000>; 570 #dma-cells = <3>; 571 dma-channels = <64>; 572 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 637 clock-names = "dma"; 638 }; 639 640 mu7: mailbox@42430000 { 641 compatible = "fsl,imx95-mu"; 642 reg = <0x42430000 0x10000>; 643 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 645 #mbox-cells = <2>; 646 status = "disabled"; 647 }; 648 649 wdog3: watchdog@42490000 { 650 compatible = "fsl,imx93-wdt"; 651 reg = <0x42490000 0x10000>; 652 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 654 timeout-sec = <40>; 655 status = "disabled"; 656 }; 657 658 tpm3: pwm@424e0000 { 659 compatible = "fsl,imx7ulp-pwm"; 660 reg = <0x424e0000 0x1000>; 661 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 662 #pwm-cells = <3>; 663 status = "disabled"; 664 }; 665 666 tpm4: pwm@424f0000 { 667 compatible = "fsl,imx7ulp-pwm"; 668 reg = <0x424f0000 0x1000>; 669 clocks = <&scmi_clk IMX95_CLK_TPM4>; 670 #pwm-cells = <3>; 671 status = "disabled"; 672 }; 673 674 tpm5: pwm@42500000 { 675 compatible = "fsl,imx7ulp-pwm"; 676 reg = <0x42500000 0x1000>; 677 clocks = <&scmi_clk IMX95_CLK_TPM5>; 678 #pwm-cells = <3>; 679 status = "disabled"; 680 }; 681 682 tpm6: pwm@42510000 { 683 compatible = "fsl,imx7ulp-pwm"; 684 reg = <0x42510000 0x1000>; 685 clocks = <&scmi_clk IMX95_CLK_TPM6>; 686 #pwm-cells = <3>; 687 status = "disabled"; 688 }; 689 690 i3c2: i3c@42520000 { 691 compatible = "silvaco,i3c-master-v1"; 692 reg = <0x42520000 0x10000>; 693 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <3>; 695 #size-cells = <0>; 696 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 697 <&scmi_clk IMX95_CLK_I3C2>, 698 <&scmi_clk IMX95_CLK_I3C2SLOW>; 699 clock-names = "pclk", "fast_clk", "slow_clk"; 700 status = "disabled"; 701 }; 702 703 lpi2c3: i2c@42530000 { 704 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 705 reg = <0x42530000 0x10000>; 706 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 708 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 709 clock-names = "per", "ipg"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 713 dma-names = "tx", "rx"; 714 status = "disabled"; 715 }; 716 717 lpi2c4: i2c@42540000 { 718 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 719 reg = <0x42540000 0x10000>; 720 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 722 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 723 clock-names = "per", "ipg"; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 727 dma-names = "tx", "rx"; 728 status = "disabled"; 729 }; 730 731 lpspi3: spi@42550000 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 735 reg = <0x42550000 0x10000>; 736 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 738 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 739 clock-names = "per", "ipg"; 740 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 741 dma-names = "tx", "rx"; 742 status = "disabled"; 743 }; 744 745 lpspi4: spi@42560000 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 749 reg = <0x42560000 0x10000>; 750 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 752 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 753 clock-names = "per", "ipg"; 754 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 755 dma-names = "tx", "rx"; 756 status = "disabled"; 757 }; 758 759 lpuart3: serial@42570000 { 760 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 761 "fsl,imx7ulp-lpuart"; 762 reg = <0x42570000 0x1000>; 763 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 765 clock-names = "ipg"; 766 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 767 dma-names = "rx", "tx"; 768 status = "disabled"; 769 }; 770 771 lpuart4: serial@42580000 { 772 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 773 "fsl,imx7ulp-lpuart"; 774 reg = <0x42580000 0x1000>; 775 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 777 clock-names = "ipg"; 778 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 779 dma-names = "rx", "tx"; 780 status = "disabled"; 781 }; 782 783 lpuart5: serial@42590000 { 784 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 785 "fsl,imx7ulp-lpuart"; 786 reg = <0x42590000 0x1000>; 787 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 789 clock-names = "ipg"; 790 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 791 dma-names = "rx", "tx"; 792 status = "disabled"; 793 }; 794 795 lpuart6: serial@425a0000 { 796 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 797 "fsl,imx7ulp-lpuart"; 798 reg = <0x425a0000 0x1000>; 799 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 801 clock-names = "ipg"; 802 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 803 dma-names = "rx", "tx"; 804 status = "disabled"; 805 }; 806 807 flexcan2: can@425b0000 { 808 compatible = "fsl,imx95-flexcan"; 809 reg = <0x425b0000 0x10000>; 810 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 812 <&scmi_clk IMX95_CLK_CAN2>; 813 clock-names = "ipg", "per"; 814 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 815 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 816 assigned-clock-rates = <40000000>; 817 fsl,clk-source = /bits/ 8 <0>; 818 status = "disabled"; 819 }; 820 821 flexcan3: can@42600000 { 822 compatible = "fsl,imx95-flexcan"; 823 reg = <0x42600000 0x10000>; 824 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 826 <&scmi_clk IMX95_CLK_CAN3>; 827 clock-names = "ipg", "per"; 828 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 829 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 830 assigned-clock-rates = <40000000>; 831 fsl,clk-source = /bits/ 8 <0>; 832 status = "disabled"; 833 }; 834 835 flexspi1: spi@425e0000 { 836 compatible = "nxp,imx8mm-fspi"; 837 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 838 reg-names = "fspi_base", "fspi_mmap"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 843 <&scmi_clk IMX95_CLK_FLEXSPI1>; 844 clock-names = "fspi_en", "fspi"; 845 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 846 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 847 assigned-clock-rates = <200000000>; 848 status = "disabled"; 849 }; 850 851 sai3: sai@42650000 { 852 compatible = "fsl,imx95-sai"; 853 reg = <0x42650000 0x10000>; 854 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 856 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 857 <&dummy>; 858 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 859 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 860 dma-names = "rx", "tx"; 861 status = "disabled"; 862 }; 863 864 sai4: sai@42660000 { 865 compatible = "fsl,imx95-sai"; 866 reg = <0x42660000 0x10000>; 867 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 869 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 870 <&dummy>; 871 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 872 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 873 dma-names = "rx", "tx"; 874 status = "disabled"; 875 }; 876 877 sai5: sai@42670000 { 878 compatible = "fsl,imx95-sai"; 879 reg = <0x42670000 0x10000>; 880 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 882 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 883 <&dummy>; 884 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 885 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 xcvr: xcvr@42680000 { 891 compatible = "fsl,imx95-xcvr"; 892 reg = <0x42680000 0x800>, <0x42680800 0x400>, 893 <0x42680c00 0x080>, <0x42680e00 0x080>; 894 reg-names = "ram", "regs", "rxfifo", "txfifo"; 895 interrupts = /* XCVR IRQ 0 */ 896 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 897 /* XCVR IRQ 1 */ 898 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 900 <&scmi_clk IMX95_CLK_SPDIF>, 901 <&dummy>, 902 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 903 clock-names = "ipg", "phy", "spba", "pll_ipg"; 904 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 905 dma-names = "rx", "tx"; 906 status = "disabled"; 907 }; 908 909 lpuart7: serial@42690000 { 910 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 911 "fsl,imx7ulp-lpuart"; 912 reg = <0x42690000 0x1000>; 913 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 915 clock-names = "ipg"; 916 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; 917 dma-names = "rx", "tx"; 918 status = "disabled"; 919 }; 920 921 lpuart8: serial@426a0000 { 922 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 923 "fsl,imx7ulp-lpuart"; 924 reg = <0x426a0000 0x1000>; 925 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 927 clock-names = "ipg"; 928 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; 929 dma-names = "rx", "tx"; 930 status = "disabled"; 931 }; 932 933 lpi2c5: i2c@426b0000 { 934 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 935 reg = <0x426b0000 0x10000>; 936 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 938 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 939 clock-names = "per", "ipg"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 943 dma-names = "tx", "rx"; 944 status = "disabled"; 945 }; 946 947 lpi2c6: i2c@426c0000 { 948 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 949 reg = <0x426c0000 0x10000>; 950 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 952 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 953 clock-names = "per", "ipg"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 957 dma-names = "tx", "rx"; 958 status = "disabled"; 959 }; 960 961 lpi2c7: i2c@426d0000 { 962 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 963 reg = <0x426d0000 0x10000>; 964 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 966 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 967 clock-names = "per", "ipg"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 lpi2c8: i2c@426e0000 { 976 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 977 reg = <0x426e0000 0x10000>; 978 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 980 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 981 clock-names = "per", "ipg"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 lpspi5: spi@426f0000 { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 993 reg = <0x426f0000 0x10000>; 994 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 996 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 997 clock-names = "per", "ipg"; 998 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 999 dma-names = "tx", "rx"; 1000 status = "disabled"; 1001 }; 1002 1003 lpspi6: spi@42700000 { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1007 reg = <0x42700000 0x10000>; 1008 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1010 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1011 clock-names = "per", "ipg"; 1012 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 lpspi7: spi@42710000 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1021 reg = <0x42710000 0x10000>; 1022 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1024 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1025 clock-names = "per", "ipg"; 1026 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1027 dma-names = "tx", "rx"; 1028 status = "disabled"; 1029 }; 1030 1031 lpspi8: spi@42720000 { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1035 reg = <0x42720000 0x10000>; 1036 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1038 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1039 clock-names = "per", "ipg"; 1040 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1041 dma-names = "tx", "rx"; 1042 status = "disabled"; 1043 }; 1044 1045 mu8: mailbox@42730000 { 1046 compatible = "fsl,imx95-mu"; 1047 reg = <0x42730000 0x10000>; 1048 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1050 #mbox-cells = <2>; 1051 status = "disabled"; 1052 }; 1053 1054 flexcan4: can@427c0000 { 1055 compatible = "fsl,imx95-flexcan"; 1056 reg = <0x427c0000 0x10000>; 1057 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1059 <&scmi_clk IMX95_CLK_CAN4>; 1060 clock-names = "ipg", "per"; 1061 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1062 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1063 assigned-clock-rates = <40000000>; 1064 fsl,clk-source = /bits/ 8 <0>; 1065 status = "disabled"; 1066 }; 1067 1068 flexcan5: can@427d0000 { 1069 compatible = "fsl,imx95-flexcan"; 1070 reg = <0x427d0000 0x10000>; 1071 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1073 <&scmi_clk IMX95_CLK_CAN5>; 1074 clock-names = "ipg", "per"; 1075 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1076 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1077 assigned-clock-rates = <40000000>; 1078 fsl,clk-source = /bits/ 8 <0>; 1079 status = "disabled"; 1080 }; 1081 }; 1082 1083 aips3: bus@42800000 { 1084 compatible = "fsl,aips-bus", "simple-bus"; 1085 reg = <0 0x42800000 0 0x800000>; 1086 #address-cells = <1>; 1087 #size-cells = <1>; 1088 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1089 1090 usdhc1: mmc@42850000 { 1091 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1092 reg = <0x42850000 0x10000>; 1093 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1095 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1096 <&scmi_clk IMX95_CLK_USDHC1>; 1097 clock-names = "ipg", "ahb", "per"; 1098 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1099 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1100 assigned-clock-rates = <400000000>; 1101 bus-width = <8>; 1102 fsl,tuning-start-tap = <1>; 1103 fsl,tuning-step= <2>; 1104 status = "disabled"; 1105 }; 1106 1107 usdhc2: mmc@42860000 { 1108 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1109 reg = <0x42860000 0x10000>; 1110 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1112 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1113 <&scmi_clk IMX95_CLK_USDHC2>; 1114 clock-names = "ipg", "ahb", "per"; 1115 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1116 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1117 assigned-clock-rates = <400000000>; 1118 bus-width = <4>; 1119 fsl,tuning-start-tap = <1>; 1120 fsl,tuning-step= <2>; 1121 status = "disabled"; 1122 }; 1123 1124 usdhc3: mmc@428b0000 { 1125 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1126 reg = <0x428b0000 0x10000>; 1127 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1129 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1130 <&scmi_clk IMX95_CLK_USDHC3>; 1131 clock-names = "ipg", "ahb", "per"; 1132 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1133 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1134 assigned-clock-rates = <400000000>; 1135 bus-width = <4>; 1136 fsl,tuning-start-tap = <1>; 1137 fsl,tuning-step= <2>; 1138 status = "disabled"; 1139 }; 1140 }; 1141 1142 gpio2: gpio@43810000 { 1143 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1144 reg = <0x0 0x43810000 0x0 0x1000>; 1145 gpio-controller; 1146 #gpio-cells = <2>; 1147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1149 interrupt-controller; 1150 #interrupt-cells = <2>; 1151 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1152 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1153 clock-names = "gpio", "port"; 1154 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1155 }; 1156 1157 gpio3: gpio@43820000 { 1158 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1159 reg = <0x0 0x43820000 0x0 0x1000>; 1160 gpio-controller; 1161 #gpio-cells = <2>; 1162 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-controller; 1165 #interrupt-cells = <2>; 1166 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1167 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1168 clock-names = "gpio", "port"; 1169 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1170 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1171 }; 1172 1173 gpio4: gpio@43840000 { 1174 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1175 reg = <0x0 0x43840000 0x0 0x1000>; 1176 gpio-controller; 1177 #gpio-cells = <2>; 1178 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1180 interrupt-controller; 1181 #interrupt-cells = <2>; 1182 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1183 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1184 clock-names = "gpio", "port"; 1185 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1186 }; 1187 1188 gpio5: gpio@43850000 { 1189 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1190 reg = <0x0 0x43850000 0x0 0x1000>; 1191 gpio-controller; 1192 #gpio-cells = <2>; 1193 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-controller; 1196 #interrupt-cells = <2>; 1197 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1198 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1199 clock-names = "gpio", "port"; 1200 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1201 }; 1202 1203 aips1: bus@44000000 { 1204 compatible = "fsl,aips-bus", "simple-bus"; 1205 reg = <0x0 0x44000000 0x0 0x800000>; 1206 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1207 #address-cells = <1>; 1208 #size-cells = <1>; 1209 1210 edma1: dma-controller@44000000 { 1211 compatible = "fsl,imx93-edma3"; 1212 reg = <0x44000000 0x200000>; 1213 #dma-cells = <3>; 1214 dma-channels = <31>; 1215 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1247 clock-names = "dma"; 1248 }; 1249 1250 mu1: mailbox@44220000 { 1251 compatible = "fsl,imx95-mu"; 1252 reg = <0x44220000 0x10000>; 1253 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1255 #mbox-cells = <2>; 1256 status = "disabled"; 1257 }; 1258 1259 tpm1: pwm@44310000 { 1260 compatible = "fsl,imx7ulp-pwm"; 1261 reg = <0x44310000 0x1000>; 1262 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1263 #pwm-cells = <3>; 1264 status = "disabled"; 1265 }; 1266 1267 tpm2: pwm@44320000 { 1268 compatible = "fsl,imx7ulp-pwm"; 1269 reg = <0x44320000 0x1000>; 1270 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1271 #pwm-cells = <3>; 1272 status = "disabled"; 1273 }; 1274 1275 i3c1: i3c@44330000 { 1276 compatible = "silvaco,i3c-master-v1"; 1277 reg = <0x44330000 0x10000>; 1278 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1279 #address-cells = <3>; 1280 #size-cells = <0>; 1281 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1282 <&scmi_clk IMX95_CLK_I3C1>, 1283 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1284 clock-names = "pclk", "fast_clk", "slow_clk"; 1285 status = "disabled"; 1286 }; 1287 1288 lpi2c1: i2c@44340000 { 1289 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1290 reg = <0x44340000 0x10000>; 1291 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1293 <&scmi_clk IMX95_CLK_BUSAON>; 1294 clock-names = "per", "ipg"; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1298 dma-names = "tx", "rx"; 1299 status = "disabled"; 1300 }; 1301 1302 lpi2c2: i2c@44350000 { 1303 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1304 reg = <0x44350000 0x10000>; 1305 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1307 <&scmi_clk IMX95_CLK_BUSAON>; 1308 clock-names = "per", "ipg"; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 lpspi1: spi@44360000 { 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1320 reg = <0x44360000 0x10000>; 1321 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1323 <&scmi_clk IMX95_CLK_BUSAON>; 1324 clock-names = "per", "ipg"; 1325 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1326 dma-names = "tx", "rx"; 1327 status = "disabled"; 1328 }; 1329 1330 lpspi2: spi@44370000 { 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1334 reg = <0x44370000 0x10000>; 1335 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1337 <&scmi_clk IMX95_CLK_BUSAON>; 1338 clock-names = "per", "ipg"; 1339 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1340 dma-names = "tx", "rx"; 1341 status = "disabled"; 1342 }; 1343 1344 lpuart1: serial@44380000 { 1345 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1346 "fsl,imx7ulp-lpuart"; 1347 reg = <0x44380000 0x1000>; 1348 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1350 clock-names = "ipg"; 1351 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1352 dma-names = "rx", "tx"; 1353 status = "disabled"; 1354 }; 1355 1356 lpuart2: serial@44390000 { 1357 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1358 "fsl,imx7ulp-lpuart"; 1359 reg = <0x44390000 0x1000>; 1360 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1362 clock-names = "ipg"; 1363 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1364 dma-names = "rx", "tx"; 1365 status = "disabled"; 1366 }; 1367 1368 flexcan1: can@443a0000 { 1369 compatible = "fsl,imx95-flexcan"; 1370 reg = <0x443a0000 0x10000>; 1371 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1373 <&scmi_clk IMX95_CLK_CAN1>; 1374 clock-names = "ipg", "per"; 1375 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1376 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1377 assigned-clock-rates = <40000000>; 1378 fsl,clk-source = /bits/ 8 <0>; 1379 status = "disabled"; 1380 }; 1381 1382 sai1: sai@443b0000 { 1383 compatible = "fsl,imx95-sai"; 1384 reg = <0x443b0000 0x10000>; 1385 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1387 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1388 <&dummy>; 1389 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1390 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1391 dma-names = "rx", "tx"; 1392 status = "disabled"; 1393 }; 1394 1395 micfil: micfil@44520000 { 1396 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1397 reg = <0x44520000 0x10000>; 1398 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1402 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1403 <&scmi_clk IMX95_CLK_PDM>, 1404 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1405 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1406 <&dummy>; 1407 clock-names = "ipg_clk", "ipg_clk_app", 1408 "pll8k", "pll11k", "clkext3"; 1409 dmas = <&edma1 6 0 5>; 1410 dma-names = "rx"; 1411 status = "disabled"; 1412 }; 1413 1414 adc1: adc@44530000 { 1415 compatible = "nxp,imx93-adc"; 1416 reg = <0x44530000 0x10000>; 1417 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&scmi_clk IMX95_CLK_ADC>; 1421 clock-names = "ipg"; 1422 #io-channel-cells = <1>; 1423 status = "disabled"; 1424 }; 1425 1426 mu2: mailbox@445b0000 { 1427 compatible = "fsl,imx95-mu"; 1428 reg = <0x445b0000 0x1000>; 1429 ranges; 1430 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <1>; 1433 #mbox-cells = <2>; 1434 1435 sram0: sram@445b1000 { 1436 compatible = "mmio-sram"; 1437 reg = <0x445b1000 0x400>; 1438 ranges = <0x0 0x445b1000 0x400>; 1439 #address-cells = <1>; 1440 #size-cells = <1>; 1441 1442 scmi_buf0: scmi-sram-section@0 { 1443 compatible = "arm,scmi-shmem"; 1444 reg = <0x0 0x80>; 1445 }; 1446 1447 scmi_buf1: scmi-sram-section@80 { 1448 compatible = "arm,scmi-shmem"; 1449 reg = <0x80 0x80>; 1450 }; 1451 }; 1452 1453 }; 1454 1455 mu3: mailbox@445d0000 { 1456 compatible = "fsl,imx95-mu"; 1457 reg = <0x445d0000 0x10000>; 1458 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1460 #mbox-cells = <2>; 1461 status = "disabled"; 1462 }; 1463 1464 mu4: mailbox@445f0000 { 1465 compatible = "fsl,imx95-mu"; 1466 reg = <0x445f0000 0x10000>; 1467 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1469 #mbox-cells = <2>; 1470 status = "disabled"; 1471 }; 1472 1473 mu6: mailbox@44630000 { 1474 compatible = "fsl,imx95-mu"; 1475 reg = <0x44630000 0x10000>; 1476 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1478 #mbox-cells = <2>; 1479 status = "disabled"; 1480 }; 1481 }; 1482 1483 mailbox@47320000 { 1484 compatible = "fsl,imx95-mu-v2x"; 1485 reg = <0x0 0x47320000 0x0 0x10000>; 1486 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1487 #mbox-cells = <2>; 1488 }; 1489 1490 mailbox@47350000 { 1491 compatible = "fsl,imx95-mu-v2x"; 1492 reg = <0x0 0x47350000 0x0 0x10000>; 1493 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1494 #mbox-cells = <2>; 1495 }; 1496 1497 /* GPIO1 is under exclusive control of System Manager */ 1498 gpio1: gpio@47400000 { 1499 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1500 reg = <0x0 0x47400000 0x0 0x1000>; 1501 gpio-controller; 1502 #gpio-cells = <2>; 1503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1505 interrupt-controller; 1506 #interrupt-cells = <2>; 1507 clocks = <&scmi_clk IMX95_CLK_M33>, 1508 <&scmi_clk IMX95_CLK_M33>; 1509 clock-names = "gpio", "port"; 1510 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1511 status = "disabled"; 1512 }; 1513 1514 elemu0: mailbox@47520000 { 1515 compatible = "fsl,imx95-mu-ele"; 1516 reg = <0x0 0x47520000 0x0 0x10000>; 1517 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1518 #mbox-cells = <2>; 1519 status = "disabled"; 1520 }; 1521 1522 elemu1: mailbox@47530000 { 1523 compatible = "fsl,imx95-mu-ele"; 1524 reg = <0x0 0x47530000 0x0 0x10000>; 1525 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1526 #mbox-cells = <2>; 1527 status = "disabled"; 1528 }; 1529 1530 elemu2: mailbox@47540000 { 1531 compatible = "fsl,imx95-mu-ele"; 1532 reg = <0x0 0x47540000 0x0 0x10000>; 1533 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1534 #mbox-cells = <2>; 1535 status = "disabled"; 1536 }; 1537 1538 elemu3: mailbox@47550000 { 1539 compatible = "fsl,imx95-mu-ele"; 1540 reg = <0x0 0x47550000 0x0 0x10000>; 1541 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1542 #mbox-cells = <2>; 1543 }; 1544 1545 elemu4: mailbox@47560000 { 1546 compatible = "fsl,imx95-mu-ele"; 1547 reg = <0x0 0x47560000 0x0 0x10000>; 1548 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1549 #mbox-cells = <2>; 1550 status = "disabled"; 1551 }; 1552 1553 elemu5: mailbox@47570000 { 1554 compatible = "fsl,imx95-mu-ele"; 1555 reg = <0x0 0x47570000 0x0 0x10000>; 1556 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1557 #mbox-cells = <2>; 1558 status = "disabled"; 1559 }; 1560 1561 aips4: bus@49000000 { 1562 compatible = "fsl,aips-bus", "simple-bus"; 1563 reg = <0x0 0x49000000 0x0 0x800000>; 1564 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1565 #address-cells = <1>; 1566 #size-cells = <1>; 1567 1568 smmu: iommu@490d0000 { 1569 compatible = "arm,smmu-v3"; 1570 reg = <0x490d0000 0x100000>; 1571 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1572 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1573 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1574 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1575 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1576 #iommu-cells = <1>; 1577 status = "disabled"; 1578 }; 1579 }; 1580 1581 usb3: usb@4c010010 { 1582 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1583 reg = <0x0 0x4c010010 0x0 0x04>, 1584 <0x0 0x4c1f0000 0x0 0x20>; 1585 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1586 <&scmi_clk IMX95_CLK_32K>; 1587 clock-names = "hsio", "suspend"; 1588 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <2>; 1590 #size-cells = <2>; 1591 ranges; 1592 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1593 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1594 status = "disabled"; 1595 1596 usb3_dwc3: usb@4c100000 { 1597 compatible = "snps,dwc3"; 1598 reg = <0x0 0x4c100000 0x0 0x10000>; 1599 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1600 <&scmi_clk IMX95_CLK_24M>, 1601 <&scmi_clk IMX95_CLK_32K>; 1602 clock-names = "bus_early", "ref", "suspend"; 1603 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1604 phys = <&usb3_phy>, <&usb3_phy>; 1605 phy-names = "usb2-phy", "usb3-phy"; 1606 snps,gfladj-refclk-lpm-sel-quirk; 1607 snps,parkmode-disable-ss-quirk; 1608 iommus = <&smmu 0xe>; 1609 }; 1610 }; 1611 1612 hsio_blk_ctl: syscon@4c0100c0 { 1613 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1614 reg = <0x0 0x4c0100c0 0x0 0x1>; 1615 #clock-cells = <1>; 1616 clocks = <&clk_sys100m>; 1617 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1618 }; 1619 1620 usb3_phy: phy@4c1f0040 { 1621 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1622 reg = <0x0 0x4c1f0040 0x0 0x40>, 1623 <0x0 0x4c1fc000 0x0 0x100>; 1624 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1625 clock-names = "phy"; 1626 #phy-cells = <0>; 1627 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1628 status = "disabled"; 1629 }; 1630 1631 usb2: usb@4c200000 { 1632 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1633 reg = <0x0 0x4c200000 0x0 0x200>; 1634 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1637 <&scmi_clk IMX95_CLK_32K>; 1638 clock-names = "usb_ctrl_root", "usb_wakeup"; 1639 iommus = <&smmu 0xf>; 1640 phys = <&usbphynop>; 1641 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1642 fsl,usbmisc = <&usbmisc 0>; 1643 status = "disabled"; 1644 }; 1645 1646 usbmisc: usbmisc@4c200200 { 1647 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", 1648 "fsl,imx6q-usbmisc"; 1649 reg = <0x0 0x4c200200 0x0 0x200>, 1650 <0x0 0x4c010014 0x0 0x04>; 1651 #index-cells = <1>; 1652 }; 1653 1654 pcie0: pcie@4c300000 { 1655 compatible = "fsl,imx95-pcie"; 1656 reg = <0 0x4c300000 0 0x10000>, 1657 <0 0x60100000 0 0xfe00000>, 1658 <0 0x4c360000 0 0x10000>, 1659 <0 0x4c340000 0 0x4000>; 1660 reg-names = "dbi", "config", "atu", "app"; 1661 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1662 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1663 #address-cells = <3>; 1664 #size-cells = <2>; 1665 device_type = "pci"; 1666 linux,pci-domain = <0>; 1667 bus-range = <0x00 0xff>; 1668 num-lanes = <1>; 1669 num-viewport = <8>; 1670 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1671 interrupt-names = "msi"; 1672 #interrupt-cells = <1>; 1673 interrupt-map-mask = <0 0 0 0x7>; 1674 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1675 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1676 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1677 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1678 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1679 <&scmi_clk IMX95_CLK_HSIOPLL>, 1680 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1681 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1682 <&hsio_blk_ctl 0>; 1683 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1684 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1685 <&scmi_clk IMX95_CLK_HSIOPLL>, 1686 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1687 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1688 assigned-clock-parents = <0>, <0>, 1689 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1690 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1691 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1692 msi-map = <0x0 &its 0x10 0x1>, 1693 <0x100 &its 0x11 0x7>; 1694 iommu-map = <0x000 &smmu 0x10 0x1>, 1695 <0x100 &smmu 0x11 0x7>; 1696 iommu-map-mask = <0x1ff>; 1697 fsl,max-link-speed = <3>; 1698 status = "disabled"; 1699 }; 1700 1701 pcie0_ep: pcie-ep@4c300000 { 1702 compatible = "fsl,imx95-pcie-ep"; 1703 reg = <0 0x4c300000 0 0x10000>, 1704 <0 0x4c360000 0 0x1000>, 1705 <0 0x4c320000 0 0x1000>, 1706 <0 0x4c340000 0 0x4000>, 1707 <0 0x4c370000 0 0x10000>, 1708 <0x9 0 1 0>; 1709 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1710 num-lanes = <1>; 1711 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1712 interrupt-names = "dma"; 1713 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1714 <&scmi_clk IMX95_CLK_HSIOPLL>, 1715 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1716 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1717 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1718 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1719 <&scmi_clk IMX95_CLK_HSIOPLL>, 1720 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1721 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1722 assigned-clock-parents = <0>, <0>, 1723 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1724 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1725 status = "disabled"; 1726 }; 1727 1728 pcie1: pcie@4c380000 { 1729 compatible = "fsl,imx95-pcie"; 1730 reg = <0 0x4c380000 0 0x10000>, 1731 <8 0x80100000 0 0xfe00000>, 1732 <0 0x4c3e0000 0 0x10000>, 1733 <0 0x4c3c0000 0 0x4000>; 1734 reg-names = "dbi", "config", "atu", "app"; 1735 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1736 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1737 #address-cells = <3>; 1738 #size-cells = <2>; 1739 device_type = "pci"; 1740 linux,pci-domain = <1>; 1741 bus-range = <0x00 0xff>; 1742 num-lanes = <1>; 1743 num-viewport = <8>; 1744 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1745 interrupt-names = "msi"; 1746 #interrupt-cells = <1>; 1747 interrupt-map-mask = <0 0 0 0x7>; 1748 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1749 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1750 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1751 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1752 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1753 <&scmi_clk IMX95_CLK_HSIOPLL>, 1754 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1755 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1756 <&hsio_blk_ctl 0>; 1757 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1758 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1759 <&scmi_clk IMX95_CLK_HSIOPLL>, 1760 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1761 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1762 assigned-clock-parents = <0>, <0>, 1763 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1764 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1765 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1766 msi-map = <0x0 &its 0x98 0x1>, 1767 <0x100 &its 0x99 0x7>; 1768 msi-map-mask = <0x1ff>; 1769 /* smmu have not Devid(BIT[7:6]) */ 1770 iommu-map = <0x000 &smmu 0x18 0x1>, 1771 <0x100 &smmu 0x19 0x7>; 1772 iommu-map-mask = <0x1ff>; 1773 fsl,max-link-speed = <3>; 1774 status = "disabled"; 1775 }; 1776 1777 pcie1_ep: pcie-ep@4c380000 { 1778 compatible = "fsl,imx95-pcie-ep"; 1779 reg = <0 0x4c380000 0 0x10000>, 1780 <0 0x4c3e0000 0 0x1000>, 1781 <0 0x4c3a0000 0 0x1000>, 1782 <0 0x4c3c0000 0 0x4000>, 1783 <0 0x4c3f0000 0 0x10000>, 1784 <0xa 0 1 0>; 1785 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1786 num-lanes = <1>; 1787 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1788 interrupt-names = "dma"; 1789 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1790 <&scmi_clk IMX95_CLK_HSIOPLL>, 1791 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1792 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1793 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1794 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1795 <&scmi_clk IMX95_CLK_HSIOPLL>, 1796 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1797 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1798 assigned-clock-parents = <0>, <0>, 1799 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1800 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1801 status = "disabled"; 1802 }; 1803 1804 netcmix_blk_ctrl: syscon@4c810000 { 1805 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 1806 reg = <0x0 0x4c810000 0x0 0x8>; 1807 #clock-cells = <1>; 1808 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1809 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1810 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1811 assigned-clock-rates = <133333333>; 1812 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1813 status = "disabled"; 1814 }; 1815 1816 sai2: sai@4c880000 { 1817 compatible = "fsl,imx95-sai"; 1818 reg = <0x0 0x4c880000 0x0 0x10000>; 1819 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 1821 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 1822 <&dummy>; 1823 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1824 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1825 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1826 dma-names = "rx", "tx"; 1827 status = "disabled"; 1828 }; 1829 1830 netc_blk_ctrl: system-controller@4cde0000 { 1831 compatible = "nxp,imx95-netc-blk-ctrl"; 1832 reg = <0x0 0x4cde0000 0x0 0x10000>, 1833 <0x0 0x4cdf0000 0x0 0x10000>, 1834 <0x0 0x4c81000c 0x0 0x18>; 1835 reg-names = "ierb", "prb", "netcmix"; 1836 #address-cells = <2>; 1837 #size-cells = <2>; 1838 ranges; 1839 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1840 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 1841 <&scmi_clk IMX95_CLK_ENETREF>; 1842 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 1843 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 1844 assigned-clock-rates = <666666666>, <250000000>; 1845 clocks = <&scmi_clk IMX95_CLK_ENET>; 1846 clock-names = "ipg"; 1847 status = "disabled"; 1848 1849 netc_bus0: pcie@4ca00000 { 1850 compatible = "pci-host-ecam-generic"; 1851 reg = <0x0 0x4ca00000 0x0 0x100000>; 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 device_type = "pci"; 1855 bus-range = <0x0 0x0>; 1856 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 1857 <0x10 &its 0x61 0x1>, //ENETC0 VF0 1858 <0x20 &its 0x62 0x1>, //ENETC0 VF1 1859 <0x40 &its 0x63 0x1>, //ENETC1 PF 1860 <0x80 &its 0x64 0x1>, //ENETC2 PF 1861 <0x90 &its 0x65 0x1>, //ENETC2 VF0 1862 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 1863 <0xc0 &its 0x67 0x1>; //NETC Timer 1864 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 1865 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 1866 /* Timer BAR2 - prefetchable memory */ 1867 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 1868 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 1869 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 1870 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 1871 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 1872 1873 enetc_port0: ethernet@0,0 { 1874 compatible = "pci1131,e101"; 1875 reg = <0x000000 0 0 0 0>; 1876 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1877 clock-names = "ref"; 1878 status = "disabled"; 1879 }; 1880 1881 enetc_port1: ethernet@8,0 { 1882 compatible = "pci1131,e101"; 1883 reg = <0x004000 0 0 0 0>; 1884 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1885 clock-names = "ref"; 1886 status = "disabled"; 1887 }; 1888 1889 enetc_port2: ethernet@10,0 { 1890 compatible = "pci1131,e101"; 1891 reg = <0x008000 0 0 0 0>; 1892 status = "disabled"; 1893 }; 1894 1895 netc_timer: ethernet@18,0 { 1896 reg = <0x00c000 0 0 0 0>; 1897 status = "disabled"; 1898 }; 1899 }; 1900 1901 netc_bus1: pcie@4cb00000 { 1902 compatible = "pci-host-ecam-generic"; 1903 reg = <0x0 0x4cb00000 0x0 0x100000>; 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 device_type = "pci"; 1907 bus-range = <0x1 0x1>; 1908 /* EMDIO BAR0 - non-prefetchable memory */ 1909 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 1910 /* EMDIO BAR2 - prefetchable memory */ 1911 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 1912 1913 netc_emdio: mdio@0,0 { 1914 compatible = "pci1131,ee00"; 1915 reg = <0x010000 0 0 0 0>; 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 status = "disabled"; 1919 }; 1920 }; 1921 }; 1922 1923 ddr-pmu@4e090dc0 { 1924 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 1925 reg = <0x0 0x4e090dc0 0x0 0x200>; 1926 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1927 }; 1928 }; 1929}; 1930