1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7/delete-node/ &adma_pwm; 8/delete-node/ &adma_pwm_lpcg; 9 10&dma_subsys { 11 uart4_lpcg: clock-controller@5a4a0000 { 12 compatible = "fsl,imx8qxp-lpcg"; 13 reg = <0x5a4a0000 0x10000>; 14 #clock-cells = <1>; 15 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, 16 <&dma_ipg_clk>; 17 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 18 clock-output-names = "uart4_lpcg_baud_clk", 19 "uart4_lpcg_ipg_clk"; 20 power-domains = <&pd IMX_SC_R_UART_4>; 21 }; 22 23 i2c4: i2c@5a840000 { 24 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 25 reg = <0x5a840000 0x4000>; 26 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-parent = <&gic>; 28 clocks = <&i2c4_lpcg 0>, 29 <&i2c4_lpcg 1>; 30 clock-names = "per", "ipg"; 31 assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; 32 assigned-clock-rates = <24000000>; 33 power-domains = <&pd IMX_SC_R_I2C_4>; 34 status = "disabled"; 35 }; 36 37 i2c4_lpcg: clock-controller@5ac40000 { 38 compatible = "fsl,imx8qxp-lpcg"; 39 reg = <0x5ac40000 0x10000>; 40 #clock-cells = <1>; 41 clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, 42 <&dma_ipg_clk>; 43 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 44 clock-output-names = "i2c4_lpcg_clk", 45 "i2c4_lpcg_ipg_clk"; 46 power-domains = <&pd IMX_SC_R_I2C_4>; 47 }; 48 49 can1_lpcg: clock-controller@5ace0000 { 50 compatible = "fsl,imx8qxp-lpcg"; 51 reg = <0x5ace0000 0x10000>; 52 #clock-cells = <1>; 53 clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, 54 <&dma_ipg_clk>, <&dma_ipg_clk>; 55 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 56 clock-output-names = "can1_lpcg_pe_clk", 57 "can1_lpcg_ipg_clk", 58 "can1_lpcg_chi_clk"; 59 power-domains = <&pd IMX_SC_R_CAN_1>; 60 }; 61 62 can2_lpcg: clock-controller@5acf0000 { 63 compatible = "fsl,imx8qxp-lpcg"; 64 reg = <0x5acf0000 0x10000>; 65 #clock-cells = <1>; 66 clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, 67 <&dma_ipg_clk>, <&dma_ipg_clk>; 68 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 69 clock-output-names = "can2_lpcg_pe_clk", 70 "can2_lpcg_ipg_clk", 71 "can2_lpcg_chi_clk"; 72 power-domains = <&pd IMX_SC_R_CAN_2>; 73 }; 74}; 75 76&edma2 { 77 reg = <0x5a1f0000 0x170000>; 78 #dma-cells = <3>; 79 dma-channels = <22>; 80 dma-channel-mask = <0xf00>; 81 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 90 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 91 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 92 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ 93 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 104 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 105 <&pd IMX_SC_R_DMA_0_CH1>, 106 <&pd IMX_SC_R_DMA_0_CH2>, 107 <&pd IMX_SC_R_DMA_0_CH3>, 108 <&pd IMX_SC_R_DMA_0_CH4>, 109 <&pd IMX_SC_R_DMA_0_CH5>, 110 <&pd IMX_SC_R_DMA_0_CH6>, 111 <&pd IMX_SC_R_DMA_0_CH7>, 112 <&pd IMX_SC_R_DMA_0_CH8>, 113 <&pd IMX_SC_R_DMA_0_CH9>, 114 <&pd IMX_SC_R_DMA_0_CH10>, 115 <&pd IMX_SC_R_DMA_0_CH11>, 116 <&pd IMX_SC_R_DMA_0_CH12>, 117 <&pd IMX_SC_R_DMA_0_CH13>, 118 <&pd IMX_SC_R_DMA_0_CH14>, 119 <&pd IMX_SC_R_DMA_0_CH15>, 120 <&pd IMX_SC_R_DMA_0_CH16>, 121 <&pd IMX_SC_R_DMA_0_CH17>, 122 <&pd IMX_SC_R_DMA_0_CH18>, 123 <&pd IMX_SC_R_DMA_0_CH19>, 124 <&pd IMX_SC_R_DMA_0_CH20>, 125 <&pd IMX_SC_R_DMA_0_CH21>; 126 status = "okay"; 127}; 128 129/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */ 130&edma3 { 131 reg = <0x5a9f0000 0x210000>; 132 dma-channels = <10>; 133 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 143 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 144 <&pd IMX_SC_R_DMA_1_CH1>, 145 <&pd IMX_SC_R_DMA_1_CH2>, 146 <&pd IMX_SC_R_DMA_1_CH3>, 147 <&pd IMX_SC_R_DMA_1_CH4>, 148 <&pd IMX_SC_R_DMA_1_CH5>, 149 <&pd IMX_SC_R_DMA_1_CH6>, 150 <&pd IMX_SC_R_DMA_1_CH7>, 151 <&pd IMX_SC_R_DMA_1_CH8>, 152 <&pd IMX_SC_R_DMA_1_CH9>; 153}; 154 155&flexcan1 { 156 fsl,clk-source = /bits/ 8 <1>; 157}; 158 159&flexcan2 { 160 clocks = <&can1_lpcg IMX_LPCG_CLK_4>, 161 <&can1_lpcg IMX_LPCG_CLK_0>; 162 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; 163 fsl,clk-source = /bits/ 8 <1>; 164}; 165 166&flexcan3 { 167 clocks = <&can2_lpcg IMX_LPCG_CLK_4>, 168 <&can2_lpcg IMX_LPCG_CLK_0>; 169 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; 170 fsl,clk-source = /bits/ 8 <1>; 171}; 172 173&lpuart0 { 174 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 175 dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; 176 dma-names = "rx","tx"; 177}; 178 179&lpuart1 { 180 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 181 dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; 182 dma-names = "rx","tx"; 183}; 184 185&lpuart2 { 186 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 187 dmas = <&edma2 17 0 0>, <&edma2 16 0 1>; 188 dma-names = "rx","tx"; 189}; 190 191&lpuart3 { 192 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 193 dmas = <&edma2 19 0 0>, <&edma2 18 0 1>; 194 dma-names = "rx","tx"; 195}; 196 197&i2c0 { 198 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 199}; 200 201&i2c1 { 202 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 203}; 204 205&i2c2 { 206 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 207}; 208 209&i2c3 { 210 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 211}; 212