xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
4 * 2025 Maud Spierings <maudspierings@gocontroll.com>
5 */
6
7#include "imx8mp.dtsi"
8
9/ {
10	/* PHY regulator */
11	regulator-3v3-etn {
12		compatible = "regulator-fixed";
13		gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
14		enable-active-high;
15		pinctrl-0 = <&pinctrl_reg_3v3_etn>;
16		pinctrl-names = "default";
17		regulator-always-on;
18		regulator-boot-on;
19		regulator-max-microvolt = <3300000>;
20		regulator-min-microvolt = <3300000>;
21		regulator-name = "3v3-etn";
22		vin-supply = <&reg_vdd_3v3>;
23	};
24};
25
26&A53_0 {
27	cpu-supply = <&reg_vdd_arm>;
28};
29
30&A53_1 {
31	cpu-supply = <&reg_vdd_arm>;
32};
33
34&A53_2 {
35	cpu-supply = <&reg_vdd_arm>;
36};
37
38&A53_3 {
39	cpu-supply = <&reg_vdd_arm>;
40};
41
42&eqos {
43	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
44			  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
45			  <&clk IMX8MP_CLK_ENET_QOS>;
46	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
47				 <&clk IMX8MP_SYS_PLL2_100M>,
48				 <&clk IMX8MP_SYS_PLL2_50M>;
49	assigned-clock-rates = <266000000>, <100000000>, <50000000>;
50	phy-handle = <&ethphy0>;
51	phy-mode = "rmii";
52	pinctrl-0 = <&pinctrl_eqos>;
53	pinctrl-1 = <&pinctrl_eqos_sleep>;
54	pinctrl-names = "default", "sleep";
55	status = "okay";
56
57	mdio {
58		compatible = "snps,dwmac-mdio";
59		#address-cells = <1>;
60		#size-cells = <0>;
61		pinctrl-0 = <&pinctrl_ethphy_rst_b>;
62		pinctrl-names = "default";
63		reset-delay-us = <25000>;
64		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
65
66		ethphy0: ethernet-phy@0 {
67			reg = <0>;
68			interrupt-parent = <&gpio4>;
69			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
70			clocks = <&clk IMX8MP_CLK_ENET_QOS>;
71			pinctrl-0 = <&pinctrl_ethphy_int_b>;
72			pinctrl-names = "default";
73			smsc,disable-energy-detect;
74		};
75	};
76};
77
78&gpio1 {
79	gpio-line-names = "SODIMM_152",
80			  "SODIMM_42",
81			  "PMIC_WDOG_B SODIMM_153",
82			  "PMIC_IRQ_B",
83			  "SODIMM_154",
84			  "SODIMM_155",
85			  "SODIMM_156",
86			  "SODIMM_157",
87			  "SODIMM_158",
88			  "SODIMM_159",
89			  "SODIMM_161",
90			  "SODIMM_162",
91			  "SODIMM_34",
92			  "SODIMM_36",
93			  "SODIMM_27",
94			  "SODIMM_28",
95			  "ENET_MDC",
96			  "ENET_MDIO",
97			  "",
98			  "ENET_XTAL1/CLKIN",
99			  "ENET_TXD1",
100			  "ENET_TXD0",
101			  "ENET_TXEN",
102			  "ENET_POWER",
103			  "ENET_COL/CRS_DV",
104			  "ENET_RXER",
105			  "ENET_RXD0",
106			  "ENET_RXD1",
107			  "",
108			  "",
109			  "",
110			  "";
111};
112
113&gpio2 {
114	gpio-line-names = "",
115			  "",
116			  "",
117			  "",
118			  "",
119			  "",
120			  "",
121			  "",
122			  "",
123			  "",
124			  "",
125			  "",
126			  "SODIMM_51",
127			  "SODIMM_57",
128			  "SODIMM_56",
129			  "SODIMM_52",
130			  "SODIMM_53",
131			  "SODIMM_54",
132			  "SODIMM_55",
133			  "SODIMM_15",
134			  "",
135			  "",
136			  "",
137			  "",
138			  "",
139			  "",
140			  "",
141			  "",
142			  "",
143			  "",
144			  "",
145			  "";
146};
147
148&gpio3 {
149	gpio-line-names = "",
150			  "",
151			  "EMMC_DS",
152			  "EMMC_DAT5",
153			  "EMMC_DAT6",
154			  "EMMC_DAT7",
155			  "",
156			  "",
157			  "",
158			  "",
159			  "EMMC_DAT0",
160			  "EMMC_DAT1",
161			  "EMMC_DAT2",
162			  "EMMC_DAT3",
163			  "",
164			  "EMMC_DAT4",
165			  "",
166			  "EMMC_CLK",
167			  "EMMC_CMD",
168			  "SODIMM_75",
169			  "SODIMM_145",
170			  "SODIMM_163",
171			  "SODIMM_164",
172			  "SODIMM_165",
173			  "SODIMM_143",
174			  "SODIMM_144",
175			  "SODIMM_72",
176			  "SODIMM_73",
177			  "SODIMM_74",
178			  "SODIMM_93",
179			  "",
180			  "";
181};
182
183&gpio4 {
184	gpio-line-names = "SODIMM_98",
185			  "SODIMM_99",
186			  "SODIMM_100",
187			  "SODIMM_101",
188			  "SODIMM_45",
189			  "SODIMM_43",
190			  "SODIMM_105",
191			  "SODIMM_106",
192			  "SODIMM_107",
193			  "SODIMM_108",
194			  "SODIMM_104",
195			  "SODIMM_103",
196			  "SODIMM_115",
197			  "SODIMM_114",
198			  "SODIMM_113",
199			  "SODIMM_112",
200			  "SODIMM_109",
201			  "SODIMM_110",
202			  "SODIMM_95",
203			  "SODIMM_96",
204			  "SODIMM_97",
205			  "ENET_nINT",
206			  "ENET_nRST",
207			  "SODIMM_84",
208			  "SODIMM_87",
209			  "SODIMM_86",
210			  "SODIMM_85",
211			  "SODIMM_83",
212			  "",
213			  "SODIMM_66",
214			  "SODIMM_65",
215			  "";
216};
217
218&gpio5 {
219	gpio-line-names = "",
220			  "",
221			  "",
222			  "SODIMM_76",
223			  "SODIMM_81",
224			  "SODIMM_146",
225			  "SODIMM_48",
226			  "SODIMM_46",
227			  "SODIMM_47",
228			  "SODIMM_44",
229			  "SODIMM_49",
230			  "",
231			  "SODIMM_70",
232			  "SODIMM_69",
233			  "PMIC_SCL",
234			  "PMIC_SDA",
235			  "SODIMM_41",
236			  "SODIMM_40",
237			  "SODIMM_148",
238			  "SODIMM_149",
239			  "SODIMM_150",
240			  "SODIMM_151",
241			  "SODIMM_60",
242			  "SODIMM_59",
243			  "SODIMM_64",
244			  "SODIMM_63",
245			  "SODIMM_62",
246			  "SODIMM_61",
247			  "SODIMM_68",
248			  "SODIMM_67",
249			  "",
250			  "";
251};
252
253&i2c1 {
254	clock-frequency = <400000>;
255	pinctrl-0 = <&pinctrl_i2c1>;
256	pinctrl-1 = <&pinctrl_i2c1_gpio>;
257	pinctrl-names = "default", "gpio";
258	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
259	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
260	status = "okay";
261
262	pmic@25 {
263		compatible = "nxp,pca9450c";
264		reg = <0x25>;
265		interrupt-parent = <&gpio1>;
266		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
267		pinctrl-0 = <&pinctrl_pmic>;
268		pinctrl-names = "default";
269
270		regulators {
271			reg_vdd_soc: BUCK1 {
272				regulator-always-on;
273				regulator-boot-on;
274				regulator-max-microvolt = <900000>;
275				regulator-min-microvolt = <805000>;
276				regulator-name = "vdd-soc";
277				regulator-ramp-delay = <3125>;
278			};
279
280			reg_vdd_arm: BUCK2 {
281				regulator-always-on;
282				regulator-boot-on;
283				regulator-max-microvolt = <950000>;
284				regulator-min-microvolt = <805000>;
285				regulator-name = "vdd-core";
286				regulator-ramp-delay = <3125>;
287				nxp,dvs-run-voltage = <950000>;
288				nxp,dvs-standby-voltage = <850000>;
289			};
290
291			reg_vdd_3v3: BUCK4 {
292				regulator-always-on;
293				regulator-boot-on;
294				regulator-max-microvolt = <3300000>;
295				regulator-min-microvolt = <3300000>;
296				regulator-name = "3v3";
297			};
298
299			reg_nvcc_nand: BUCK5 {
300				regulator-always-on;
301				regulator-boot-on;
302				regulator-max-microvolt = <1800000>;
303				regulator-min-microvolt = <1800000>;
304				regulator-name = "nvcc-nand";
305			};
306
307			reg_nvcc_dram: BUCK6 {
308				regulator-always-on;
309				regulator-boot-on;
310				regulator-max-microvolt = <1100000>;
311				regulator-min-microvolt = <1100000>;
312				regulator-name = "nvcc-dram";
313			};
314
315			reg_snvs_1v8: LDO1 {
316				regulator-always-on;
317				regulator-boot-on;
318				regulator-max-microvolt = <1800000>;
319				regulator-min-microvolt = <1800000>;
320				regulator-name = "snvs-1v8";
321			};
322
323			ldo2_reg: LDO2 {
324				regulator-always-on;
325				regulator-max-microvolt = <1150000>;
326				regulator-min-microvolt = <800000>;
327				regulator-name = "LDO2";
328			};
329
330			reg_vdda_1v8: LDO3 {
331				regulator-always-on;
332				regulator-boot-on;
333				regulator-max-microvolt = <1800000>;
334				regulator-min-microvolt = <1800000>;
335				regulator-name = "vdda-1v8";
336			};
337
338			ldo4_reg: LDO4 {
339				regulator-max-microvolt = <3300000>;
340				regulator-min-microvolt = <800000>;
341				regulator-name = "LDO4";
342			};
343
344			ldo5_reg: LDO5 {
345				regulator-always-on;
346				regulator-boot-on;
347				regulator-max-microvolt = <3300000>;
348				regulator-min-microvolt = <1800000>;
349				regulator-name = "LDO5";
350			};
351		};
352	};
353};
354
355&iomuxc {
356	pinctrl_eqos: eqosgrp {
357		fsl,pins = <
358			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK
359				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)
360			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
361				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
362			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
363				(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
364			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
365				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
366			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
367				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
368			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
369				(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
370			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
371				(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
372			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER
373				(MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
374			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
375				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
376			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
377				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
378		>;
379	};
380
381	pinctrl_eqos_sleep: eqos-sleep-grp {
382		fsl,pins = <
383			MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19
384				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
385			MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16
386				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
387			MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17
388				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
389			MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21
390				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
391			MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20
392				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
393			MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26
394				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
395			MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27
396				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
397			MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25
398				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
399			MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24
400				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
401			MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22
402				(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
403		>;
404	};
405
406	pinctrl_ethphy_int_b: ethphy-int-bgrp {
407		fsl,pins = <
408			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21
409				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)
410		>;
411	};
412
413	pinctrl_ethphy_rst_b: ethphy-rst-bgrp {
414		fsl,pins = <
415			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
416				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
417		>;
418	};
419
420	pinctrl_i2c1: i2c1grp {
421		fsl,pins = <
422			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
423				MX8MP_I2C_DEFAULT
424			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
425				MX8MP_I2C_DEFAULT
426		>;
427	};
428
429	pinctrl_i2c1_gpio: i2c1-gpiogrp {
430		fsl,pins = <
431			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
432				MX8MP_I2C_DEFAULT
433			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
434				MX8MP_I2C_DEFAULT
435		>;
436	};
437
438	pinctrl_pmic: pmicgrp {
439		fsl,pins = <
440			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
441				(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
442		>;
443	};
444
445	pinctrl_reg_3v3_etn: reg-3v3-etngrp {
446		fsl,pins = <
447			MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23
448				(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
449		>;
450	};
451
452	pinctrl_usdhc3: usdhc3grp {
453		fsl,pins = <
454			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
455				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
456			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
457				MX8MP_USDHC_DATA_DEFAULT
458			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
459				MX8MP_USDHC_DATA_DEFAULT
460			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
461				MX8MP_USDHC_DATA_DEFAULT
462			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
463				MX8MP_USDHC_DATA_DEFAULT
464			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
465				MX8MP_USDHC_DATA_DEFAULT
466			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
467				MX8MP_USDHC_DATA_DEFAULT
468			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
469				MX8MP_USDHC_DATA_DEFAULT
470			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
471				MX8MP_USDHC_DATA_DEFAULT
472			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
473				MX8MP_USDHC_DATA_DEFAULT
474			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
475				(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
476		>;
477	};
478
479	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
480		fsl,pins = <
481			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
482				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
483			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
484				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
485			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
486				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
487			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
488				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
489			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
490				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
491			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
492				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
493			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
494				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
495			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
496				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
497			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
498				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
499			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
500				(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
501			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
502				(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
503		>;
504	};
505
506	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
507		fsl,pins = <
508			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
509				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
510			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
511				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
512			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
513				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
514			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
515				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
516			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
517				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
518			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
519				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
520			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
521				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
522			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
523				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
524			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
525				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
526			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
527				(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
528			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
529				(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
530		>;
531	};
532};
533
534&usdhc3 {
535	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
536	assigned-clock-rates = <200000000>;
537	bus-width = <8>;
538	max-frequency = <200000000>;
539	non-removable;
540	pinctrl-0 = <&pinctrl_usdhc3>;
541	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
542	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
543	pinctrl-names = "default", "state_100mhz", "state_200mhz";
544	vmmc-supply = <&reg_vdd_3v3>;
545	voltage-ranges = <3300 3300>;
546	vqmmc-supply = <&reg_nvcc_nand>;
547	status = "okay";
548};
549