1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019-2021 NXP 4 * Zhou Guoniu <guoniu.zhou@nxp.com> 5 */ 6img_ipg_clk: clock-img-ipg { 7 compatible = "fixed-clock"; 8 #clock-cells = <0>; 9 clock-frequency = <200000000>; 10 clock-output-names = "img_ipg_clk"; 11}; 12 13img_pxl_clk: clock-img-pxl { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <600000000>; 17 clock-output-names = "img_pxl_clk"; 18}; 19 20img_subsys: bus@58000000 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x58000000 0x0 0x58000000 0x1000000>; 25 26 isi: isi@58100000 { 27 reg = <0x58100000 0x80000>; 28 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; 36 clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, 37 <&pdma1_lpcg IMX_LPCG_CLK_0>, 38 <&pdma2_lpcg IMX_LPCG_CLK_0>, 39 <&pdma3_lpcg IMX_LPCG_CLK_0>, 40 <&pdma4_lpcg IMX_LPCG_CLK_0>, 41 <&pdma5_lpcg IMX_LPCG_CLK_0>, 42 <&pdma6_lpcg IMX_LPCG_CLK_0>, 43 <&pdma7_lpcg IMX_LPCG_CLK_0>; 44 clock-names = "per0", "per1", "per2", "per3", 45 "per4", "per5", "per6", "per7"; 46 interrupt-parent = <&gic>; 47 power-domains = <&pd IMX_SC_R_ISI_CH0>, 48 <&pd IMX_SC_R_ISI_CH1>, 49 <&pd IMX_SC_R_ISI_CH2>, 50 <&pd IMX_SC_R_ISI_CH3>, 51 <&pd IMX_SC_R_ISI_CH4>, 52 <&pd IMX_SC_R_ISI_CH5>, 53 <&pd IMX_SC_R_ISI_CH6>, 54 <&pd IMX_SC_R_ISI_CH7>; 55 status = "disabled"; 56 }; 57 58 irqsteer_csi0: irqsteer@58220000 { 59 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 60 reg = <0x58220000 0x1000>; 61 #interrupt-cells = <1>; 62 interrupt-controller; 63 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 64 clocks = <&img_ipg_clk>; 65 clock-names = "ipg"; 66 interrupt-parent = <&gic>; 67 power-domains = <&pd IMX_SC_R_CSI_0>; 68 fsl,channel = <0>; 69 fsl,num-irqs = <32>; 70 }; 71 72 gpio0_mipi_csi0: gpio@58222000 { 73 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 74 reg = <0x58222000 0x1000>; 75 #interrupt-cells = <2>; 76 interrupt-controller; 77 interrupts = <0>; 78 #gpio-cells = <2>; 79 gpio-controller; 80 interrupt-parent = <&irqsteer_csi0>; 81 power-domains = <&pd IMX_SC_R_CSI_0>; 82 }; 83 84 csi0_core_lpcg: clock-controller@58223018 { 85 compatible = "fsl,imx8qxp-lpcg"; 86 reg = <0x58223018 0x4>; 87 clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; 88 #clock-cells = <1>; 89 clock-indices = <IMX_LPCG_CLK_4>; 90 clock-output-names = "csi0_lpcg_core_clk"; 91 power-domains = <&pd IMX_SC_R_ISI_CH0>; 92 }; 93 94 csi0_esc_lpcg: clock-controller@5822301c { 95 compatible = "fsl,imx8qxp-lpcg"; 96 reg = <0x5822301c 0x4>; 97 clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; 98 #clock-cells = <1>; 99 clock-indices = <IMX_LPCG_CLK_4>; 100 clock-output-names = "csi0_lpcg_esc_clk"; 101 power-domains = <&pd IMX_SC_R_ISI_CH0>; 102 }; 103 104 i2c_mipi_csi0: i2c@58226000 { 105 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 106 reg = <0x58226000 0x1000>; 107 interrupts = <8>; 108 clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, 109 <&img_ipg_clk>; 110 clock-names = "per", "ipg"; 111 assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; 112 assigned-clock-rates = <24000000>; 113 interrupt-parent = <&irqsteer_csi0>; 114 power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; 115 status = "disabled"; 116 }; 117 118 mipi_csi_0: csi@58227000 { 119 compatible = "fsl,imx8qxp-mipi-csi2"; 120 reg = <0x58227000 0x1000>, 121 <0x58221000 0x1000>; 122 clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>, 123 <&csi0_esc_lpcg IMX_LPCG_CLK_4>, 124 <&csi0_pxl_lpcg IMX_LPCG_CLK_0>; 125 clock-names = "core", "esc", "ui"; 126 assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>, 127 <&csi0_esc_lpcg IMX_LPCG_CLK_4>; 128 assigned-clock-rates = <360000000>, <72000000>; 129 power-domains = <&pd IMX_SC_R_ISI_CH0>; 130 resets = <&scu_reset IMX_SC_R_CSI_0>; 131 status = "disabled"; 132 }; 133 134 irqsteer_csi1: irqsteer@58240000 { 135 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 136 reg = <0x58240000 0x1000>; 137 #interrupt-cells = <1>; 138 interrupt-controller; 139 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&img_ipg_clk>; 141 clock-names = "ipg"; 142 interrupt-parent = <&gic>; 143 power-domains = <&pd IMX_SC_R_CSI_1>; 144 fsl,channel = <0>; 145 fsl,num-irqs = <32>; 146 }; 147 148 gpio0_mipi_csi1: gpio@58242000 { 149 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 150 reg = <0x58242000 0x1000>; 151 #interrupt-cells = <2>; 152 interrupt-controller; 153 interrupts = <0>; 154 #gpio-cells = <2>; 155 gpio-controller; 156 interrupt-parent = <&irqsteer_csi1>; 157 power-domains = <&pd IMX_SC_R_CSI_1>; 158 }; 159 160 csi1_core_lpcg: clock-controller@58243018 { 161 compatible = "fsl,imx8qxp-lpcg"; 162 reg = <0x58243018 0x4>; 163 clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; 164 #clock-cells = <1>; 165 clock-indices = <IMX_LPCG_CLK_4>; 166 clock-output-names = "csi1_lpcg_core_clk"; 167 power-domains = <&pd IMX_SC_R_ISI_CH0>; 168 }; 169 170 csi1_esc_lpcg: clock-controller@5824301c { 171 compatible = "fsl,imx8qxp-lpcg"; 172 reg = <0x5824301c 0x4>; 173 clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; 174 #clock-cells = <1>; 175 clock-indices = <IMX_LPCG_CLK_4>; 176 clock-output-names = "csi1_lpcg_esc_clk"; 177 power-domains = <&pd IMX_SC_R_ISI_CH0>; 178 }; 179 180 i2c_mipi_csi1: i2c@58246000 { 181 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 182 reg = <0x58246000 0x1000>; 183 interrupts = <8>; 184 clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, 185 <&img_ipg_clk>; 186 clock-names = "per", "ipg"; 187 assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; 188 assigned-clock-rates = <24000000>; 189 interrupt-parent = <&irqsteer_csi1>; 190 power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; 191 status = "disabled"; 192 }; 193 194 mipi_csi_1: csi@58247000 { 195 compatible = "fsl,imx8qxp-mipi-csi2"; 196 reg = <0x58247000 0x1000>, 197 <0x58241000 0x1000>; 198 clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>, 199 <&csi1_esc_lpcg IMX_LPCG_CLK_4>, 200 <&csi1_pxl_lpcg IMX_LPCG_CLK_0>; 201 clock-names = "core", "esc", "ui"; 202 assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>, 203 <&csi1_esc_lpcg IMX_LPCG_CLK_4>; 204 assigned-clock-rates = <360000000>, <72000000>; 205 power-domains = <&pd IMX_SC_R_ISI_CH0>; 206 resets = <&scu_reset IMX_SC_R_CSI_1>; 207 status = "disabled"; 208 }; 209 210 irqsteer_parallel: irqsteer@58260000 { 211 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 212 reg = <0x58260000 0x1000>; 213 #interrupt-cells = <1>; 214 interrupt-controller; 215 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk_dummy>; 217 clock-names = "ipg"; 218 interrupt-parent = <&gic>; 219 power-domains = <&pd IMX_SC_R_PI_0>; 220 fsl,channel = <0>; 221 fsl,num-irqs = <32>; 222 status = "disabled"; 223 }; 224 225 pi0_ipg_lpcg: clock-controller@58263004 { 226 compatible = "fsl,imx8qxp-lpcg"; 227 reg = <0x58263004 0x4>; 228 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; 229 #clock-cells = <1>; 230 clock-indices = <IMX_LPCG_CLK_4>; 231 clock-output-names = "pi0_lpcg_ipg_clk"; 232 power-domains = <&pd IMX_SC_R_ISI_CH0>; 233 }; 234 235 pi0_pxl_lpcg: clock-controller@58263018 { 236 compatible = "fsl,imx8qxp-lpcg"; 237 reg = <0x58263018 0x4>; 238 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; 239 #clock-cells = <1>; 240 clock-indices = <IMX_LPCG_CLK_0>; 241 clock-output-names = "pi0_lpcg_pxl_clk"; 242 power-domains = <&pd IMX_SC_R_ISI_CH0>; 243 }; 244 245 pi0_misc_lpcg: clock-controller@5826301c { 246 compatible = "fsl,imx8qxp-lpcg"; 247 reg = <0x5826301c 0x4>; 248 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; 249 #clock-cells = <1>; 250 clock-indices = <IMX_LPCG_CLK_0>; 251 clock-output-names = "pi0_lpcg_misc_clk"; 252 power-domains = <&pd IMX_SC_R_ISI_CH0>; 253 }; 254 255 i2c0_parallel: i2c@58266000 { 256 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 257 reg = <0x58266000 0x1000>; 258 interrupts = <8>; 259 clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, 260 <&img_ipg_clk>; 261 clock-names = "per", "ipg"; 262 assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; 263 assigned-clock-rates = <24000000>; 264 interrupt-parent = <&irqsteer_parallel>; 265 power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; 266 status = "disabled"; 267 }; 268 269 jpegdec: jpegdec@58400000 { 270 reg = <0x58400000 0x00050000>; 271 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 273 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 274 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 275 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 276 assigned-clock-rates = <200000000>, <200000000>; 277 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, 278 <&pd IMX_SC_R_MJPEG_DEC_S0>; 279 }; 280 281 jpegenc: jpegenc@58450000 { 282 reg = <0x58450000 0x00050000>; 283 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 285 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 286 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 287 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 288 assigned-clock-rates = <200000000>, <200000000>; 289 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, 290 <&pd IMX_SC_R_MJPEG_ENC_S0>; 291 }; 292 293 pdma0_lpcg: clock-controller@58500000 { 294 compatible = "fsl,imx8qxp-lpcg"; 295 reg = <0x58500000 0x10000>; 296 clocks = <&img_pxl_clk>; 297 #clock-cells = <1>; 298 clock-indices = <IMX_LPCG_CLK_0>; 299 clock-output-names = "pdma0_lpcg_clk"; 300 power-domains = <&pd IMX_SC_R_ISI_CH0>; 301 }; 302 303 pdma1_lpcg: clock-controller@58510000 { 304 compatible = "fsl,imx8qxp-lpcg"; 305 reg = <0x58510000 0x10000>; 306 clocks = <&img_pxl_clk>; 307 #clock-cells = <1>; 308 clock-indices = <IMX_LPCG_CLK_0>; 309 clock-output-names = "pdma1_lpcg_clk"; 310 power-domains = <&pd IMX_SC_R_ISI_CH1>; 311 }; 312 313 pdma2_lpcg: clock-controller@58520000 { 314 compatible = "fsl,imx8qxp-lpcg"; 315 reg = <0x58520000 0x10000>; 316 clocks = <&img_pxl_clk>; 317 #clock-cells = <1>; 318 clock-indices = <IMX_LPCG_CLK_0>; 319 clock-output-names = "pdma2_lpcg_clk"; 320 power-domains = <&pd IMX_SC_R_ISI_CH2>; 321 }; 322 323 pdma3_lpcg: clock-controller@58530000 { 324 compatible = "fsl,imx8qxp-lpcg"; 325 reg = <0x58530000 0x10000>; 326 clocks = <&img_pxl_clk>; 327 #clock-cells = <1>; 328 clock-indices = <IMX_LPCG_CLK_0>; 329 clock-output-names = "pdma3_lpcg_clk"; 330 power-domains = <&pd IMX_SC_R_ISI_CH3>; 331 }; 332 333 pdma4_lpcg: clock-controller@58540000 { 334 compatible = "fsl,imx8qxp-lpcg"; 335 reg = <0x58540000 0x10000>; 336 clocks = <&img_pxl_clk>; 337 #clock-cells = <1>; 338 clock-indices = <IMX_LPCG_CLK_0>; 339 clock-output-names = "pdma4_lpcg_clk"; 340 power-domains = <&pd IMX_SC_R_ISI_CH4>; 341 }; 342 343 pdma5_lpcg: clock-controller@58550000 { 344 compatible = "fsl,imx8qxp-lpcg"; 345 reg = <0x58550000 0x10000>; 346 clocks = <&img_pxl_clk>; 347 #clock-cells = <1>; 348 clock-indices = <IMX_LPCG_CLK_0>; 349 clock-output-names = "pdma5_lpcg_clk"; 350 power-domains = <&pd IMX_SC_R_ISI_CH5>; 351 }; 352 353 pdma6_lpcg: clock-controller@58560000 { 354 compatible = "fsl,imx8qxp-lpcg"; 355 reg = <0x58560000 0x10000>; 356 clocks = <&img_pxl_clk>; 357 #clock-cells = <1>; 358 clock-indices = <IMX_LPCG_CLK_0>; 359 clock-output-names = "pdma6_lpcg_clk"; 360 power-domains = <&pd IMX_SC_R_ISI_CH6>; 361 }; 362 363 pdma7_lpcg: clock-controller@58570000 { 364 compatible = "fsl,imx8qxp-lpcg"; 365 reg = <0x58570000 0x10000>; 366 clocks = <&img_pxl_clk>; 367 #clock-cells = <1>; 368 clock-indices = <IMX_LPCG_CLK_0>; 369 clock-output-names = "pdma7_lpcg_clk"; 370 power-domains = <&pd IMX_SC_R_ISI_CH7>; 371 }; 372 373 csi0_pxl_lpcg: clock-controller@58580000 { 374 compatible = "fsl,imx8qxp-lpcg"; 375 reg = <0x58580000 0x10000>; 376 clocks = <&img_pxl_clk>; 377 #clock-cells = <1>; 378 clock-indices = <IMX_LPCG_CLK_0>; 379 clock-output-names = "csi0_lpcg_pxl_clk"; 380 power-domains = <&pd IMX_SC_R_CSI_0>; 381 }; 382 383 csi1_pxl_lpcg: clock-controller@58590000 { 384 compatible = "fsl,imx8qxp-lpcg"; 385 reg = <0x58590000 0x10000>; 386 clocks = <&img_pxl_clk>; 387 #clock-cells = <1>; 388 clock-indices = <IMX_LPCG_CLK_0>; 389 clock-output-names = "csi1_lpcg_pxl_clk"; 390 power-domains = <&pd IMX_SC_R_CSI_1>; 391 }; 392 393 hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 { 394 compatible = "fsl,imx8qxp-lpcg"; 395 reg = <0x585a0000 0x10000>; 396 clocks = <&img_pxl_clk>; 397 #clock-cells = <1>; 398 clock-indices = <IMX_LPCG_CLK_0>; 399 clock-output-names = "hdmi_rx_lpcg_pxl_link_clk"; 400 power-domains = <&pd IMX_SC_R_HDMI_RX>; 401 }; 402 403 img_jpeg_dec_lpcg: clock-controller@585d0000 { 404 compatible = "fsl,imx8qxp-lpcg"; 405 reg = <0x585d0000 0x10000>; 406 #clock-cells = <1>; 407 clocks = <&img_ipg_clk>, <&img_ipg_clk>; 408 clock-indices = <IMX_LPCG_CLK_0>, 409 <IMX_LPCG_CLK_4>; 410 clock-output-names = "img_jpeg_dec_lpcg_clk", 411 "img_jpeg_dec_lpcg_ipg_clk"; 412 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; 413 }; 414 415 img_jpeg_enc_lpcg: clock-controller@585f0000 { 416 compatible = "fsl,imx8qxp-lpcg"; 417 reg = <0x585f0000 0x10000>; 418 #clock-cells = <1>; 419 clocks = <&img_ipg_clk>, <&img_ipg_clk>; 420 clock-indices = <IMX_LPCG_CLK_0>, 421 <IMX_LPCG_CLK_4>; 422 clock-output-names = "img_jpeg_enc_lpcg_clk", 423 "img_jpeg_enc_lpcg_ipg_clk"; 424 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; 425 }; 426}; 427