1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10conn_axi_clk: clock-conn-axi { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <333333333>; 14 clock-output-names = "conn_axi_clk"; 15}; 16 17conn_ahb_clk: clock-conn-ahb { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <166666666>; 21 clock-output-names = "conn_ahb_clk"; 22}; 23 24conn_ipg_clk: clock-conn-ipg { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <83333333>; 28 clock-output-names = "conn_ipg_clk"; 29}; 30 31conn_bch_clk: clock-conn-bch { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <400000000>; 35 clock-output-names = "conn_bch_clk"; 36}; 37 38conn_subsys: bus@5b000000 { 39 compatible = "simple-bus"; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 43 44 usbotg1: usb@5b0d0000 { 45 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; 46 reg = <0x5b0d0000 0x200>; 47 interrupt-parent = <&gic>; 48 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 49 fsl,usbphy = <&usbphy1>; 50 fsl,usbmisc = <&usbmisc1 0>; 51 clocks = <&usb2_lpcg IMX_LPCG_CLK_6>; 52 ahb-burst-config = <0x0>; 53 tx-burst-size-dword = <0x10>; 54 rx-burst-size-dword = <0x10>; 55 power-domains = <&pd IMX_SC_R_USB_0>; 56 status = "disabled"; 57 }; 58 59 usbmisc1: usbmisc@5b0d0200 { 60 #index-cells = <1>; 61 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 62 reg = <0x5b0d0200 0x200>; 63 }; 64 65 usbphy1: usbphy@5b100000 { 66 compatible = "fsl,imx7ulp-usbphy"; 67 reg = <0x5b100000 0x1000>; 68 clocks = <&usb2_lpcg IMX_LPCG_CLK_7>; 69 power-domains = <&pd IMX_SC_R_USB_0_PHY>; 70 status = "disabled"; 71 }; 72 73 usdhc1: mmc@5b010000 { 74 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 75 reg = <0x5b010000 0x10000>; 76 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 77 <&sdhc0_lpcg IMX_LPCG_CLK_5>, 78 <&sdhc0_lpcg IMX_LPCG_CLK_0>; 79 clock-names = "ipg", "ahb", "per"; 80 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; 81 assigned-clock-rates = <400000000>; 82 power-domains = <&pd IMX_SC_R_SDHC_0>; 83 fsl,tuning-start-tap = <20>; 84 fsl,tuning-step = <2>; 85 status = "disabled"; 86 }; 87 88 usdhc2: mmc@5b020000 { 89 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 90 reg = <0x5b020000 0x10000>; 91 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 92 <&sdhc1_lpcg IMX_LPCG_CLK_5>, 93 <&sdhc1_lpcg IMX_LPCG_CLK_0>; 94 clock-names = "ipg", "ahb", "per"; 95 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; 96 assigned-clock-rates = <200000000>; 97 power-domains = <&pd IMX_SC_R_SDHC_1>; 98 fsl,tuning-start-tap = <20>; 99 fsl,tuning-step = <2>; 100 status = "disabled"; 101 }; 102 103 usdhc3: mmc@5b030000 { 104 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 105 reg = <0x5b030000 0x10000>; 106 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 107 <&sdhc2_lpcg IMX_LPCG_CLK_5>, 108 <&sdhc2_lpcg IMX_LPCG_CLK_0>; 109 clock-names = "ipg", "ahb", "per"; 110 assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; 111 assigned-clock-rates = <200000000>; 112 power-domains = <&pd IMX_SC_R_SDHC_2>; 113 fsl,tuning-start-tap = <20>; 114 fsl,tuning-step = <2>; 115 status = "disabled"; 116 }; 117 118 fec1: ethernet@5b040000 { 119 reg = <0x5b040000 0x10000>; 120 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 125 <&enet0_lpcg IMX_LPCG_CLK_2>, 126 <&enet0_lpcg IMX_LPCG_CLK_3>, 127 <&enet0_lpcg IMX_LPCG_CLK_0>, 128 <&enet0_lpcg IMX_LPCG_CLK_1>; 129 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 130 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 131 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 132 assigned-clock-rates = <250000000>, <125000000>; 133 fsl,num-tx-queues = <3>; 134 fsl,num-rx-queues = <3>; 135 power-domains = <&pd IMX_SC_R_ENET_0>; 136 status = "disabled"; 137 }; 138 139 fec2: ethernet@5b050000 { 140 reg = <0x5b050000 0x10000>; 141 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 146 <&enet1_lpcg IMX_LPCG_CLK_2>, 147 <&enet1_lpcg IMX_LPCG_CLK_3>, 148 <&enet1_lpcg IMX_LPCG_CLK_0>, 149 <&enet0_lpcg IMX_LPCG_CLK_1>; 150 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 151 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 152 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 153 assigned-clock-rates = <250000000>, <125000000>; 154 fsl,num-tx-queues = <3>; 155 fsl,num-rx-queues = <3>; 156 power-domains = <&pd IMX_SC_R_ENET_1>; 157 status = "disabled"; 158 }; 159 160 usbotg3: usb@5b110000 { 161 compatible = "fsl,imx8qm-usb3"; 162 reg = <0x5b110000 0x10000>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges; 166 clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, 167 <&usb3_lpcg IMX_LPCG_CLK_0>, 168 <&usb3_lpcg IMX_LPCG_CLK_7>, 169 <&usb3_lpcg IMX_LPCG_CLK_4>, 170 <&usb3_lpcg IMX_LPCG_CLK_5>; 171 clock-names = "lpm", "bus", "aclk", "ipg", "core"; 172 assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 173 assigned-clock-rates = <250000000>; 174 power-domains = <&pd IMX_SC_R_USB_2>; 175 status = "disabled"; 176 177 usbotg3_cdns3: usb@5b120000 { 178 compatible = "cdns,usb3"; 179 reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */ 180 <0x5b130000 0x10000>, /* memory area for HOST registers */ 181 <0x5b140000 0x10000>; /* memory area for DEVICE registers */ 182 reg-names = "otg", "xhci", "dev"; 183 interrupt-parent = <&gic>; 184 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-names = "host", "peripheral", "otg", "wakeup"; 189 phys = <&usb3_phy>; 190 phy-names = "cdns3,usb3-phy"; 191 cdns,on-chip-buff-size = /bits/ 16 <18>; 192 status = "disabled"; 193 }; 194 }; 195 196 usb3_phy: usb-phy@5b160000 { 197 compatible = "nxp,salvo-phy"; 198 reg = <0x5b160000 0x40000>; 199 clocks = <&usb3_lpcg IMX_LPCG_CLK_6>; 200 clock-names = "salvo_phy_clk"; 201 power-domains = <&pd IMX_SC_R_USB_2_PHY>; 202 #phy-cells = <0>; 203 status = "disabled"; 204 }; 205 206 /* LPCG clocks */ 207 sdhc0_lpcg: clock-controller@5b200000 { 208 compatible = "fsl,imx8qxp-lpcg"; 209 reg = <0x5b200000 0x10000>; 210 #clock-cells = <1>; 211 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 212 <&conn_ipg_clk>, <&conn_axi_clk>; 213 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 214 <IMX_LPCG_CLK_5>; 215 clock-output-names = "sdhc0_lpcg_per_clk", 216 "sdhc0_lpcg_ipg_clk", 217 "sdhc0_lpcg_ahb_clk"; 218 power-domains = <&pd IMX_SC_R_SDHC_0>; 219 }; 220 221 sdhc1_lpcg: clock-controller@5b210000 { 222 compatible = "fsl,imx8qxp-lpcg"; 223 reg = <0x5b210000 0x10000>; 224 #clock-cells = <1>; 225 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 226 <&conn_ipg_clk>, <&conn_axi_clk>; 227 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 228 <IMX_LPCG_CLK_5>; 229 clock-output-names = "sdhc1_lpcg_per_clk", 230 "sdhc1_lpcg_ipg_clk", 231 "sdhc1_lpcg_ahb_clk"; 232 power-domains = <&pd IMX_SC_R_SDHC_1>; 233 }; 234 235 sdhc2_lpcg: clock-controller@5b220000 { 236 compatible = "fsl,imx8qxp-lpcg"; 237 reg = <0x5b220000 0x10000>; 238 #clock-cells = <1>; 239 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 240 <&conn_ipg_clk>, <&conn_axi_clk>; 241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 242 <IMX_LPCG_CLK_5>; 243 clock-output-names = "sdhc2_lpcg_per_clk", 244 "sdhc2_lpcg_ipg_clk", 245 "sdhc2_lpcg_ahb_clk"; 246 power-domains = <&pd IMX_SC_R_SDHC_2>; 247 }; 248 249 enet0_lpcg: clock-controller@5b230000 { 250 compatible = "fsl,imx8qxp-lpcg"; 251 reg = <0x5b230000 0x10000>; 252 #clock-cells = <1>; 253 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 254 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 255 <&conn_axi_clk>, 256 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 257 <&conn_ipg_clk>, 258 <&conn_ipg_clk>; 259 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 260 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 261 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 262 clock-output-names = "enet0_lpcg_timer_clk", 263 "enet0_lpcg_txc_sampling_clk", 264 "enet0_lpcg_ahb_clk", 265 "enet0_lpcg_rgmii_txc_clk", 266 "enet0_lpcg_ipg_clk", 267 "enet0_lpcg_ipg_s_clk"; 268 power-domains = <&pd IMX_SC_R_ENET_0>; 269 }; 270 271 enet1_lpcg: clock-controller@5b240000 { 272 compatible = "fsl,imx8qxp-lpcg"; 273 reg = <0x5b240000 0x10000>; 274 #clock-cells = <1>; 275 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 276 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 277 <&conn_axi_clk>, 278 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, 279 <&conn_ipg_clk>, 280 <&conn_ipg_clk>; 281 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 282 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 283 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 284 clock-output-names = "enet1_lpcg_timer_clk", 285 "enet1_lpcg_txc_sampling_clk", 286 "enet1_lpcg_ahb_clk", 287 "enet1_lpcg_rgmii_txc_clk", 288 "enet1_lpcg_ipg_clk", 289 "enet1_lpcg_ipg_s_clk"; 290 power-domains = <&pd IMX_SC_R_ENET_1>; 291 }; 292 293 usb2_lpcg: clock-controller@5b270000 { 294 compatible = "fsl,imx8qxp-lpcg"; 295 reg = <0x5b270000 0x10000>; 296 #clock-cells = <1>; 297 clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; 298 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 299 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; 300 power-domains = <&pd IMX_SC_R_USB_0_PHY>; 301 }; 302 303 usb3_lpcg: clock-controller@5b280000 { 304 compatible = "fsl,imx8qxp-lpcg"; 305 reg = <0x5b280000 0x10000>; 306 #clock-cells = <1>; 307 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 308 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 309 <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 310 clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, 311 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, 312 <&conn_ipg_clk>, 313 <&conn_ipg_clk>, 314 <&conn_ipg_clk>, 315 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 316 clock-output-names = "usb3_app_clk", 317 "usb3_lpm_clk", 318 "usb3_ipg_clk", 319 "usb3_core_pclk", 320 "usb3_phy_clk", 321 "usb3_aclk"; 322 power-domains = <&pd IMX_SC_R_USB_2_PHY>; 323 }; 324 325 rawnand_0_lpcg: clock-controller@5b290000 { 326 compatible = "fsl,imx8qxp-lpcg"; 327 reg = <0x5b290000 0x4>; 328 #clock-cells = <1>; 329 clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, 330 <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, 331 <&conn_axi_clk>, 332 <&conn_axi_clk>; 333 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 334 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 335 clock-output-names = "gpmi_bch", 336 "gpmi_io", 337 "gpmi_apb", 338 "gpmi_bch_apb"; 339 power-domains = <&pd IMX_SC_R_NAND>; 340 }; 341 342 rawnand_4_lpcg: clock-controller@5b290004 { 343 compatible = "fsl,imx8qxp-lpcg"; 344 reg = <0x5b290004 0x10000>; 345 #clock-cells = <1>; 346 clocks = <&conn_axi_clk>; 347 clock-indices = <IMX_LPCG_CLK_4>; 348 clock-output-names = "apbhdma_hclk"; 349 power-domains = <&pd IMX_SC_R_NAND>; 350 }; 351 352 dma_apbh: dma-controller@5b810000 { 353 compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh"; 354 reg = <0x5b810000 0x2000>; 355 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 359 #dma-cells = <1>; 360 dma-channels = <4>; 361 clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>; 362 power-domains = <&pd IMX_SC_R_NAND>; 363 }; 364 365 gpmi: nand-controller@5b812000 { 366 compatible = "fsl,imx8qxp-gpmi-nand"; 367 reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; 368 reg-names = "gpmi-nand", "bch"; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-names = "bch"; 373 clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>, 374 <&rawnand_0_lpcg IMX_LPCG_CLK_4>, 375 <&rawnand_0_lpcg IMX_LPCG_CLK_0>, 376 <&rawnand_0_lpcg IMX_LPCG_CLK_5>; 377 clock-names = "gpmi_io", "gpmi_apb", 378 "gpmi_bch", "gpmi_bch_apb"; 379 dmas = <&dma_apbh 0>; 380 dma-names = "rx-tx"; 381 power-domains = <&pd IMX_SC_R_NAND>; 382 assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; 383 assigned-clock-rates = <50000000>; 384 status = "disabled"; 385 }; 386}; 387