1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com> 4 * Copyright (C) 2025 Engicam srl 5 */ 6 7/dts-v1/; 8 9 #include "imx6ull.dtsi" 10 11/ { 12 compatible = "engicam,microgea-imx6ull", "fsl,imx6ull"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x20000000>; 17 }; 18}; 19 20&fec1 { 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_phy_reset>; 23 phy-mode = "rmii"; 24 phy-handle = <ðphy0>; 25 local-mac-address = [00 00 00 00 00 00]; 26 status = "okay"; 27 28 mdio { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 ethphy0: ethernet-phy@0 { 33 compatible = "ethernet-phy-ieee802.3-c22"; 34 reg = <0>; 35 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 36 reset-assert-us = <4000>; 37 reset-deassert-us = <4000>; 38 }; 39 }; 40}; 41 42/* NAND */ 43&gpmi { 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_gpmi_nand>; 46 nand-ecc-mode = "hw"; 47 nand-ecc-strength = <0>; 48 nand-ecc-step-size = <0>; 49 nand-on-flash-bbt; 50 status = "okay"; 51}; 52 53&iomuxc { 54 pinctrl_enet1: enet1grp { 55 fsl,pins = < 56 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 57 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 58 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 59 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 60 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 61 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 62 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 63 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 64 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 65 >; 66 }; 67 68 pinctrl_gpmi_nand: gpminandgrp { 69 fsl,pins = < 70 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 71 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 72 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 73 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 74 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 75 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 76 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 77 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 78 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 79 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 80 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 81 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 82 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 83 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 84 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 85 >; 86 }; 87}; 88 89&iomuxc_snvs { 90 pinctrl_phy_reset: phy-resetgrp { 91 fsl,pins = < 92 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 93 >; 94 }; 95}; 96