1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2018-2022 Toradex 4 */ 5 6#include "imx6ull.dtsi" 7 8/ { 9 /* Ethernet aliases to ensure correct MAC addresses */ 10 aliases { 11 ethernet0 = &fec2; 12 ethernet1 = &fec1; 13 }; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 4 8 16 32 64 128 255>; 18 default-brightness-level = <6>; 19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_3v3>; 23 pwms = <&pwm4 0 5000000 1>; 24 status = "disabled"; 25 }; 26 27 connector { 28 compatible = "gpio-usb-b-connector", "usb-b-connector"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_snvs_usbc_det>; 31 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 32 label = "USBC"; 33 self-powered; 34 type = "micro"; 35 36 port { 37 usb_dr_connector: endpoint { 38 remote-endpoint = <&usb1_drd_sw>; 39 }; 40 }; 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_snvs_gpiokeys>; 47 48 key-wakeup { 49 debounce-interval = <10>; 50 gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 51 label = "Wake-Up"; 52 linux,code = <KEY_WAKEUP>; 53 wakeup-source; 54 }; 55 }; 56 57 panel_dpi: panel-dpi { 58 compatible = "edt,et057090dhu"; 59 backlight = <&backlight>; 60 power-supply = <®_3v3>; 61 status = "disabled"; 62 63 port { 64 lcd_panel_in: endpoint { 65 remote-endpoint = <&lcdif_out>; 66 }; 67 }; 68 }; 69 70 reg_module_3v3: regulator-module-3v3 { 71 compatible = "regulator-fixed"; 72 regulator-always-on; 73 regulator-name = "+V3.3"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 }; 77 78 reg_module_3v3_avdd: regulator-module-3v3-avdd { 79 compatible = "regulator-fixed"; 80 regulator-always-on; 81 regulator-name = "+V3.3_AVDD_AUDIO"; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 }; 85 86 reg_sd1_vqmmc: regulator-sd1-vqmmc { 87 compatible = "regulator-gpio"; 88 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 91 regulator-always-on; 92 regulator-name = "+V3.3_1.8_SD"; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <3300000>; 95 states = <1800000 0x1 3300000 0x0>; 96 vin-supply = <®_module_3v3>; 97 }; 98 99 reg_eth_phy: regulator-eth-phy { 100 compatible = "regulator-fixed-clock"; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 regulator-name = "+V3.3_ETH"; 105 vin-supply = <®_module_3v3>; 106 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 107 startup-delay-us = <150000>; 108 }; 109}; 110 111&adc1 { 112 vref-supply = <®_module_3v3_avdd>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_adc1>; 115}; 116 117&can1 { 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_flexcan1>; 120 status = "disabled"; 121}; 122 123&can2 { 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_flexcan2>; 126 status = "disabled"; 127}; 128 129/* Colibri SPI */ 130&ecspi1 { 131 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 134}; 135 136/* Ethernet */ 137&fec2 { 138 pinctrl-names = "default", "sleep"; 139 pinctrl-0 = <&pinctrl_enet2>; 140 pinctrl-1 = <&pinctrl_enet2_sleep>; 141 phy-mode = "rmii"; 142 phy-handle = <ðphy1>; 143 phy-supply = <®_eth_phy>; 144 status = "okay"; 145 146 mdio { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 150 ethphy1: ethernet-phy@2 { 151 compatible = "ethernet-phy-ieee802.3-c22"; 152 max-speed = <100>; 153 reg = <2>; 154 }; 155 }; 156}; 157 158/* NAND */ 159&gpmi { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_gpmi_nand>; 162 fsl,use-minimum-ecc; 163 nand-on-flash-bbt; 164 nand-ecc-mode = "hw"; 165 nand-ecc-strength = <8>; 166 nand-ecc-step-size = <512>; 167 status = "okay"; 168}; 169 170/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ 171&i2c1 { 172 pinctrl-names = "default", "gpio"; 173 pinctrl-0 = <&pinctrl_i2c1>; 174 pinctrl-1 = <&pinctrl_i2c1_gpio>; 175 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 176 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 177 status = "disabled"; 178 179 /* Atmel maxtouch controller */ 180 atmel_mxt_ts: touchscreen@4a { 181 compatible = "atmel,maxtouch"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; 184 reg = <0x4a>; 185 interrupt-parent = <&gpio5>; 186 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ 187 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ 188 status = "disabled"; 189 }; 190}; 191 192/* 193 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 194 * touch screen controller 195 */ 196&i2c2 { 197 /* Use low frequency to compensate for the high pull-up values. */ 198 clock-frequency = <40000>; 199 pinctrl-names = "default", "gpio"; 200 pinctrl-0 = <&pinctrl_i2c2>; 201 pinctrl-1 = <&pinctrl_i2c2_gpio>; 202 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 203 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 204 status = "okay"; 205 206 ad7879_ts: touchscreen@2c { 207 compatible = "adi,ad7879-1"; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 210 reg = <0x2c>; 211 interrupt-parent = <&gpio5>; 212 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 213 touchscreen-max-pressure = <4096>; 214 adi,resistance-plate-x = <120>; 215 adi,first-conversion-delay = /bits/ 8 <3>; 216 adi,acquisition-time = /bits/ 8 <1>; 217 adi,median-filter-size = /bits/ 8 <2>; 218 adi,averaging = /bits/ 8 <1>; 219 adi,conversion-interval = /bits/ 8 <255>; 220 status = "disabled"; 221 }; 222}; 223 224&lcdif { 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_lcdif_dat 227 &pinctrl_lcdif_ctrl>; 228 status = "disabled"; 229 230 port { 231 lcdif_out: endpoint { 232 remote-endpoint = <&lcd_panel_in>; 233 }; 234 }; 235}; 236 237/* PWM <A> */ 238&pwm4 { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_pwm4>; 241}; 242 243/* PWM <B> */ 244&pwm5 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_pwm5>; 247}; 248 249/* PWM <C> */ 250&pwm6 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_pwm6>; 253}; 254 255/* PWM <D> */ 256&pwm7 { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_pwm7>; 259}; 260 261&sdma { 262 status = "okay"; 263}; 264 265&snvs_pwrkey { 266 status = "disabled"; 267}; 268 269/* Colibri UART_A */ 270&uart1 { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 273 uart-has-rtscts; 274 fsl,dte-mode; 275}; 276 277/* Colibri UART_B */ 278&uart2 { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_uart2>; 281 uart-has-rtscts; 282 fsl,dte-mode; 283}; 284 285/* Colibri UART_C */ 286&uart5 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_uart5>; 289 fsl,dte-mode; 290}; 291 292/* Colibri USBC */ 293&usbotg1 { 294 dr_mode = "otg"; 295 srp-disable; 296 hnp-disable; 297 adp-disable; 298 usb-role-switch; 299 300 port { 301 usb1_drd_sw: endpoint { 302 remote-endpoint = <&usb_dr_connector>; 303 }; 304 }; 305}; 306 307/* Colibri USBH */ 308&usbotg2 { 309 dr_mode = "host"; 310}; 311 312/* Colibri MMC/SD */ 313&usdhc1 { 314 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 315 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 316 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 317 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 318 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; 319 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 320 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 321 assigned-clock-rates = <0>, <198000000>; 322 bus-width = <4>; 323 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 324 disable-wp; 325 keep-power-in-suspend; 326 no-1-8-v; 327 vqmmc-supply = <®_sd1_vqmmc>; 328 wakeup-source; 329}; 330 331&wdog1 { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_wdog>; 334 fsl,ext-reset-output; 335}; 336 337&iomuxc { 338 pinctrl_adc1: adc1grp { 339 fsl,pins = < 340 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ 341 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ 342 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ 343 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ 344 >; 345 }; 346 347 pinctrl_atmel_adap: atmeladapgrp { 348 fsl,pins = < 349 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ 350 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ 351 >; 352 }; 353 354 pinctrl_atmel_conn: atmelconngrp { 355 fsl,pins = < 356 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ 357 >; 358 }; 359 360 pinctrl_can_int: canintgrp { 361 fsl,pins = < 362 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ 363 >; 364 }; 365 366 pinctrl_enet2: enet2grp { 367 fsl,pins = < 368 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 369 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 370 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 371 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 372 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 373 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 374 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 375 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 376 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 377 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 378 >; 379 }; 380 381 pinctrl_enet2_sleep: enet2-sleepgrp { 382 fsl,pins = < 383 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 384 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 385 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 386 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 387 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 388 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 389 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 390 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 391 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 392 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 393 >; 394 }; 395 396 pinctrl_ecspi1_cs: ecspi1csgrp { 397 fsl,pins = < 398 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ 399 >; 400 }; 401 402 pinctrl_ecspi1: ecspi1grp { 403 fsl,pins = < 404 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ 405 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ 406 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ 407 >; 408 }; 409 410 pinctrl_flexcan1: flexcan1grp { 411 fsl,pins = < 412 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 413 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 414 >; 415 }; 416 417 pinctrl_flexcan2: flexcan2grp { 418 fsl,pins = < 419 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 420 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 421 >; 422 }; 423 424 pinctrl_gpio_bl_on: gpioblongrp { 425 fsl,pins = < 426 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ 427 >; 428 }; 429 430 pinctrl_gpio1: gpio1grp { 431 fsl,pins = < 432 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ 433 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ 434 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ 435 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ 436 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ 437 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ 438 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ 439 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ 440 >; 441 }; 442 443 pinctrl_gpio2: gpio2grp { /* Camera */ 444 fsl,pins = < 445 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ 446 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ 447 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ 448 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ 449 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ 450 >; 451 }; 452 453 pinctrl_gpio3: gpio3grp { /* CAN2 */ 454 fsl,pins = < 455 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ 456 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ 457 >; 458 }; 459 460 pinctrl_gpio4: gpio4grp { 461 fsl,pins = < 462 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ 463 >; 464 }; 465 466 pinctrl_gpio6: gpio6grp { /* Wifi pins */ 467 fsl,pins = < 468 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ 469 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ 470 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ 471 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ 472 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ 473 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ 474 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ 475 >; 476 }; 477 478 pinctrl_gpio7: gpio7grp { /* CAN1 */ 479 fsl,pins = < 480 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ 481 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ 482 >; 483 }; 484 485 /* 486 * With an eMMC instead of a raw NAND device the following pins 487 * are available at SODIMM pins. 488 */ 489 pinctrl_gpmi_gpio: gpmigpiogrp { 490 fsl,pins = < 491 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ 492 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ 493 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ 494 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ 495 >; 496 }; 497 498 pinctrl_gpmi_nand: gpminandgrp { 499 fsl,pins = < 500 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 501 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 502 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 503 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 504 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 505 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 506 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 507 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 508 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 509 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 510 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 511 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 512 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 513 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 514 >; 515 }; 516 517 pinctrl_i2c1: i2c1grp { 518 fsl,pins = < 519 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ 520 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ 521 >; 522 }; 523 524 pinctrl_i2c1_gpio: i2c1-gpiogrp { 525 fsl,pins = < 526 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ 527 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ 528 >; 529 }; 530 531 pinctrl_i2c2: i2c2grp { 532 fsl,pins = < 533 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 534 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 535 >; 536 }; 537 538 pinctrl_i2c2_gpio: i2c2-gpiogrp { 539 fsl,pins = < 540 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 541 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 542 >; 543 }; 544 545 pinctrl_lcdif_dat: lcdifdatgrp { 546 fsl,pins = < 547 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ 548 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ 549 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ 550 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ 551 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ 552 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ 553 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ 554 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ 555 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ 556 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ 557 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ 558 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ 559 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ 560 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ 561 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ 562 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ 563 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ 564 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ 565 >; 566 }; 567 568 pinctrl_lcdif_ctrl: lcdifctrlgrp { 569 fsl,pins = < 570 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ 571 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ 572 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ 573 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ 574 >; 575 }; 576 577 pinctrl_pwm4: pwm4grp { 578 fsl,pins = < 579 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ 580 >; 581 }; 582 583 pinctrl_pwm5: pwm5grp { 584 fsl,pins = < 585 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ 586 >; 587 }; 588 589 pinctrl_pwm6: pwm6grp { 590 fsl,pins = < 591 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ 592 >; 593 }; 594 595 pinctrl_pwm7: pwm7grp { 596 fsl,pins = < 597 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ 598 >; 599 }; 600 601 pinctrl_uart1: uart1grp { 602 fsl,pins = < 603 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ 604 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ 605 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ 606 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ 607 >; 608 }; 609 610 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ 611 fsl,pins = < 612 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ 613 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ 614 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ 615 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ 616 >; 617 }; 618 619 pinctrl_uart2: uart2grp { 620 fsl,pins = < 621 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ 622 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ 623 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ 624 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ 625 >; 626 }; 627 pinctrl_uart5: uart5grp { 628 fsl,pins = < 629 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ 630 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ 631 >; 632 }; 633 634 pinctrl_usbh_reg: usbhreggrp { 635 fsl,pins = < 636 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ 637 >; 638 }; 639 640 pinctrl_usdhc1: usdhc1grp { 641 fsl,pins = < 642 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ 643 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ 644 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ 645 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ 646 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ 647 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ 648 >; 649 }; 650 651 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 652 fsl,pins = < 653 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 654 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 655 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 656 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 657 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 658 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 659 >; 660 }; 661 662 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 663 fsl,pins = < 664 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 665 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 666 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 667 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 668 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 669 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 670 >; 671 }; 672 673 pinctrl_usdhc2: usdhc2grp { 674 fsl,pins = < 675 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 676 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 677 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 678 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 679 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 680 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 681 682 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 683 >; 684 }; 685 686 pinctrl_usdhc2emmc: usdhc2emmcgrp { 687 fsl,pins = < 688 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 689 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 690 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 691 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 692 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 693 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 694 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 695 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 696 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 697 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 698 >; 699 }; 700 701 pinctrl_wdog: wdoggrp { 702 fsl,pins = < 703 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 704 >; 705 }; 706}; 707 708&iomuxc_snvs { 709 pinctrl_atmel_snvs_conn: atmelsnvsconngrp { 710 fsl,pins = < 711 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ 712 >; 713 }; 714 715 pinctrl_snvs_gpio1: snvsgpio1grp { 716 fsl,pins = < 717 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ 718 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ 719 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ 720 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ 721 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ 722 >; 723 }; 724 725 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ 726 fsl,pins = < 727 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ 728 >; 729 }; 730 731 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ 732 fsl,pins = < 733 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 734 >; 735 }; 736 737 pinctrl_snvs_reg_sd: snvsregsdgrp { 738 fsl,pins = < 739 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 740 >; 741 }; 742 743 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 744 fsl,pins = < 745 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 746 >; 747 }; 748 749 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { 750 fsl,pins = < 751 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ 752 >; 753 }; 754 755 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { 756 fsl,pins = < 757 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ 758 >; 759 }; 760 761 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { 762 fsl,pins = < 763 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 764 >; 765 }; 766 767 pinctrl_snvs_wifi_pdn: snvswifipdngrp { 768 fsl,pins = < 769 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 770 >; 771 }; 772}; 773