1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/pwm/pwm.h> 9 10/ { 11 aliases { 12 can0 = &can2; 13 can1 = &can1; 14 display = &display; 15 i2c0 = &i2c2; 16 i2c1 = &i2c_gpio; 17 i2c2 = &i2c1; 18 i2c3 = &i2c3; 19 i2c4 = &i2c4; 20 lcdif-23bit-pins-a = &pinctrl_disp0_1; 21 lcdif-24bit-pins-a = &pinctrl_disp0_2; 22 pwm0 = &pwm5; 23 reg-can-xcvr = ®_can_xcvr; 24 serial2 = &uart5; 25 serial4 = &uart3; 26 spi0 = &ecspi2; 27 spi1 = &spi_gpio; 28 stk5led = &user_led; 29 usbh1 = &usbotg2; 30 usbotg = &usbotg1; 31 }; 32 33 chosen { 34 stdout-path = &uart1; 35 }; 36 37 memory@80000000 { 38 device_type = "memory"; 39 reg = <0x80000000 0>; /* will be filled by U-Boot */ 40 }; 41 42 clocks { 43 mclk: mclk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <26000000>; 47 }; 48 }; 49 50 backlight: backlight { 51 compatible = "pwm-backlight"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_lcd_rst>; 54 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; 55 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; 56 power-supply = <®_lcd_pwr>; 57 /* 58 * a poor man's way to create a 1:1 relationship between 59 * the PWM value and the actual duty cycle 60 */ 61 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 62 10 11 12 13 14 15 16 17 18 19 63 20 21 22 23 24 25 26 27 28 29 64 30 31 32 33 34 35 36 37 38 39 65 40 41 42 43 44 45 46 47 48 49 66 50 51 52 53 54 55 56 57 58 59 67 60 61 62 63 64 65 66 67 68 69 68 70 71 72 73 74 75 76 77 78 79 69 80 81 82 83 84 85 86 87 88 89 70 90 91 92 93 94 95 96 97 98 99 71 100>; 72 default-brightness-level = <50>; 73 }; 74 75 i2c_gpio: i2c-gpio { 76 compatible = "i2c-gpio"; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_i2c_gpio>; 81 sda-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 82 scl-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; 83 clock-frequency = <400000>; 84 status = "okay"; 85 86 ds1339: rtc@68 { 87 compatible = "dallas,ds1339"; 88 reg = <0x68>; 89 status = "disabled"; 90 }; 91 }; 92 93 leds { 94 compatible = "gpio-leds"; 95 96 user_led: led-user { 97 label = "Heartbeat"; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_led>; 100 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 101 linux,default-trigger = "heartbeat"; 102 }; 103 }; 104 105 reg_3v3_etn: regulator-3v3etn { 106 compatible = "regulator-fixed"; 107 regulator-name = "3V3_ETN"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_etnphy_power>; 112 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; 113 enable-active-high; 114 }; 115 116 reg_2v5: regulator-2v5 { 117 compatible = "regulator-fixed"; 118 regulator-name = "2V5"; 119 regulator-min-microvolt = <2500000>; 120 regulator-max-microvolt = <2500000>; 121 regulator-always-on; 122 }; 123 124 reg_3v3: regulator-3v3 { 125 compatible = "regulator-fixed"; 126 regulator-name = "3V3"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 regulator-always-on; 130 }; 131 132 reg_can_xcvr: regulator-canxcvr { 133 compatible = "regulator-fixed"; 134 regulator-name = "CAN XCVR"; 135 regulator-min-microvolt = <3300000>; 136 regulator-max-microvolt = <3300000>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_flexcan_xcvr>; 139 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; 140 }; 141 142 reg_lcd_pwr: regulator-lcdpwr { 143 compatible = "regulator-fixed"; 144 regulator-name = "LCD POWER"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_lcd_pwr>; 149 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; 150 enable-active-high; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 reg_usbh1_vbus: regulator-usbh1vbus { 156 compatible = "regulator-fixed"; 157 regulator-name = "usbh1_vbus"; 158 regulator-min-microvolt = <5000000>; 159 regulator-max-microvolt = <5000000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; 162 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 }; 165 166 reg_usbotg_vbus: regulator-usbotgvbus { 167 compatible = "regulator-fixed"; 168 regulator-name = "usbotg_vbus"; 169 regulator-min-microvolt = <5000000>; 170 regulator-max-microvolt = <5000000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; 173 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; 174 enable-active-high; 175 }; 176 177 spi_gpio: spi { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 compatible = "spi-gpio"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_spi_gpio>; 183 mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 184 miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; 185 sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 186 num-chipselects = <2>; 187 cs-gpios = < 188 &gpio1 29 GPIO_ACTIVE_HIGH 189 &gpio1 10 GPIO_ACTIVE_HIGH 190 >; 191 status = "disabled"; 192 }; 193 194 sound { 195 compatible = "karo,imx6ul-tx6ul-sgtl5000", 196 "simple-audio-card"; 197 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; 198 simple-audio-card,format = "i2s"; 199 simple-audio-card,bitclock-master = <&codec_dai>; 200 simple-audio-card,frame-master = <&codec_dai>; 201 simple-audio-card,widgets = 202 "Microphone", "Mic Jack", 203 "Line", "Line In", 204 "Line", "Line Out", 205 "Headphone", "Headphone Jack"; 206 simple-audio-card,routing = 207 "MIC_IN", "Mic Jack", 208 "Mic Jack", "Mic Bias", 209 "Headphone Jack", "HP_OUT"; 210 211 cpu_dai: simple-audio-card,cpu { 212 sound-dai = <&sai2>; 213 }; 214 215 codec_dai: simple-audio-card,codec { 216 sound-dai = <&sgtl5000>; 217 }; 218 }; 219}; 220 221&can1 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_flexcan1>; 224 xceiver-supply = <®_can_xcvr>; 225 status = "okay"; 226}; 227 228&can2 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_flexcan2>; 231 xceiver-supply = <®_can_xcvr>; 232 status = "okay"; 233}; 234 235&ecspi2 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_ecspi2>; 238 cs-gpios = < 239 &gpio1 29 GPIO_ACTIVE_HIGH 240 &gpio1 10 GPIO_ACTIVE_HIGH 241 >; 242 status = "disabled"; 243}; 244 245&fec1 { 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; 248 phy-mode = "rmii"; 249 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 250 phy-supply = <®_3v3_etn>; 251 phy-handle = <&etnphy0>; 252 status = "okay"; 253 254 mdio { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 etnphy0: ethernet-phy@0 { 259 compatible = "ethernet-phy-ieee802.3-c22"; 260 reg = <0>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_etnphy0_int>; 263 interrupt-parent = <&gpio5>; 264 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 265 status = "okay"; 266 }; 267 268 etnphy1: ethernet-phy@2 { 269 compatible = "ethernet-phy-ieee802.3-c22"; 270 reg = <2>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_etnphy1_int>; 273 interrupt-parent = <&gpio4>; 274 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 275 status = "okay"; 276 }; 277 }; 278}; 279 280&fec2 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; 283 phy-mode = "rmii"; 284 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 285 phy-supply = <®_3v3_etn>; 286 phy-handle = <&etnphy1>; 287 status = "disabled"; 288}; 289 290&gpmi { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_gpmi_nand>; 293 nand-on-flash-bbt; 294 fsl,no-blockmark-swap; 295 status = "okay"; 296}; 297 298&i2c2 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_i2c2>; 301 clock-frequency = <400000>; 302 status = "okay"; 303 304 sgtl5000: codec@a { 305 compatible = "fsl,sgtl5000"; 306 reg = <0x0a>; 307 #sound-dai-cells = <0>; 308 VDDA-supply = <®_2v5>; 309 VDDIO-supply = <®_3v3>; 310 clocks = <&mclk>; 311 }; 312 313 polytouch: polytouch@38 { 314 compatible = "edt,edt-ft5x06"; 315 reg = <0x38>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_edt_ft5x06>; 318 interrupt-parent = <&gpio5>; 319 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 320 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 321 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 322 wakeup-source; 323 }; 324 325 touchscreen: touchscreen@48 { 326 compatible = "ti,tsc2007"; 327 reg = <0x48>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_tsc2007>; 330 interrupt-parent = <&gpio3>; 331 interrupts = <26 IRQ_TYPE_NONE>; 332 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 333 ti,x-plate-ohms = <660>; 334 wakeup-source; 335 }; 336}; 337 338&kpp { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_kpp>; 341 /* sample keymap */ 342 /* row/col 0..3 are mapped to KPP row/col 4..7 */ 343 linux,keymap = < 344 MATRIX_KEY(4, 4, KEY_POWER) 345 MATRIX_KEY(4, 5, KEY_KP0) 346 MATRIX_KEY(4, 6, KEY_KP1) 347 MATRIX_KEY(4, 7, KEY_KP2) 348 MATRIX_KEY(5, 4, KEY_KP3) 349 MATRIX_KEY(5, 5, KEY_KP4) 350 MATRIX_KEY(5, 6, KEY_KP5) 351 MATRIX_KEY(5, 7, KEY_KP6) 352 MATRIX_KEY(6, 4, KEY_KP7) 353 MATRIX_KEY(6, 5, KEY_KP8) 354 MATRIX_KEY(6, 6, KEY_KP9) 355 >; 356 status = "okay"; 357}; 358 359&lcdif { 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_disp0_1>; 362 lcd-supply = <®_lcd_pwr>; 363 display = <&display>; 364 status = "okay"; 365 366 display: disp0 { 367 bits-per-pixel = <32>; 368 bus-width = <24>; 369 status = "okay"; 370 371 display-timings { 372 timing-vga { 373 clock-frequency = <25200000>; 374 hactive = <640>; 375 vactive = <480>; 376 hback-porch = <48>; 377 hsync-len = <96>; 378 hfront-porch = <16>; 379 vback-porch = <31>; 380 vsync-len = <2>; 381 vfront-porch = <12>; 382 hsync-active = <0>; 383 vsync-active = <0>; 384 de-active = <1>; 385 pixelclk-active = <1>; 386 }; 387 388 timing-etv570 { 389 clock-frequency = <25200000>; 390 hactive = <640>; 391 vactive = <480>; 392 hback-porch = <114>; 393 hsync-len = <30>; 394 hfront-porch = <16>; 395 vback-porch = <32>; 396 vsync-len = <3>; 397 vfront-porch = <10>; 398 hsync-active = <0>; 399 vsync-active = <0>; 400 de-active = <1>; 401 pixelclk-active = <1>; 402 }; 403 404 timing-et0350 { 405 clock-frequency = <6413760>; 406 hactive = <320>; 407 vactive = <240>; 408 hback-porch = <34>; 409 hsync-len = <34>; 410 hfront-porch = <20>; 411 vback-porch = <15>; 412 vsync-len = <3>; 413 vfront-porch = <4>; 414 hsync-active = <0>; 415 vsync-active = <0>; 416 de-active = <1>; 417 pixelclk-active = <1>; 418 }; 419 420 timing-et0430 { 421 clock-frequency = <9009000>; 422 hactive = <480>; 423 vactive = <272>; 424 hback-porch = <2>; 425 hsync-len = <41>; 426 hfront-porch = <2>; 427 vback-porch = <2>; 428 vsync-len = <10>; 429 vfront-porch = <2>; 430 hsync-active = <0>; 431 vsync-active = <0>; 432 de-active = <1>; 433 pixelclk-active = <0>; 434 }; 435 436 timing-et0500 { 437 clock-frequency = <33264000>; 438 hactive = <800>; 439 vactive = <480>; 440 hback-porch = <88>; 441 hsync-len = <128>; 442 hfront-porch = <40>; 443 vback-porch = <33>; 444 vsync-len = <2>; 445 vfront-porch = <10>; 446 hsync-active = <0>; 447 vsync-active = <0>; 448 de-active = <1>; 449 pixelclk-active = <1>; 450 }; 451 452 timing-et0700 { /* same as ET0500 */ 453 clock-frequency = <33264000>; 454 hactive = <800>; 455 vactive = <480>; 456 hback-porch = <88>; 457 hsync-len = <128>; 458 hfront-porch = <40>; 459 vback-porch = <33>; 460 vsync-len = <2>; 461 vfront-porch = <10>; 462 hsync-active = <0>; 463 vsync-active = <0>; 464 de-active = <1>; 465 pixelclk-active = <1>; 466 }; 467 468 timing-etq570 { 469 clock-frequency = <6596040>; 470 hactive = <320>; 471 vactive = <240>; 472 hback-porch = <38>; 473 hsync-len = <30>; 474 hfront-porch = <30>; 475 vback-porch = <16>; 476 vsync-len = <3>; 477 vfront-porch = <4>; 478 hsync-active = <0>; 479 vsync-active = <0>; 480 de-active = <1>; 481 pixelclk-active = <1>; 482 }; 483 }; 484 }; 485}; 486 487&pwm5 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_pwm5>; 490 status = "okay"; 491}; 492 493&sai2 { 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_sai2>; 496 status = "okay"; 497}; 498 499&uart1 { 500 pinctrl-names = "default"; 501 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; 502 uart-has-rtscts; 503 status = "okay"; 504}; 505 506&uart2 { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; 509 uart-has-rtscts; 510 status = "okay"; 511}; 512 513&uart5 { 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; 516 uart-has-rtscts; 517 status = "okay"; 518}; 519 520&usbotg1 { 521 vbus-supply = <®_usbotg_vbus>; 522 dr_mode = "peripheral"; 523 disable-over-current; 524 status = "okay"; 525}; 526 527&usbotg2 { 528 vbus-supply = <®_usbh1_vbus>; 529 dr_mode = "host"; 530 disable-over-current; 531 status = "okay"; 532}; 533 534&usdhc1 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; 537 bus-width = <4>; 538 no-1-8-v; 539 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; 540 fsl,wp-controller; 541 status = "okay"; 542}; 543 544&iomuxc { 545 pinctrl_led: ledgrp { 546 fsl,pins = < 547 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ 548 >; 549 }; 550 551 pinctrl_disp0_1: disp0-1-grp { 552 fsl,pins = < 553 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ 554 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ 555 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ 556 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ 557 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ 558 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 559 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 560 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 561 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 562 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 563 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 564 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 565 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 566 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 567 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 568 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 569 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 570 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 571 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 572 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 573 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 574 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 575 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 576 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 577 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 578 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 579 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 580 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 581 >; 582 }; 583 584 pinctrl_disp0_2: disp0-2-grp { 585 fsl,pins = < 586 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ 587 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ 588 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ 589 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ 590 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 591 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 592 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 593 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 594 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 595 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 596 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 597 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 598 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 599 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 600 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 601 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 602 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 603 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 604 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 605 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 606 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 607 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 608 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 609 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 610 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 611 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 612 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 613 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 614 >; 615 }; 616 617 pinctrl_ecspi2: ecspi2grp { 618 fsl,pins = < 619 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ 620 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ 621 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ 622 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ 623 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ 624 >; 625 }; 626 627 pinctrl_edt_ft5x06: edt-ft5x06grp { 628 fsl,pins = < 629 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ 630 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ 631 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ 632 >; 633 }; 634 635 pinctrl_enet1: enet1grp { 636 fsl,pins = < 637 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 638 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 639 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 640 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 641 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 642 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 643 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 644 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 645 >; 646 }; 647 648 pinctrl_enet2: enet2grp { 649 fsl,pins = < 650 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 651 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 652 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 653 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 654 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 655 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 656 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 657 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 658 >; 659 }; 660 661 pinctrl_enet1_mdio: enet1-mdiogrp { 662 fsl,pins = < 663 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 664 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 665 >; 666 }; 667 668 pinctrl_etnphy_power: etnphy-pwrgrp { 669 fsl,pins = < 670 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ 671 >; 672 }; 673 674 pinctrl_etnphy0_int: etnphy-int-0-grp { 675 fsl,pins = < 676 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ 677 >; 678 }; 679 680 pinctrl_etnphy0_rst: etnphy-rst-0-grp { 681 fsl,pins = < 682 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ 683 >; 684 }; 685 686 pinctrl_etnphy1_int: etnphy-int-1-grp { 687 fsl,pins = < 688 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ 689 >; 690 }; 691 692 pinctrl_etnphy1_rst: etnphy-rst-1-grp { 693 fsl,pins = < 694 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ 695 >; 696 }; 697 698 pinctrl_flexcan1: flexcan1grp { 699 fsl,pins = < 700 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 701 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 702 >; 703 }; 704 705 pinctrl_flexcan2: flexcan2grp { 706 fsl,pins = < 707 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 708 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 709 >; 710 }; 711 712 pinctrl_flexcan_xcvr: flexcan-xcvrgrp { 713 fsl,pins = < 714 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ 715 >; 716 }; 717 718 pinctrl_gpmi_nand: gpminandgrp { 719 fsl,pins = < 720 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 721 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 722 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 723 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 724 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 725 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 726 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 727 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 728 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 729 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 730 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 731 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 732 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 733 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 734 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 735 >; 736 }; 737 738 pinctrl_i2c_gpio: i2c-gpiogrp { 739 fsl,pins = < 740 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ 741 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ 742 >; 743 }; 744 745 pinctrl_i2c2: i2c2grp { 746 fsl,pins = < 747 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 748 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 749 >; 750 }; 751 752 pinctrl_kpp: kppgrp { 753 fsl,pins = < 754 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 755 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 756 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 757 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 758 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 759 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 760 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 761 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 762 >; 763 }; 764 765 pinctrl_lcd_pwr: lcd-pwrgrp { 766 fsl,pins = < 767 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ 768 >; 769 }; 770 771 pinctrl_lcd_rst: lcd-rstgrp { 772 fsl,pins = < 773 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ 774 >; 775 }; 776 777 pinctrl_pwm5: pwm5grp { 778 fsl,pins = < 779 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 780 >; 781 }; 782 783 pinctrl_sai2: sai2grp { 784 fsl,pins = < 785 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ 786 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ 787 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ 788 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ 789 >; 790 }; 791 792 pinctrl_spi_gpio: spi-gpiogrp { 793 fsl,pins = < 794 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ 795 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ 796 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ 797 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ 798 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ 799 >; 800 }; 801 802 pinctrl_tsc2007: tsc2007grp { 803 fsl,pins = < 804 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ 805 >; 806 }; 807 808 pinctrl_uart1: uart1grp { 809 fsl,pins = < 810 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 811 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 812 >; 813 }; 814 815 pinctrl_uart1_rtscts: uart1-rtsctsgrp { 816 fsl,pins = < 817 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 818 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 819 >; 820 }; 821 822 pinctrl_uart2: uart2grp { 823 fsl,pins = < 824 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 825 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 826 >; 827 }; 828 829 pinctrl_uart2_rtscts: uart2-rtsctsgrp { 830 fsl,pins = < 831 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 832 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 833 >; 834 }; 835 836 pinctrl_uart5: uart5grp { 837 fsl,pins = < 838 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 839 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 840 >; 841 }; 842 843 pinctrl_uart5_rtscts: uart5-rtsctsgrp { 844 fsl,pins = < 845 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 846 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 847 >; 848 }; 849 850 pinctrl_usbh1_oc: usbh1-ocgrp { 851 fsl,pins = < 852 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ 853 >; 854 }; 855 856 pinctrl_usbh1_vbus: usbh1-vbusgrp { 857 fsl,pins = < 858 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ 859 >; 860 }; 861 862 pinctrl_usbotg_oc: usbotg-ocgrp { 863 fsl,pins = < 864 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ 865 >; 866 }; 867 868 pinctrl_usbotg_vbus: usbotg-vbusgrp { 869 fsl,pins = < 870 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ 871 >; 872 }; 873 874 pinctrl_usdhc1: usdhc1grp { 875 fsl,pins = < 876 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 877 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 878 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 879 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 880 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 881 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 882 >; 883 }; 884 885 pinctrl_usdhc1_cd: usdhc1cdgrp { 886 fsl,pins = < 887 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ 888 >; 889 }; 890 891 pinctrl_usdhc2: usdhc2grp { 892 fsl,pins = < 893 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 894 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 895 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 896 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 897 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 898 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 899 /* eMMC RESET */ 900 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 901 >; 902 }; 903}; 904