1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 ethernet0 = &fec; 14 ethernet1 = &lan1; 15 ethernet2 = &lan2; 16 ethernet3 = &lan3; 17 ethernet4 = &lan4; 18 led0 = &led0; 19 led1 = &led1; 20 led2 = &led2; 21 usb0 = &usbh1; 22 usb1 = &usbotg; 23 }; 24 25 chosen { 26 stdout-path = &uart2; 27 }; 28 29 backlight { 30 compatible = "pwm-backlight"; 31 pwms = <&pwm4 0 5000000 0>; 32 brightness-levels = <0 4 8 16 32 64 128 255>; 33 default-brightness-level = <7>; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys"; 38 39 user-pb { 40 label = "user_pb"; 41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 42 linux,code = <BTN_0>; 43 }; 44 45 user-pb1x { 46 label = "user_pb1x"; 47 linux,code = <BTN_1>; 48 interrupt-parent = <&gsc>; 49 interrupts = <0>; 50 }; 51 52 key-erased { 53 label = "key-erased"; 54 linux,code = <BTN_2>; 55 interrupt-parent = <&gsc>; 56 interrupts = <1>; 57 }; 58 59 eeprom-wp { 60 label = "eeprom_wp"; 61 linux,code = <BTN_3>; 62 interrupt-parent = <&gsc>; 63 interrupts = <2>; 64 }; 65 66 tamper { 67 label = "tamper"; 68 linux,code = <BTN_4>; 69 interrupt-parent = <&gsc>; 70 interrupts = <5>; 71 }; 72 73 switch-hold { 74 label = "switch_hold"; 75 linux,code = <BTN_5>; 76 interrupt-parent = <&gsc>; 77 interrupts = <7>; 78 }; 79 }; 80 81 leds { 82 compatible = "gpio-leds"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_gpio_leds>; 85 86 led0: led-user1 { 87 label = "user1"; 88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 89 default-state = "on"; 90 linux,default-trigger = "heartbeat"; 91 }; 92 93 led1: led-user2 { 94 label = "user2"; 95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 96 default-state = "off"; 97 }; 98 99 led2: led-user3 { 100 label = "user3"; 101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 102 default-state = "off"; 103 }; 104 }; 105 106 memory@10000000 { 107 device_type = "memory"; 108 reg = <0x10000000 0x40000000>; 109 }; 110 111 pps { 112 compatible = "pps-gpio"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_pps>; 115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 116 }; 117 118 reg_1p0v: regulator-1p0v { 119 compatible = "regulator-fixed"; 120 regulator-name = "1P0V"; 121 regulator-min-microvolt = <1000000>; 122 regulator-max-microvolt = <1000000>; 123 regulator-always-on; 124 }; 125 126 reg_3p3v: regulator-3p3v { 127 compatible = "regulator-fixed"; 128 regulator-name = "3P3V"; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 regulator-always-on; 132 }; 133 134 reg_usb_h1_vbus: regulator-usb-h1-vbus { 135 compatible = "regulator-fixed"; 136 regulator-name = "usb_h1_vbus"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 regulator-always-on; 140 }; 141 142 reg_usb_otg_vbus: regulator-usb-otg-vbus { 143 compatible = "regulator-fixed"; 144 regulator-name = "usb_otg_vbus"; 145 regulator-min-microvolt = <5000000>; 146 regulator-max-microvolt = <5000000>; 147 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 148 enable-active-high; 149 }; 150}; 151 152&clks { 153 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 154 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 155 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 156 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 157}; 158 159&fec { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_enet>; 162 phy-mode = "rgmii-id"; 163 status = "okay"; 164 165 fixed-link { 166 speed = <1000>; 167 full-duplex; 168 }; 169 170 mdio { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 switch@0 { 175 compatible = "marvell,mv88e6085"; 176 reg = <0>; 177 178 mdio { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 sw_phy0: ethernet-phy@0 { 183 reg = <0x0>; 184 }; 185 186 sw_phy1: ethernet-phy@1 { 187 reg = <0x1>; 188 }; 189 190 sw_phy2: ethernet-phy@2 { 191 reg = <0x2>; 192 }; 193 194 sw_phy3: ethernet-phy@3 { 195 reg = <0x3>; 196 }; 197 }; 198 199 ports { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 lan4: port@0 { 204 reg = <0>; 205 label = "lan4"; 206 phy-handle = <&sw_phy0>; 207 phy-mode = "internal"; 208 local-mac-address = [00 00 00 00 00 00]; 209 }; 210 211 lan3: port@1 { 212 reg = <1>; 213 label = "lan3"; 214 phy-handle = <&sw_phy1>; 215 phy-mode = "internal"; 216 local-mac-address = [00 00 00 00 00 00]; 217 }; 218 219 lan2: port@2 { 220 reg = <2>; 221 label = "lan2"; 222 phy-handle = <&sw_phy2>; 223 phy-mode = "internal"; 224 local-mac-address = [00 00 00 00 00 00]; 225 }; 226 227 lan1: port@3 { 228 reg = <3>; 229 label = "lan1"; 230 phy-handle = <&sw_phy3>; 231 phy-mode = "internal"; 232 local-mac-address = [00 00 00 00 00 00]; 233 }; 234 235 port@5 { 236 reg = <5>; 237 ethernet = <&fec>; 238 phy-mode = "rgmii-id"; 239 240 fixed-link { 241 speed = <1000>; 242 full-duplex; 243 }; 244 }; 245 }; 246 }; 247 }; 248}; 249 250&i2c1 { 251 clock-frequency = <100000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c1>; 254 status = "okay"; 255 256 gsc: gsc@20 { 257 compatible = "gw,gsc"; 258 reg = <0x20>; 259 interrupt-parent = <&gpio1>; 260 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 261 interrupt-controller; 262 #interrupt-cells = <1>; 263 #size-cells = <0>; 264 265 adc { 266 compatible = "gw,gsc-adc"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 channel@0 { 271 gw,mode = <0>; 272 reg = <0x00>; 273 label = "temp"; 274 }; 275 276 channel@2 { 277 gw,mode = <1>; 278 reg = <0x02>; 279 label = "vdd_vin"; 280 }; 281 282 channel@5 { 283 gw,mode = <1>; 284 reg = <0x05>; 285 label = "vdd_3p3"; 286 }; 287 288 channel@8 { 289 gw,mode = <1>; 290 reg = <0x08>; 291 label = "vdd_bat"; 292 }; 293 294 channel@b { 295 gw,mode = <1>; 296 reg = <0x0b>; 297 label = "vdd_5p0"; 298 }; 299 300 channel@e { 301 gw,mode = <1>; 302 reg = <0xe>; 303 label = "vdd_arm"; 304 }; 305 306 channel@11 { 307 gw,mode = <1>; 308 reg = <0x11>; 309 label = "vdd_soc"; 310 }; 311 312 channel@14 { 313 gw,mode = <1>; 314 reg = <0x14>; 315 label = "vdd_3p0"; 316 }; 317 318 channel@17 { 319 gw,mode = <1>; 320 reg = <0x17>; 321 label = "vdd_1p5"; 322 }; 323 324 channel@1d { 325 gw,mode = <1>; 326 reg = <0x1d>; 327 label = "vdd_1p8"; 328 }; 329 330 channel@20 { 331 gw,mode = <1>; 332 reg = <0x20>; 333 label = "vdd_an1"; 334 }; 335 336 channel@23 { 337 gw,mode = <1>; 338 reg = <0x23>; 339 label = "vdd_2p5"; 340 }; 341 }; 342 }; 343 344 gsc_gpio: gpio@23 { 345 compatible = "nxp,pca9555"; 346 reg = <0x23>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-parent = <&gsc>; 350 interrupts = <4>; 351 }; 352 353 eeprom1: eeprom@50 { 354 compatible = "atmel,24c02"; 355 reg = <0x50>; 356 pagesize = <16>; 357 }; 358 359 eeprom2: eeprom@51 { 360 compatible = "atmel,24c02"; 361 reg = <0x51>; 362 pagesize = <16>; 363 }; 364 365 eeprom3: eeprom@52 { 366 compatible = "atmel,24c02"; 367 reg = <0x52>; 368 pagesize = <16>; 369 }; 370 371 eeprom4: eeprom@53 { 372 compatible = "atmel,24c02"; 373 reg = <0x53>; 374 pagesize = <16>; 375 }; 376 377 dts1672: rtc@68 { 378 compatible = "dallas,ds1672"; 379 reg = <0x68>; 380 }; 381}; 382 383&i2c2 { 384 clock-frequency = <100000>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_i2c2>; 387 status = "okay"; 388 389 magn@1c { 390 compatible = "st,lsm9ds1-magn"; 391 reg = <0x1c>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_mag>; 394 interrupt-parent = <&gpio5>; 395 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 396 }; 397 398 ltc3676: pmic@3c { 399 compatible = "lltc,ltc3676"; 400 reg = <0x3c>; 401 interrupt-parent = <&gpio1>; 402 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 403 404 regulators { 405 /* VDD_SOC (1+R1/R2 = 1.635) */ 406 reg_vdd_soc: sw1 { 407 regulator-name = "vddsoc"; 408 regulator-min-microvolt = <674400>; 409 regulator-max-microvolt = <1308000>; 410 lltc,fb-voltage-divider = <127000 200000>; 411 regulator-ramp-delay = <7000>; 412 regulator-boot-on; 413 regulator-always-on; 414 }; 415 416 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 417 reg_1p8v: sw2 { 418 regulator-name = "vdd1p8"; 419 regulator-min-microvolt = <1033310>; 420 regulator-max-microvolt = <2004000>; 421 lltc,fb-voltage-divider = <301000 200000>; 422 regulator-ramp-delay = <7000>; 423 regulator-boot-on; 424 regulator-always-on; 425 }; 426 427 /* VDD_ARM (1+R1/R2 = 1.635) */ 428 reg_vdd_arm: sw3 { 429 regulator-name = "vddarm"; 430 regulator-min-microvolt = <674400>; 431 regulator-max-microvolt = <1308000>; 432 lltc,fb-voltage-divider = <127000 200000>; 433 regulator-ramp-delay = <7000>; 434 regulator-boot-on; 435 regulator-always-on; 436 }; 437 438 /* VDD_DDR (1+R1/R2 = 2.105) */ 439 reg_vdd_ddr: sw4 { 440 regulator-name = "vddddr"; 441 regulator-min-microvolt = <868310>; 442 regulator-max-microvolt = <1684000>; 443 lltc,fb-voltage-divider = <221000 200000>; 444 regulator-ramp-delay = <7000>; 445 regulator-boot-on; 446 regulator-always-on; 447 }; 448 449 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 450 reg_2p5v: ldo2 { 451 regulator-name = "vdd2p5"; 452 regulator-min-microvolt = <2490375>; 453 regulator-max-microvolt = <2490375>; 454 lltc,fb-voltage-divider = <487000 200000>; 455 regulator-boot-on; 456 regulator-always-on; 457 }; 458 459 /* VDD_HIGH (1+R1/R2 = 4.17) */ 460 reg_3p0v: ldo4 { 461 regulator-name = "vdd3p0"; 462 regulator-min-microvolt = <3023250>; 463 regulator-max-microvolt = <3023250>; 464 lltc,fb-voltage-divider = <634000 200000>; 465 regulator-boot-on; 466 regulator-always-on; 467 }; 468 }; 469 }; 470 471 crypto@60 { 472 compatible = "atmel,atecc508a"; 473 reg = <0x60>; 474 }; 475 476 imu@6a { 477 compatible = "st,lsm9ds1-imu"; 478 reg = <0x6a>; 479 st,drdy-int-pin = <1>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_imu>; 482 interrupt-parent = <&gpio4>; 483 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 484 }; 485}; 486 487&i2c3 { 488 clock-frequency = <100000>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_i2c3>; 491 status = "okay"; 492 493 egalax_ts: touchscreen@4 { 494 compatible = "eeti,egalax_ts"; 495 reg = <0x04>; 496 interrupt-parent = <&gpio1>; 497 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 498 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 499 }; 500}; 501 502&ldb { 503 status = "okay"; 504 505 lvds-channel@0 { 506 fsl,data-mapping = "spwg"; 507 fsl,data-width = <18>; 508 status = "okay"; 509 510 display-timings { 511 native-mode = <&timing0>; 512 timing0: timing-hsd100pxn1 { 513 clock-frequency = <65000000>; 514 hactive = <1024>; 515 vactive = <768>; 516 hback-porch = <220>; 517 hfront-porch = <40>; 518 vback-porch = <21>; 519 vfront-porch = <7>; 520 hsync-len = <60>; 521 vsync-len = <10>; 522 }; 523 }; 524 }; 525}; 526 527&pcie { 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pinctrl_pcie>; 530 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 531 status = "okay"; 532}; 533 534&pwm2 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 537 status = "disabled"; 538}; 539 540&pwm3 { 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 543 status = "disabled"; 544}; 545 546&pwm4 { 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_pwm4>; 549 status = "okay"; 550}; 551 552&uart1 { 553 pinctrl-names = "default"; 554 pinctrl-0 = <&pinctrl_uart1>; 555 status = "okay"; 556}; 557 558&uart2 { 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pinctrl_uart2>; 561 status = "okay"; 562}; 563 564&uart3 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_uart3>; 567 uart-has-rtscts; 568 status = "okay"; 569}; 570 571&uart4 { 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_uart4>; 574 uart-has-rtscts; 575 status = "okay"; 576}; 577 578&uart5 { 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pinctrl_uart5>; 581 status = "okay"; 582}; 583 584&usbotg { 585 vbus-supply = <®_usb_otg_vbus>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_usbotg>; 588 disable-over-current; 589 status = "okay"; 590}; 591 592&usbh1 { 593 vbus-supply = <®_usb_h1_vbus>; 594 status = "okay"; 595}; 596 597&usdhc3 { 598 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 599 pinctrl-0 = <&pinctrl_usdhc3>; 600 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 601 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 602 non-removable; 603 vmmc-supply = <®_3p3v>; 604 keep-power-in-suspend; 605 status = "okay"; 606}; 607 608&wdog1 { 609 pinctrl-names = "default"; 610 pinctrl-0 = <&pinctrl_wdog>; 611 fsl,ext-reset-output; 612}; 613 614&iomuxc { 615 pinctrl_enet: enetgrp { 616 fsl,pins = < 617 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 618 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 619 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 620 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 621 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 622 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 623 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 624 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 625 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 626 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 627 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 628 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 629 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 630 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 631 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 632 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 633 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 634 >; 635 }; 636 637 pinctrl_gpio_leds: gpioledsgrp { 638 fsl,pins = < 639 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 640 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 641 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 642 >; 643 }; 644 645 pinctrl_i2c1: i2c1grp { 646 fsl,pins = < 647 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 648 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 649 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 650 >; 651 }; 652 653 pinctrl_i2c2: i2c2grp { 654 fsl,pins = < 655 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 656 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 657 >; 658 }; 659 660 pinctrl_i2c3: i2c3grp { 661 fsl,pins = < 662 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 663 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 664 >; 665 }; 666 667 pinctrl_imu: imugrp { 668 fsl,pins = < 669 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 670 >; 671 }; 672 673 pinctrl_mag: maggrp { 674 fsl,pins = < 675 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 676 >; 677 }; 678 679 pinctrl_pcie: pciegrp { 680 fsl,pins = < 681 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 682 >; 683 }; 684 685 pinctrl_pmic: pmicgrp { 686 fsl,pins = < 687 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 688 >; 689 }; 690 691 pinctrl_pps: ppsgrp { 692 fsl,pins = < 693 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 694 >; 695 }; 696 697 pinctrl_pwm2: pwm2grp { 698 fsl,pins = < 699 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 700 >; 701 }; 702 703 pinctrl_pwm3: pwm3grp { 704 fsl,pins = < 705 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 706 >; 707 }; 708 709 pinctrl_pwm4: pwm4grp { 710 fsl,pins = < 711 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 712 >; 713 }; 714 715 pinctrl_uart1: uart1grp { 716 fsl,pins = < 717 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 718 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 719 >; 720 }; 721 722 pinctrl_uart2: uart2grp { 723 fsl,pins = < 724 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 725 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 726 >; 727 }; 728 729 pinctrl_uart3: uart3grp { 730 fsl,pins = < 731 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 732 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 733 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 734 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 735 >; 736 }; 737 738 pinctrl_uart4: uart4grp { 739 fsl,pins = < 740 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 741 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 742 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 743 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 744 >; 745 }; 746 747 pinctrl_uart5: uart5grp { 748 fsl,pins = < 749 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 750 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 751 >; 752 }; 753 754 pinctrl_usbotg: usbotggrp { 755 fsl,pins = < 756 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 757 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 758 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 759 >; 760 }; 761 762 pinctrl_usdhc3: usdhc3grp { 763 fsl,pins = < 764 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 765 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 766 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 767 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 768 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 769 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 770 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 771 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 772 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 773 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 774 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 775 >; 776 }; 777 778 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 779 fsl,pins = < 780 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 781 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 782 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 783 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 784 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 785 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 786 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 787 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 788 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 789 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 790 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 791 >; 792 }; 793 794 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 795 fsl,pins = < 796 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 797 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 798 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 799 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 800 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 801 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 802 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 803 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 804 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 805 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 806 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 807 >; 808 }; 809 810 pinctrl_wdog: wdoggrp { 811 fsl,pins = < 812 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 813 >; 814 }; 815}; 816