1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2014 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/media/tda1997x.h> 8#include <dt-bindings/input/linux-event-codes.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/sound/fsl-imx-audmux.h> 11 12/ { 13 /* these are used by bootloader for disabling nodes */ 14 aliases { 15 led0 = &led0; 16 nand = &gpmi; 17 ssi0 = &ssi1; 18 usb0 = &usbh1; 19 usb1 = &usbotg; 20 }; 21 22 chosen { 23 bootargs = "console=ttymxc1,115200"; 24 }; 25 26 gpio-keys { 27 compatible = "gpio-keys"; 28 29 user-pb { 30 label = "user_pb"; 31 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 32 linux,code = <BTN_0>; 33 }; 34 35 user-pb1x { 36 label = "user_pb1x"; 37 linux,code = <BTN_1>; 38 interrupt-parent = <&gsc>; 39 interrupts = <0>; 40 }; 41 42 key-erased { 43 label = "key-erased"; 44 linux,code = <BTN_2>; 45 interrupt-parent = <&gsc>; 46 interrupts = <1>; 47 }; 48 49 eeprom-wp { 50 label = "eeprom_wp"; 51 linux,code = <BTN_3>; 52 interrupt-parent = <&gsc>; 53 interrupts = <2>; 54 }; 55 56 tamper { 57 label = "tamper"; 58 linux,code = <BTN_4>; 59 interrupt-parent = <&gsc>; 60 interrupts = <5>; 61 }; 62 63 switch-hold { 64 label = "switch_hold"; 65 linux,code = <BTN_5>; 66 interrupt-parent = <&gsc>; 67 interrupts = <7>; 68 }; 69 }; 70 71 leds { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led0: led-user1 { 77 label = "user1"; 78 gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 79 default-state = "on"; 80 linux,default-trigger = "heartbeat"; 81 }; 82 }; 83 84 memory@10000000 { 85 device_type = "memory"; 86 reg = <0x10000000 0x20000000>; 87 }; 88 89 reg_5p0v: regulator-5p0v { 90 compatible = "regulator-fixed"; 91 regulator-name = "5P0V"; 92 regulator-min-microvolt = <5000000>; 93 regulator-max-microvolt = <5000000>; 94 }; 95 96 reg_usb_h1_vbus: regulator-usb-h1-vbus { 97 compatible = "regulator-fixed"; 98 regulator-name = "usb_h1_vbus"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 }; 102 103 reg_usb_otg_vbus: regulator-usb-otg-vbus { 104 compatible = "regulator-fixed"; 105 regulator-name = "usb_otg_vbus"; 106 regulator-min-microvolt = <5000000>; 107 regulator-max-microvolt = <5000000>; 108 }; 109 110 sound-digital { 111 compatible = "simple-audio-card"; 112 simple-audio-card,name = "tda1997x-audio"; 113 simple-audio-card,format = "i2s"; 114 simple-audio-card,bitclock-master = <&sound_codec>; 115 simple-audio-card,frame-master = <&sound_codec>; 116 117 sound_cpu: simple-audio-card,cpu { 118 sound-dai = <&ssi1>; 119 }; 120 121 sound_codec: simple-audio-card,codec { 122 sound-dai = <&hdmi_receiver>; 123 }; 124 }; 125}; 126 127&audmux { 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ 130 status = "okay"; 131 132 mux-ssi1 { 133 fsl,audmux-port = <0>; 134 fsl,port-config = < 135 (IMX_AUDMUX_V2_PTCR_TFSDIR | 136 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ 137 IMX_AUDMUX_V2_PTCR_TCLKDIR | 138 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ 139 IMX_AUDMUX_V2_PTCR_SYN) 140 IMX_AUDMUX_V2_PDCR_RXDSEL(4) 141 >; 142 }; 143 144 mux-aud5 { 145 fsl,audmux-port = <4>; 146 fsl,port-config = < 147 IMX_AUDMUX_V2_PTCR_SYN 148 IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; 149 }; 150}; 151 152&can1 { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_flexcan1>; 155 status = "okay"; 156}; 157 158&gpmi { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_gpmi_nand>; 161 status = "okay"; 162}; 163 164&hdmi { 165 ddc-i2c-bus = <&i2c3>; 166 status = "okay"; 167}; 168 169&i2c1 { 170 clock-frequency = <100000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_i2c1>; 173 status = "okay"; 174 175 gsc: gsc@20 { 176 compatible = "gw,gsc"; 177 reg = <0x20>; 178 interrupt-parent = <&gpio1>; 179 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 180 interrupt-controller; 181 #interrupt-cells = <1>; 182 #size-cells = <0>; 183 184 adc { 185 compatible = "gw,gsc-adc"; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 189 channel@0 { 190 gw,mode = <0>; 191 reg = <0x00>; 192 label = "temp"; 193 }; 194 195 channel@2 { 196 gw,mode = <1>; 197 reg = <0x02>; 198 label = "vdd_vin"; 199 }; 200 201 channel@5 { 202 gw,mode = <1>; 203 reg = <0x05>; 204 label = "vdd_3p3"; 205 }; 206 207 channel@8 { 208 gw,mode = <1>; 209 reg = <0x08>; 210 label = "vdd_bat"; 211 }; 212 213 channel@b { 214 gw,mode = <1>; 215 reg = <0x0b>; 216 label = "vdd_5p0"; 217 }; 218 219 channel@e { 220 gw,mode = <1>; 221 reg = <0xe>; 222 label = "vdd_arm"; 223 }; 224 225 channel@11 { 226 gw,mode = <1>; 227 reg = <0x11>; 228 label = "vdd_soc"; 229 }; 230 231 channel@14 { 232 gw,mode = <1>; 233 reg = <0x14>; 234 label = "vdd_3p0"; 235 }; 236 237 channel@17 { 238 gw,mode = <1>; 239 reg = <0x17>; 240 label = "vdd_1p5"; 241 }; 242 243 channel@1d { 244 gw,mode = <1>; 245 reg = <0x1d>; 246 label = "vdd_1p8a"; 247 }; 248 249 channel@20 { 250 gw,mode = <1>; 251 reg = <0x20>; 252 label = "vdd_1p0b"; 253 }; 254 }; 255 }; 256 257 gsc_gpio: gpio@23 { 258 compatible = "nxp,pca9555"; 259 reg = <0x23>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 interrupt-parent = <&gsc>; 263 interrupts = <4>; 264 }; 265 266 eeprom1: eeprom@50 { 267 compatible = "atmel,24c02"; 268 reg = <0x50>; 269 pagesize = <16>; 270 }; 271 272 eeprom2: eeprom@51 { 273 compatible = "atmel,24c02"; 274 reg = <0x51>; 275 pagesize = <16>; 276 }; 277 278 eeprom3: eeprom@52 { 279 compatible = "atmel,24c02"; 280 reg = <0x52>; 281 pagesize = <16>; 282 }; 283 284 eeprom4: eeprom@53 { 285 compatible = "atmel,24c02"; 286 reg = <0x53>; 287 pagesize = <16>; 288 }; 289 290 rtc: ds1672@68 { 291 compatible = "dallas,ds1672"; 292 reg = <0x68>; 293 }; 294}; 295 296&i2c2 { 297 clock-frequency = <100000>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_i2c2>; 300 status = "okay"; 301 302 ltc3676: pmic@3c { 303 compatible = "lltc,ltc3676"; 304 reg = <0x3c>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_pmic>; 307 interrupt-parent = <&gpio1>; 308 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 309 310 regulators { 311 /* VDD_SOC (1+R1/R2 = 1.635) */ 312 reg_vdd_soc: sw1 { 313 regulator-name = "vddsoc"; 314 regulator-min-microvolt = <674400>; 315 regulator-max-microvolt = <1308000>; 316 lltc,fb-voltage-divider = <127000 200000>; 317 regulator-ramp-delay = <7000>; 318 regulator-boot-on; 319 regulator-always-on; 320 }; 321 322 /* VDD_DDR (1+R1/R2 = 2.105) */ 323 reg_vdd_ddr: sw2 { 324 regulator-name = "vddddr"; 325 regulator-min-microvolt = <868310>; 326 regulator-max-microvolt = <1684000>; 327 lltc,fb-voltage-divider = <221000 200000>; 328 regulator-ramp-delay = <7000>; 329 regulator-boot-on; 330 regulator-always-on; 331 }; 332 333 /* VDD_ARM (1+R1/R2 = 1.635) */ 334 reg_vdd_arm: sw3 { 335 regulator-name = "vddarm"; 336 regulator-min-microvolt = <674400>; 337 regulator-max-microvolt = <1308000>; 338 lltc,fb-voltage-divider = <127000 200000>; 339 regulator-ramp-delay = <7000>; 340 regulator-boot-on; 341 regulator-always-on; 342 }; 343 344 /* VDD_3P3 (1+R1/R2 = 1.281) */ 345 reg_3p3: sw4 { 346 regulator-name = "vdd3p3"; 347 regulator-min-microvolt = <1880000>; 348 regulator-max-microvolt = <3647000>; 349 lltc,fb-voltage-divider = <200000 56200>; 350 regulator-ramp-delay = <7000>; 351 regulator-boot-on; 352 regulator-always-on; 353 }; 354 355 /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ 356 reg_1p8a: ldo2 { 357 regulator-name = "vdd1p8a"; 358 regulator-min-microvolt = <1816125>; 359 regulator-max-microvolt = <1816125>; 360 lltc,fb-voltage-divider = <301000 200000>; 361 regulator-boot-on; 362 regulator-always-on; 363 }; 364 365 /* VDD_1P8b: HDMI In analog */ 366 reg_1p8b: ldo3 { 367 regulator-name = "vdd1p8b"; 368 regulator-min-microvolt = <1800000>; 369 regulator-max-microvolt = <1800000>; 370 regulator-boot-on; 371 }; 372 373 /* VDD_HIGH (1+R1/R2 = 4.17) */ 374 reg_3p0: ldo4 { 375 regulator-name = "vdd3p0"; 376 regulator-min-microvolt = <3023250>; 377 regulator-max-microvolt = <3023250>; 378 lltc,fb-voltage-divider = <634000 200000>; 379 regulator-boot-on; 380 regulator-always-on; 381 }; 382 }; 383 }; 384}; 385 386&i2c3 { 387 clock-frequency = <100000>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_i2c3>; 390 status = "okay"; 391 392 gpio_exp: pca9555@24 { 393 compatible = "nxp,pca9555"; 394 reg = <0x24>; 395 gpio-controller; 396 #gpio-cells = <2>; 397 }; 398 399 hdmi_receiver: hdmi-receiver@48 { 400 compatible = "nxp,tda19971"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_tda1997x>; 403 reg = <0x48>; 404 interrupt-parent = <&gpio1>; 405 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 406 DOVDD-supply = <®_3p3>; 407 AVDD-supply = <®_1p8b>; 408 DVDD-supply = <®_1p8a>; 409 #sound-dai-cells = <0>; 410 nxp,audout-format = "i2s"; 411 nxp,audout-layout = <0>; 412 nxp,audout-width = <16>; 413 nxp,audout-mclk-fs = <128>; 414 /* 415 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] 416 * and Y[11:4] across 16bits in the same cycle 417 * which we map to VP[15:08]<->CSI_DATA[19:12] 418 */ 419 nxp,vidout-portcfg = 420 /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ 421 < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, 422 /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ 423 < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, 424 /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ 425 < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, 426 /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ 427 < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; 428 429 port { 430 tda1997x_to_ipu1_csi0_mux: endpoint { 431 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 432 bus-width = <16>; 433 hsync-active = <1>; 434 vsync-active = <1>; 435 data-active = <1>; 436 }; 437 }; 438 }; 439}; 440 441&ipu1_csi0_from_ipu1_csi0_mux { 442 bus-width = <16>; 443}; 444 445&ipu1_csi0_mux_from_parallel_sensor { 446 remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; 447 bus-width = <16>; 448}; 449 450&ipu1_csi0 { 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_ipu1_csi0>; 453}; 454 455&pcie { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_pcie>; 458 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 459 status = "okay"; 460}; 461 462&pwm2 { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 465 status = "disabled"; 466}; 467 468&pwm3 { 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 471 status = "disabled"; 472}; 473 474&ssi1 { 475 status = "okay"; 476}; 477 478&uart2 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_uart2>; 481 status = "okay"; 482}; 483 484&uart3 { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_uart3>; 487 status = "okay"; 488}; 489 490&usbotg { 491 vbus-supply = <®_usb_otg_vbus>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_usbotg>; 494 disable-over-current; 495 status = "okay"; 496}; 497 498&usbh1 { 499 vbus-supply = <®_usb_h1_vbus>; 500 status = "okay"; 501}; 502 503&wdog1 { 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_wdog>; 506 fsl,ext-reset-output; 507}; 508 509&iomuxc { 510 pinctrl_audmux: audmuxgrp { 511 fsl,pins = < 512 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 513 MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 514 MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 515 >; 516 }; 517 518 pinctrl_flexcan1: flexcan1grp { 519 fsl,pins = < 520 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 521 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 522 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 523 >; 524 }; 525 526 pinctrl_gpio_leds: gpioledsgrp { 527 fsl,pins = < 528 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 529 >; 530 }; 531 532 pinctrl_gpmi_nand: gpminandgrp { 533 fsl,pins = < 534 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 535 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 536 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 537 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 538 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 539 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 540 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 541 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 542 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 543 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 544 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 545 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 546 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 547 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 548 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 549 >; 550 }; 551 552 pinctrl_i2c1: i2c1grp { 553 fsl,pins = < 554 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 555 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 556 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 557 >; 558 }; 559 560 pinctrl_i2c2: i2c2grp { 561 fsl,pins = < 562 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 563 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 564 >; 565 }; 566 567 pinctrl_i2c3: i2c3grp { 568 fsl,pins = < 569 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 570 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 571 >; 572 }; 573 574 pinctrl_ipu1_csi0: ipu1_csi0grp { 575 fsl,pins = < 576 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 577 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 578 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 579 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 580 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 581 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 582 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 583 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 584 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 585 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 586 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 587 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 588 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 589 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 590 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 591 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 592 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 593 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 594 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 595 >; 596 }; 597 598 pinctrl_pcie: pciegrp { 599 fsl,pins = < 600 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 601 >; 602 }; 603 604 pinctrl_pmic: pmicgrp { 605 fsl,pins = < 606 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 607 >; 608 }; 609 610 pinctrl_pwm2: pwm2grp { 611 fsl,pins = < 612 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 613 >; 614 }; 615 616 pinctrl_pwm3: pwm3grp { 617 fsl,pins = < 618 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 619 >; 620 }; 621 622 pinctrl_tda1997x: tda1997xgrp { 623 fsl,pins = < 624 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 625 >; 626 }; 627 628 pinctrl_uart2: uart2grp { 629 fsl,pins = < 630 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 631 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 632 >; 633 }; 634 635 pinctrl_uart3: uart3grp { 636 fsl,pins = < 637 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 638 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 639 >; 640 }; 641 642 pinctrl_usbotg: usbotggrp { 643 fsl,pins = < 644 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 645 >; 646 }; 647 648 pinctrl_wdog: wdoggrp { 649 fsl,pins = < 650 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 651 >; 652 }; 653}; 654