1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Colibri iMX6DL/S Module"; 13 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 14 15 aliases { 16 mmc0 = &usdhc3; /* eMMC */ 17 mmc1 = &usdhc1; /* MMC/SD Slot */ 18 /delete-property/ mmc2; 19 /delete-property/ mmc3; 20 }; 21 22 backlight: backlight { 23 compatible = "pwm-backlight"; 24 brightness-levels = <0 45 63 88 119 158 203 255>; 25 default-brightness-level = <4>; 26 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_gpio_bl_on>; 29 power-supply = <®_module_3v3>; 30 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 extcon_usbc_det: usbc-det { 35 compatible = "linux,extcon-usb-gpio"; 36 id-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_usbc_det>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 49 label = "Wake-Up"; 50 linux,code = <KEY_WAKEUP>; 51 wakeup-source; 52 }; 53 }; 54 55 lcd_display: disp0 { 56 compatible = "fsl,imx-parallel-display"; 57 interface-pix-fmt = "bgr666"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 60 status = "disabled"; 61 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 port@0 { 66 reg = <0>; 67 68 lcd_display_in: endpoint { 69 remote-endpoint = <&ipu1_di0_disp0>; 70 }; 71 }; 72 73 port@1 { 74 reg = <1>; 75 76 lcd_display_out: endpoint { 77 remote-endpoint = <&lcd_panel_in>; 78 }; 79 }; 80 }; 81 82 /* Will be filled by the bootloader */ 83 memory@10000000 { 84 device_type = "memory"; 85 reg = <0x10000000 0>; 86 }; 87 88 panel_dpi: panel-dpi { 89 /* 90 * edt,et057090dhu: EDT 5.7" LCD TFT 91 * edt,et070080dh6: EDT 7.0" LCD TFT 92 */ 93 compatible = "edt,et057090dhu"; 94 backlight = <&backlight>; 95 status = "disabled"; 96 97 port { 98 lcd_panel_in: endpoint { 99 remote-endpoint = <&lcd_display_out>; 100 }; 101 }; 102 }; 103 104 reg_module_3v3: regulator-module-3v3 { 105 compatible = "regulator-fixed"; 106 regulator-name = "+V3.3"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 }; 111 112 reg_module_3v3_audio: regulator-module-3v3-audio { 113 compatible = "regulator-fixed"; 114 regulator-name = "+V3.3_AUDIO"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 regulator-always-on; 118 }; 119 120 reg_usb_host_vbus: regulator-usb-host-vbus { 121 compatible = "regulator-fixed"; 122 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 125 regulator-max-microvolt = <5000000>; 126 regulator-min-microvolt = <5000000>; 127 regulator-name = "usb_host_vbus"; 128 status = "disabled"; 129 }; 130 131 sound { 132 compatible = "fsl,imx-audio-sgtl5000"; 133 audio-codec = <&codec>; 134 audio-routing = 135 "Headphone Jack", "HP_OUT", 136 "LINE_IN", "Line In Jack", 137 "MIC_IN", "Mic Jack", 138 "Mic Jack", "Mic Bias"; 139 model = "imx6dl-colibri-sgtl5000"; 140 mux-int-port = <1>; 141 mux-ext-port = <5>; 142 ssi-controller = <&ssi1>; 143 }; 144 145 spdif_out: spdif-out { 146 compatible = "linux,spdif-dit"; 147 #sound-dai-cells = <0>; 148 }; 149 150 spdif_in: spdif-in { 151 compatible = "linux,spdif-dir"; 152 #sound-dai-cells = <0>; 153 }; 154 155 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 156 sound_spdif: sound-spdif { 157 compatible = "fsl,imx-audio-spdif"; 158 audio-cpu = <&spdif>; 159 audio-codec = <&spdif_out>, <&spdif_in>; 160 model = "imx-spdif"; 161 status = "disabled"; 162 }; 163}; 164 165&audmux { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 168 status = "okay"; 169}; 170 171/* Optional on SODIMM 55/63 */ 172&can1 { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_flexcan1>; 175 status = "disabled"; 176}; 177 178/* Optional on SODIMM 178/188 */ 179&can2 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_flexcan2>; 182 status = "disabled"; 183}; 184 185&clks { 186 fsl,pmic-stby-poweroff; 187}; 188 189/* Colibri SSP */ 190&ecspi4 { 191 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_ecspi4>; 194 status = "disabled"; 195}; 196 197&fec { 198 phy-mode = "rmii"; 199 phy-handle = <ðphy>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_enet>; 202 status = "okay"; 203 204 mdio { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 ethphy: ethernet-phy@0 { 209 reg = <0>; 210 micrel,led-mode = <0>; 211 }; 212 }; 213}; 214 215&gpio1 { 216 gpio-line-names = "", 217 "SODIMM_67", 218 "SODIMM_180", 219 "SODIMM_196", 220 "SODIMM_174", 221 "SODIMM_176", 222 "SODIMM_194", 223 "SODIMM_55", 224 "SODIMM_63", 225 "SODIMM_28", 226 "SODIMM_93", 227 "SODIMM_69", 228 "SODIMM_99", 229 "SODIMM_130", 230 "SODIMM_106", 231 "SODIMM_98", 232 "SODIMM_192", 233 "SODIMM_49", 234 "SODIMM_190", 235 "SODIMM_51", 236 "SODIMM_47", 237 "SODIMM_53", 238 "", 239 "SODIMM_22"; 240}; 241 242&gpio2 { 243 gpio-line-names = "SODIMM_132", 244 "SODIMM_134", 245 "SODIMM_135", 246 "SODIMM_133", 247 "SODIMM_102", 248 "SODIMM_43", 249 "SODIMM_127", 250 "SODIMM_37", 251 "SODIMM_104", 252 "SODIMM_59", 253 "SODIMM_30", 254 "SODIMM_100", 255 "SODIMM_38", 256 "SODIMM_34", 257 "SODIMM_32", 258 "SODIMM_36", 259 "SODIMM_59", 260 "SODIMM_67", 261 "SODIMM_97", 262 "SODIMM_79", 263 "SODIMM_103", 264 "SODIMM_101", 265 "SODIMM_45", 266 "SODIMM_105", 267 "SODIMM_107", 268 "SODIMM_91", 269 "SODIMM_89", 270 "SODIMM_150", 271 "SODIMM_126", 272 "SODIMM_128", 273 "", 274 "SODIMM_94"; 275}; 276 277&gpio3 { 278 gpio-line-names = "SODIMM_111", 279 "SODIMM_113", 280 "SODIMM_115", 281 "SODIMM_117", 282 "SODIMM_119", 283 "SODIMM_121", 284 "SODIMM_123", 285 "SODIMM_125", 286 "SODIMM_110", 287 "SODIMM_112", 288 "SODIMM_114", 289 "SODIMM_116", 290 "SODIMM_118", 291 "SODIMM_120", 292 "SODIMM_122", 293 "SODIMM_124", 294 "", 295 "SODIMM_96", 296 "SODIMM_77", 297 "SODIMM_25", 298 "SODIMM_27", 299 "SODIMM_88", 300 "SODIMM_90", 301 "SODIMM_31", 302 "SODIMM_23", 303 "SODIMM_29", 304 "SODIMM_71", 305 "SODIMM_73", 306 "SODIMM_92", 307 "SODIMM_81", 308 "SODIMM_131", 309 "SODIMM_129"; 310}; 311 312&gpio4 { 313 gpio-line-names = "", 314 "", 315 "", 316 "", 317 "", 318 "SODIMM_168", 319 "", 320 "", 321 "", 322 "", 323 "SODIMM_184", 324 "SODIMM_186", 325 "HDMI_15", 326 "HDMI_16", 327 "SODIMM_178", 328 "SODIMM_188", 329 "SODIMM_56", 330 "SODIMM_44", 331 "SODIMM_68", 332 "SODIMM_82", 333 "SODIMM_24", 334 "SODIMM_76", 335 "SODIMM_70", 336 "SODIMM_60", 337 "SODIMM_58", 338 "SODIMM_78", 339 "SODIMM_72", 340 "SODIMM_80", 341 "SODIMM_46", 342 "SODIMM_62", 343 "SODIMM_48", 344 "SODIMM_74"; 345}; 346 347&gpio5 { 348 gpio-line-names = "SODIMM_95", 349 "", 350 "SODIMM_86", 351 "", 352 "SODIMM_65", 353 "SODIMM_50", 354 "SODIMM_52", 355 "SODIMM_54", 356 "SODIMM_66", 357 "SODIMM_64", 358 "SODIMM_57", 359 "SODIMM_61", 360 "SODIMM_136", 361 "SODIMM_138", 362 "SODIMM_140", 363 "SODIMM_142", 364 "SODIMM_144", 365 "SODIMM_146", 366 "SODIMM_172", 367 "SODIMM_170", 368 "SODIMM_149", 369 "SODIMM_151", 370 "SODIMM_153", 371 "SODIMM_155", 372 "SODIMM_157", 373 "SODIMM_159", 374 "SODIMM_161", 375 "SODIMM_163", 376 "SODIMM_33", 377 "SODIMM_35", 378 "SODIMM_165", 379 "SODIMM_167"; 380}; 381 382&gpio6 { 383 gpio-line-names = "SODIMM_169", 384 "SODIMM_171", 385 "SODIMM_173", 386 "SODIMM_175", 387 "SODIMM_177", 388 "SODIMM_179", 389 "SODIMM_85", 390 "SODIMM_166", 391 "SODIMM_160", 392 "SODIMM_162", 393 "SODIMM_158", 394 "SODIMM_164", 395 "", 396 "", 397 "SODIMM_156", 398 "SODIMM_75", 399 "SODIMM_154", 400 "", 401 "", 402 "", 403 "", 404 "", 405 "", 406 "", 407 "", 408 "", 409 "", 410 "", 411 "", 412 "", 413 "", 414 "SODIMM_152"; 415}; 416 417&gpio7 { 418 gpio-line-names = "", 419 "", 420 "", 421 "", 422 "", 423 "", 424 "", 425 "", 426 "", 427 "SODIMM_19", 428 "SODIMM_21", 429 "", 430 "SODIMM_137"; 431}; 432 433&hdmi { 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_hdmi_ddc>; 436 status = "disabled"; 437}; 438 439/* 440 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 441 * touch screen controller 442 */ 443&i2c2 { 444 clock-frequency = <100000>; 445 pinctrl-names = "default", "gpio"; 446 pinctrl-0 = <&pinctrl_i2c2>; 447 pinctrl-1 = <&pinctrl_i2c2_gpio>; 448 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 449 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 450 status = "okay"; 451 452 pmic: pmic@8 { 453 compatible = "fsl,pfuze100"; 454 fsl,pmic-stby-poweroff; 455 reg = <0x08>; 456 457 regulators { 458 sw1a_reg: sw1ab { 459 regulator-always-on; 460 regulator-boot-on; 461 regulator-max-microvolt = <1875000>; 462 regulator-min-microvolt = <300000>; 463 regulator-ramp-delay = <6250>; 464 }; 465 466 sw1c_reg: sw1c { 467 regulator-always-on; 468 regulator-boot-on; 469 regulator-max-microvolt = <1875000>; 470 regulator-min-microvolt = <300000>; 471 regulator-ramp-delay = <6250>; 472 }; 473 474 sw3a_reg: sw3a { 475 regulator-always-on; 476 regulator-boot-on; 477 regulator-max-microvolt = <1975000>; 478 regulator-min-microvolt = <400000>; 479 }; 480 481 swbst_reg: swbst { 482 regulator-always-on; 483 regulator-boot-on; 484 regulator-max-microvolt = <5150000>; 485 regulator-min-microvolt = <5000000>; 486 }; 487 488 snvs_reg: vsnvs { 489 regulator-always-on; 490 regulator-boot-on; 491 regulator-max-microvolt = <3000000>; 492 regulator-min-microvolt = <1000000>; 493 }; 494 495 vref_reg: vrefddr { 496 regulator-always-on; 497 regulator-boot-on; 498 }; 499 500 /* vgen1: unused */ 501 502 vgen2_reg: vgen2 { 503 regulator-always-on; 504 regulator-boot-on; 505 regulator-max-microvolt = <1550000>; 506 regulator-min-microvolt = <800000>; 507 }; 508 509 /* 510 * +V3.3_1.8_SD1 coming off VGEN3 and supplying 511 * the i.MX 6 NVCC_SD1. 512 */ 513 vgen3_reg: vgen3 { 514 regulator-always-on; 515 regulator-boot-on; 516 regulator-max-microvolt = <3300000>; 517 regulator-min-microvolt = <1800000>; 518 }; 519 520 vgen4_reg: vgen4 { 521 regulator-always-on; 522 regulator-boot-on; 523 regulator-max-microvolt = <1800000>; 524 regulator-min-microvolt = <1800000>; 525 }; 526 527 vgen5_reg: vgen5 { 528 regulator-always-on; 529 regulator-boot-on; 530 regulator-max-microvolt = <3300000>; 531 regulator-min-microvolt = <1800000>; 532 }; 533 534 vgen6_reg: vgen6 { 535 regulator-always-on; 536 regulator-boot-on; 537 regulator-max-microvolt = <3300000>; 538 regulator-min-microvolt = <1800000>; 539 }; 540 }; 541 }; 542 543 codec: sgtl5000@a { 544 compatible = "fsl,sgtl5000"; 545 clocks = <&clks IMX6QDL_CLK_CKO>; 546 lrclk-strength = <3>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_sgtl5000>; 549 reg = <0x0a>; 550 #sound-dai-cells = <0>; 551 VDDA-supply = <®_module_3v3_audio>; 552 VDDIO-supply = <®_module_3v3>; 553 VDDD-supply = <&vgen4_reg>; 554 }; 555 556 /* STMPE811 touch screen controller */ 557 stmpe811@41 { 558 compatible = "st,stmpe811"; 559 blocks = <0x5>; 560 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 561 interrupt-parent = <&gpio6>; 562 id = <0>; 563 irq-trigger = <0x1>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&pinctrl_touch_int>; 566 reg = <0x41>; 567 /* 3.25 MHz ADC clock speed */ 568 st,adc-freq = <1>; 569 /* 12-bit ADC */ 570 st,mod-12b = <1>; 571 /* internal ADC reference */ 572 st,ref-sel = <0>; 573 /* ADC converstion time: 80 clocks */ 574 st,sample-time = <4>; 575 576 stmpe_ts: stmpe_touchscreen { 577 compatible = "st,stmpe-ts"; 578 /* 8 sample average control */ 579 st,ave-ctrl = <3>; 580 /* 7 length fractional part in z */ 581 st,fraction-z = <7>; 582 /* 583 * 50 mA typical 80 mA max touchscreen drivers 584 * current limit value 585 */ 586 st,i-drive = <1>; 587 /* 1 ms panel driver settling time */ 588 st,settling = <3>; 589 /* 5 ms touch detect interrupt delay */ 590 st,touch-det-delay = <5>; 591 status = "disabled"; 592 }; 593 594 stmpe_adc: stmpe_adc { 595 compatible = "st,stmpe-adc"; 596 /* forbid to use ADC channels 3-0 (touch) */ 597 st,norequest-mask = <0x0F>; 598 }; 599 }; 600}; 601 602/* 603 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 604 */ 605&i2c3 { 606 clock-frequency = <100000>; 607 pinctrl-names = "default", "gpio"; 608 pinctrl-0 = <&pinctrl_i2c3>; 609 pinctrl-1 = <&pinctrl_i2c3_gpio>; 610 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 611 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 612 status = "disabled"; 613 614 atmel_mxt_ts: touchscreen@4a { 615 compatible = "atmel,maxtouch"; 616 interrupt-parent = <&gpio2>; 617 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ 618 pinctrl-names = "default"; 619 pinctrl-0 = <&pinctrl_atmel_conn>; 620 reg = <0x4a>; 621 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ 622 status = "disabled"; 623 }; 624}; 625 626&ipu1_di0_disp0 { 627 remote-endpoint = <&lcd_display_in>; 628}; 629 630/* Colibri PWM<B> */ 631&pwm1 { 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_pwm1>; 634 status = "disabled"; 635}; 636 637/* Colibri PWM<D> */ 638&pwm2 { 639 pinctrl-names = "default"; 640 pinctrl-0 = <&pinctrl_pwm2>; 641 status = "disabled"; 642}; 643 644/* Colibri PWM<A> */ 645&pwm3 { 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_pwm3>; 648 status = "disabled"; 649}; 650 651/* Colibri PWM<C> */ 652&pwm4 { 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_pwm4>; 655 status = "disabled"; 656}; 657 658/* Optional S/PDIF out on SODIMM 137 */ 659&spdif { 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_spdif>; 662 status = "disabled"; 663}; 664 665&ssi1 { 666 status = "okay"; 667}; 668 669/* Colibri UART_A */ 670&uart1 { 671 fsl,dte-mode; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 674 uart-has-rtscts; 675 status = "disabled"; 676}; 677 678/* Colibri UART_B */ 679&uart2 { 680 fsl,dte-mode; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pinctrl_uart2_dte>; 683 uart-has-rtscts; 684 status = "disabled"; 685}; 686 687/* Colibri UART_C */ 688&uart3 { 689 fsl,dte-mode; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_uart3_dte>; 692 status = "disabled"; 693}; 694 695/* Colibri USBH */ 696&usbh1 { 697 vbus-supply = <®_usb_host_vbus>; 698}; 699 700/* Colibri USBC */ 701&usbotg { 702 dr_mode = "otg"; 703 extcon = <0>, <&extcon_usbc_det>; 704 status = "disabled"; 705}; 706 707/* Colibri MMC */ 708&usdhc1 { 709 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 710 bus-width = <4>; 711 no-1-8-v; 712 disable-wp; 713 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 714 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 715 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; 716 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; 717 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; 718 vmmc-supply = <®_module_3v3>; 719 vqmmc-supply = <&vgen3_reg>; 720 status = "disabled"; 721}; 722 723/* eMMC */ 724&usdhc3 { 725 bus-width = <8>; 726 no-1-8-v; 727 non-removable; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&pinctrl_usdhc3>; 730 vqmmc-supply = <®_module_3v3>; 731 status = "okay"; 732}; 733 734&weim { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 737 &pinctrl_weim_cs1 &pinctrl_weim_cs2 738 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 739 #address-cells = <2>; 740 #size-cells = <1>; 741 status = "disabled"; 742}; 743 744&iomuxc { 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_usbh_oc_1>; 747 748 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 749 /* NOTE: This pin group conflicts with pin groups 750 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. 751 */ 752 pinctrl_atmel_adap: atmeladaptergrp { 753 fsl,pins = < 754 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ 755 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ 756 >; 757 }; 758 759 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 760 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and 761 * pinctrl_weim_cs2. Don't use them simultaneously. 762 */ 763 pinctrl_atmel_conn: atmelconnectorgrp { 764 fsl,pins = < 765 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ 766 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ 767 >; 768 }; 769 770 pinctrl_audmux: audmuxgrp { 771 fsl,pins = < 772 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 773 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 774 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 775 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 776 >; 777 }; 778 779 pinctrl_cam_mclk: cammclkgrp { 780 fsl,pins = < 781 /* Parallel Camera CAM sys_mclk */ 782 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 783 >; 784 }; 785 786 /* CSI pins used as GPIOs */ 787 pinctrl_csi_gpio_1: csigpio1grp { 788 fsl,pins = < 789 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 790 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 791 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 792 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 793 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 794 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 795 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 796 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 797 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 798 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 799 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 800 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 801 >; 802 }; 803 804 pinctrl_csi_gpio_2: csigpio2grp { 805 fsl,pins = < 806 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 807 >; 808 }; 809 810 pinctrl_ecspi4: ecspi4grp { 811 fsl,pins = < 812 /* SPI CS */ 813 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 814 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 815 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 816 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 817 >; 818 }; 819 820 pinctrl_enet: enetgrp { 821 fsl,pins = < 822 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 823 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 824 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 825 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 826 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 827 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 828 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 829 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 830 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 831 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 832 >; 833 }; 834 835 pinctrl_flexcan1: flexcan1grp { 836 fsl,pins = < 837 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 838 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 839 >; 840 }; 841 842 pinctrl_flexcan2: flexcan2grp { 843 fsl,pins = < 844 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 845 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 846 >; 847 }; 848 849 pinctrl_gpio_1: gpio1grp { 850 fsl,pins = < 851 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 852 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 853 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 854 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 855 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 856 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 857 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 858 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 859 >; 860 }; 861 pinctrl_gpio_2: gpio2grp { 862 fsl,pins = < 863 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 864 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 865 >; 866 }; 867 868 pinctrl_gpio_bl_on: gpioblongrp { 869 fsl,pins = < 870 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 871 >; 872 }; 873 874 pinctrl_gpio_keys: gpiokeysgrp { 875 fsl,pins = < 876 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 877 >; 878 }; 879 880 pinctrl_hdmi_ddc: hdmiddcgrp { 881 fsl,pins = < 882 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 883 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 884 >; 885 }; 886 887 pinctrl_i2c2: i2c2grp { 888 fsl,pins = < 889 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 890 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 891 >; 892 }; 893 894 pinctrl_i2c2_gpio: i2c2gpiogrp { 895 fsl,pins = < 896 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 897 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 898 >; 899 }; 900 901 pinctrl_i2c3: i2c3grp { 902 fsl,pins = < 903 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 904 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 905 >; 906 }; 907 908 pinctrl_i2c3_gpio: i2c3gpiogrp { 909 fsl,pins = < 910 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 911 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 912 >; 913 }; 914 915 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 916 fsl,pins = < 917 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 918 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 919 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 920 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 921 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 922 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 923 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 924 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 925 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 926 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 927 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 928 /* Disable PWM pins on camera interface */ 929 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 930 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 931 >; 932 }; 933 934 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 935 fsl,pins = < 936 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 937 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 938 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 939 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 940 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 941 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 942 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 943 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 944 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 945 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 946 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 947 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 948 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 949 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 950 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 951 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 952 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 953 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 954 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 955 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 956 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 957 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 958 >; 959 }; 960 961 pinctrl_lvds_transceiver: lvdstxgrp { 962 fsl,pins = < 963 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ 964 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ 965 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ 966 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ 967 >; 968 }; 969 970 pinctrl_mic_gnd: micgndgrp { 971 fsl,pins = < 972 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 973 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 974 >; 975 }; 976 977 pinctrl_mmc_cd: mmccdgrp { 978 fsl,pins = < 979 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 980 >; 981 }; 982 983 pinctrl_mmc_cd_sleep: mmccdslpgrp { 984 fsl,pins = < 985 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 986 >; 987 }; 988 989 pinctrl_pwm1: pwm1grp { 990 fsl,pins = < 991 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 992 >; 993 }; 994 995 pinctrl_pwm2: pwm2grp { 996 fsl,pins = < 997 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 998 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 999 >; 1000 }; 1001 1002 pinctrl_pwm3: pwm3grp { 1003 fsl,pins = < 1004 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 1005 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1006 >; 1007 }; 1008 1009 pinctrl_pwm4: pwm4grp { 1010 fsl,pins = < 1011 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1012 >; 1013 }; 1014 1015 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 1016 fsl,pins = < 1017 /* SODIMM 129 / USBH_PEN */ 1018 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 1019 >; 1020 }; 1021 1022 pinctrl_sgtl5000: sgtl5000grp { 1023 fsl,pins = < 1024 /* SGTL5000 sys_mclk */ 1025 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 1026 >; 1027 }; 1028 1029 pinctrl_spdif: spdifgrp { 1030 fsl,pins = < 1031 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1032 >; 1033 }; 1034 1035 pinctrl_touch_int: gpiotouchintgrp { 1036 fsl,pins = < 1037 /* STMPE811 interrupt */ 1038 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 1039 >; 1040 }; 1041 1042 pinctrl_uart1_dce: uart1dcegrp { 1043 fsl,pins = < 1044 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1045 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1046 >; 1047 }; 1048 1049 /* DTE mode */ 1050 pinctrl_uart1_dte: uart1dtegrp { 1051 fsl,pins = < 1052 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1053 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1054 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1055 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1056 >; 1057 }; 1058 1059 /* Additional DTR, DSR, DCD */ 1060 pinctrl_uart1_ctrl: uart1ctrlgrp { 1061 fsl,pins = < 1062 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1063 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1064 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1065 >; 1066 }; 1067 1068 pinctrl_uart2_dte: uart2dtegrp { 1069 fsl,pins = < 1070 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1071 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1072 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1073 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1074 >; 1075 }; 1076 1077 pinctrl_uart3_dte: uart3dtegrp { 1078 fsl,pins = < 1079 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1080 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1081 >; 1082 }; 1083 1084 pinctrl_usbc_det: usbcdetgrp { 1085 fsl,pins = < 1086 /* SODIMM 137 / USBC_DET */ 1087 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 1088 /* USBC_DET_OVERWRITE */ 1089 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 1090 /* USBC_DET_EN */ 1091 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 1092 >; 1093 }; 1094 1095 pinctrl_usbc_id_1: usbcid1grp { 1096 fsl,pins = < 1097 /* USBC_ID */ 1098 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 1099 >; 1100 }; 1101 1102 pinctrl_usbh_oc_1: usbhoc1grp { 1103 fsl,pins = < 1104 /* USBH_OC */ 1105 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 1106 >; 1107 }; 1108 1109 pinctrl_usdhc1: usdhc1grp { 1110 fsl,pins = < 1111 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1112 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1113 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1114 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1115 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1116 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1117 >; 1118 }; 1119 1120 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1121 fsl,pins = < 1122 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 1123 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 1124 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 1125 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 1126 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 1127 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 1128 >; 1129 }; 1130 1131 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1132 fsl,pins = < 1133 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 1134 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 1135 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 1136 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 1137 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 1138 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 1139 >; 1140 }; 1141 1142 /* avoid backfeeding with removed card power */ 1143 pinctrl_usdhc1_sleep: usdhc1sleepgrp { 1144 fsl,pins = < 1145 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 1146 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 1147 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 1148 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 1149 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 1150 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 1151 >; 1152 }; 1153 1154 pinctrl_usdhc3: usdhc3grp { 1155 fsl,pins = < 1156 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1157 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1158 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1159 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1160 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1161 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1162 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1163 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1164 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1165 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1166 /* eMMC reset */ 1167 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1168 >; 1169 }; 1170 1171 pinctrl_weim_cs0: weimcs0grp { 1172 fsl,pins = < 1173 /* nEXT_CS0 */ 1174 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1175 >; 1176 }; 1177 1178 pinctrl_weim_cs1: weimcs1grp { 1179 fsl,pins = < 1180 /* nEXT_CS1 */ 1181 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 1182 >; 1183 }; 1184 1185 pinctrl_weim_cs2: weimcs2grp { 1186 fsl,pins = < 1187 /* nEXT_CS2 */ 1188 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 1189 >; 1190 }; 1191 1192 /* ADDRESS[16:18] [25] used as GPIO */ 1193 pinctrl_weim_gpio_1: weimgpio1grp { 1194 fsl,pins = < 1195 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1196 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1197 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1198 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1199 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1200 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1201 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1202 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1203 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1204 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1205 >; 1206 }; 1207 1208 /* ADDRESS[19:24] used as GPIO */ 1209 pinctrl_weim_gpio_2: weimgpio2grp { 1210 fsl,pins = < 1211 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1212 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1213 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1214 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1215 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1216 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1217 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1218 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1219 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1220 >; 1221 }; 1222 1223 /* DATA[16:31] used as GPIO */ 1224 pinctrl_weim_gpio_3: weimgpio3grp { 1225 fsl,pins = < 1226 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 1227 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 1228 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 1229 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 1230 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 1231 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1232 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 1233 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 1234 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 1235 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 1236 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 1237 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 1238 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 1239 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 1240 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 1241 >; 1242 }; 1243 1244 /* DQM[0:3] used as GPIO */ 1245 pinctrl_weim_gpio_4: weimgpio4grp { 1246 fsl,pins = < 1247 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 1248 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 1249 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 1250 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 1251 >; 1252 }; 1253 1254 /* RDY used as GPIO */ 1255 pinctrl_weim_gpio_5: weimgpio5grp { 1256 fsl,pins = < 1257 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 1258 >; 1259 }; 1260 1261 /* ADDRESS[16] DATA[30] used as GPIO */ 1262 pinctrl_weim_gpio_6: weimgpio6grp { 1263 fsl,pins = < 1264 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 1265 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1266 >; 1267 }; 1268 1269 pinctrl_weim_npwe: weimnpwegrp { 1270 fsl,pins = < 1271 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 1272 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 1273 >; 1274 }; 1275 1276 pinctrl_weim_sram: weimsramgrp { 1277 fsl,pins = < 1278 /* Data */ 1279 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 1280 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 1281 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 1282 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 1283 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 1284 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 1285 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 1286 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 1287 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 1288 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 1289 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 1290 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 1291 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 1292 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 1293 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 1294 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 1295 /* Address */ 1296 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1297 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1298 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1299 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1300 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1301 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1302 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1303 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1304 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1305 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1306 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1307 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1308 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1309 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1310 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1311 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1312 /* Ctrl */ 1313 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1314 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1315 >; 1316 }; 1317 1318 pinctrl_weim_rdnwr: weimrdnwrgrp { 1319 fsl,pins = < 1320 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 1321 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 1322 >; 1323 }; 1324}; 1325