1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _hdp_6_0_0_SH_MASK_HEADER 24 #define _hdp_6_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: hdp_hdpdec 28 //HDP_NONSURFACE_BASE 29 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 30 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 31 //HDP_NONSURFACE_INFO 32 #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 33 #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 34 #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 35 #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 36 //HDP_NONSURFACE_BASE_HI 37 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 38 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 39 //HDP_SURFACE_WRITE_FLAGS 40 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 41 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 42 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 43 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 44 //HDP_SURFACE_READ_FLAGS 45 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 46 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 47 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 48 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 49 //HDP_SURFACE_WRITE_FLAGS_CLR 50 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 51 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 52 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 53 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 54 //HDP_SURFACE_READ_FLAGS_CLR 55 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 56 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 57 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 58 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 59 //HDP_NONSURF_FLAGS 60 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 61 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 62 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 63 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 64 //HDP_NONSURF_FLAGS_CLR 65 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 66 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 67 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 68 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 69 //HDP_HOST_PATH_CNTL 70 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 71 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 72 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 73 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 74 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 75 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 76 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 77 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 78 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 79 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 80 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 81 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 82 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 83 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 84 //HDP_SW_SEMAPHORE 85 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 86 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 87 //HDP_DEBUG0 88 #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 89 #define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL 90 //HDP_LAST_SURFACE_HIT 91 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 92 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 93 //HDP_OUTSTANDING_REQ 94 #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 95 #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 96 #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 97 #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 98 //HDP_MISC_CNTL 99 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 100 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 101 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 102 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 103 #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe 104 #define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13 105 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14 106 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 107 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 108 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 109 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 110 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 111 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 112 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 113 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 114 #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L 115 #define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L 116 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L 117 #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 118 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 119 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 120 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 121 //HDP_MEM_POWER_CTRL 122 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0 123 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1 124 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2 125 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3 126 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4 127 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 128 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 129 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 130 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 131 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 132 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 133 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 134 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 135 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e 136 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L 137 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L 138 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L 139 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L 140 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 141 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 142 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 143 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 144 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 145 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 146 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 147 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 148 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 149 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L 150 //HDP_MMHUB_CNTL 151 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 152 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 153 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 154 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 155 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 156 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 157 //HDP_VERSION 158 #define HDP_VERSION__MINVER__SHIFT 0x0 159 #define HDP_VERSION__MAJVER__SHIFT 0x8 160 #define HDP_VERSION__REV__SHIFT 0x10 161 #define HDP_VERSION__MINVER_MASK 0x000000FFL 162 #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 163 #define HDP_VERSION__REV_MASK 0x00FF0000L 164 //HDP_CLK_CNTL 165 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 166 #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 167 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 168 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 169 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 170 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 171 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 172 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 173 #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 174 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 175 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 176 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 177 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 178 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 179 //HDP_MEMIO_CNTL 180 #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 181 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 182 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 183 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 184 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 185 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 186 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 187 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 188 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 189 #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 190 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 191 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 192 #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 193 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 194 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 195 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 196 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 197 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 198 #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 199 #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 200 //HDP_MEMIO_ADDR 201 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 202 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 203 //HDP_MEMIO_STATUS 204 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 205 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 206 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 207 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 208 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 209 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 210 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 211 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 212 //HDP_MEMIO_WR_DATA 213 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 214 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 215 //HDP_MEMIO_RD_DATA 216 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 217 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 218 //HDP_XDP_DIRECT2HDP_FIRST 219 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 220 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 221 //HDP_XDP_D2H_FLUSH 222 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 223 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 224 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 225 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 226 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 227 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 228 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 229 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 230 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 231 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 232 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 233 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 234 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 235 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 236 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 237 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 238 //HDP_XDP_D2H_BAR_UPDATE 239 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 240 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 241 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 242 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 243 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 244 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 245 //HDP_XDP_D2H_RSVD_3 246 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 247 #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 248 //HDP_XDP_D2H_RSVD_4 249 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 250 #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 251 //HDP_XDP_D2H_RSVD_5 252 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 253 #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 254 //HDP_XDP_D2H_RSVD_6 255 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 256 #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 257 //HDP_XDP_D2H_RSVD_7 258 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 259 #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 260 //HDP_XDP_D2H_RSVD_8 261 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 262 #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 263 //HDP_XDP_D2H_RSVD_9 264 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 265 #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 266 //HDP_XDP_D2H_RSVD_10 267 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 268 #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 269 //HDP_XDP_D2H_RSVD_11 270 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 271 #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 272 //HDP_XDP_D2H_RSVD_12 273 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 274 #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 275 //HDP_XDP_D2H_RSVD_13 276 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 277 #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 278 //HDP_XDP_D2H_RSVD_14 279 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 280 #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 281 //HDP_XDP_D2H_RSVD_15 282 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 283 #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 284 //HDP_XDP_D2H_RSVD_16 285 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 286 #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 287 //HDP_XDP_D2H_RSVD_17 288 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 289 #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 290 //HDP_XDP_D2H_RSVD_18 291 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 292 #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 293 //HDP_XDP_D2H_RSVD_19 294 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 295 #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 296 //HDP_XDP_D2H_RSVD_20 297 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 298 #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 299 //HDP_XDP_D2H_RSVD_21 300 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 301 #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 302 //HDP_XDP_D2H_RSVD_22 303 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 304 #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 305 //HDP_XDP_D2H_RSVD_23 306 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 307 #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 308 //HDP_XDP_D2H_RSVD_24 309 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 310 #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 311 //HDP_XDP_D2H_RSVD_25 312 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 313 #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 314 //HDP_XDP_D2H_RSVD_26 315 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 316 #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 317 //HDP_XDP_D2H_RSVD_27 318 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 319 #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 320 //HDP_XDP_D2H_RSVD_28 321 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 322 #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 323 //HDP_XDP_D2H_RSVD_29 324 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 325 #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 326 //HDP_XDP_D2H_RSVD_30 327 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 328 #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 329 //HDP_XDP_D2H_RSVD_31 330 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 331 #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 332 //HDP_XDP_D2H_RSVD_32 333 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 334 #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 335 //HDP_XDP_D2H_RSVD_33 336 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 337 #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 338 //HDP_XDP_D2H_RSVD_34 339 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 340 #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 341 //HDP_XDP_DIRECT2HDP_LAST 342 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 343 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 344 //HDP_XDP_P2P_BAR_CFG 345 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 346 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 347 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 348 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 349 //HDP_XDP_P2P_MBX_OFFSET 350 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 351 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 352 //HDP_XDP_P2P_MBX_ADDR0 353 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 354 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 355 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 356 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 357 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 358 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 359 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 360 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 361 //HDP_XDP_P2P_MBX_ADDR1 362 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 363 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 364 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 365 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 366 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 367 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 368 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 369 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 370 //HDP_XDP_P2P_MBX_ADDR2 371 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 372 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 373 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 374 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 375 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 376 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 377 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 378 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 379 //HDP_XDP_P2P_MBX_ADDR3 380 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 381 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 382 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 383 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 384 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 385 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 386 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 387 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 388 //HDP_XDP_P2P_MBX_ADDR4 389 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 390 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 391 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 392 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 393 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 394 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 395 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 396 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 397 //HDP_XDP_P2P_MBX_ADDR5 398 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 399 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 400 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 401 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 402 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 403 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 404 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 405 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 406 //HDP_XDP_P2P_MBX_ADDR6 407 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 408 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 409 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 410 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 411 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 412 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 413 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 414 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 415 //HDP_XDP_HDP_MBX_MC_CFG 416 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 417 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 418 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 419 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 420 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 421 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 422 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 423 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 424 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 425 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 426 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 427 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 428 //HDP_XDP_HDP_MC_CFG 429 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 430 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 431 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 432 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 433 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 434 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 435 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 436 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 437 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 438 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 439 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 440 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 441 //HDP_XDP_HST_CFG 442 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 443 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 444 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 445 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 446 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 447 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 448 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 449 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 450 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 451 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 452 //HDP_XDP_HDP_IPH_CFG 453 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 454 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 455 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 456 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 457 //HDP_XDP_P2P_BAR0 458 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 459 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 460 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 461 #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 462 #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 463 #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 464 //HDP_XDP_P2P_BAR1 465 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 466 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 467 #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 468 #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 469 #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 470 #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 471 //HDP_XDP_P2P_BAR2 472 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 473 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 474 #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 475 #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 476 #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 477 #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 478 //HDP_XDP_P2P_BAR3 479 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 480 #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 481 #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 482 #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 483 #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 484 #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 485 //HDP_XDP_P2P_BAR4 486 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 487 #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 488 #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 489 #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 490 #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 491 #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 492 //HDP_XDP_P2P_BAR5 493 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 494 #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 495 #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 496 #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 497 #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 498 #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 499 //HDP_XDP_P2P_BAR6 500 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 501 #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 502 #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 503 #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 504 #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 505 #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 506 //HDP_XDP_P2P_BAR7 507 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 508 #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 509 #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 510 #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 511 #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 512 #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 513 //HDP_XDP_FLUSH_ARMED_STS 514 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 515 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 516 //HDP_XDP_FLUSH_CNTR0_STS 517 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 518 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 519 //HDP_XDP_BUSY_STS 520 #define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0 521 #define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1 522 #define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2 523 #define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3 524 #define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4 525 #define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5 526 #define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6 527 #define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7 528 #define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8 529 #define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9 530 #define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa 531 #define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb 532 #define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc 533 #define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd 534 #define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe 535 #define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf 536 #define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10 537 #define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11 538 #define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12 539 #define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13 540 #define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14 541 #define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15 542 #define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16 543 #define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17 544 #define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18 545 #define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L 546 #define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L 547 #define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L 548 #define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L 549 #define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L 550 #define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L 551 #define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L 552 #define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L 553 #define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L 554 #define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L 555 #define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L 556 #define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L 557 #define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L 558 #define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L 559 #define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L 560 #define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L 561 #define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L 562 #define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L 563 #define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L 564 #define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L 565 #define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L 566 #define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L 567 #define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L 568 #define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L 569 #define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L 570 //HDP_XDP_STICKY 571 #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 572 #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 573 #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 574 #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 575 //HDP_XDP_CHKN 576 #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 577 #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 578 #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 579 #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 580 #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 581 #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 582 #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 583 #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 584 //HDP_XDP_BARS_ADDR_39_36 585 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 586 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 587 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 588 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 589 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 590 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 591 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 592 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 593 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 594 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 595 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 596 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 597 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 598 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 599 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 600 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 601 //HDP_XDP_MC_VM_FB_LOCATION_BASE 602 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 603 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 604 //HDP_XDP_MMHUB_ERROR 605 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 606 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 607 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 608 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT 0x4 609 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 610 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 611 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 612 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 613 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 614 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 615 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT 0xc 616 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 617 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 618 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 619 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 620 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 621 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 622 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 623 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 624 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 625 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 626 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 627 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 628 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK 0x00000010L 629 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 630 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 631 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 632 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 633 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 634 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 635 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK 0x00001000L 636 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 637 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 638 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 639 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 640 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 641 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 642 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 643 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 644 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 645 646 #endif 647