1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 11#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 12#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 clock-frequency = <76800000>; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 47 bi_tcxo_div2: bi-tcxo-div2-clk { 48 compatible = "fixed-factor-clock"; 49 #clock-cells = <0>; 50 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 compatible = "fixed-factor-clock"; 58 #clock-cells = <0>; 59 60 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 61 clock-mult = <1>; 62 clock-div = <2>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 77 power-domain-names = "psci", "perf"; 78 79 l2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 cache-unified; 83 }; 84 }; 85 86 cpu1: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,oryon"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 next-level-cache = <&l2_0>; 92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 93 power-domain-names = "psci", "perf"; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 103 power-domain-names = "psci", "perf"; 104 }; 105 106 cpu3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,oryon"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 next-level-cache = <&l2_0>; 112 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 113 power-domain-names = "psci", "perf"; 114 }; 115 116 cpu4: cpu@10000 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon"; 119 reg = <0x0 0x10000>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_1>; 122 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 123 power-domain-names = "psci", "perf"; 124 125 l2_1: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 }; 130 }; 131 132 cpu5: cpu@10100 { 133 device_type = "cpu"; 134 compatible = "qcom,oryon"; 135 reg = <0x0 0x10100>; 136 enable-method = "psci"; 137 next-level-cache = <&l2_1>; 138 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 139 power-domain-names = "psci", "perf"; 140 }; 141 142 cpu6: cpu@10200 { 143 device_type = "cpu"; 144 compatible = "qcom,oryon"; 145 reg = <0x0 0x10200>; 146 enable-method = "psci"; 147 next-level-cache = <&l2_1>; 148 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 149 power-domain-names = "psci", "perf"; 150 }; 151 152 cpu7: cpu@10300 { 153 device_type = "cpu"; 154 compatible = "qcom,oryon"; 155 reg = <0x0 0x10300>; 156 enable-method = "psci"; 157 next-level-cache = <&l2_1>; 158 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 159 power-domain-names = "psci", "perf"; 160 }; 161 162 cpu8: cpu@20000 { 163 device_type = "cpu"; 164 compatible = "qcom,oryon"; 165 reg = <0x0 0x20000>; 166 enable-method = "psci"; 167 next-level-cache = <&l2_2>; 168 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 169 power-domain-names = "psci", "perf"; 170 171 l2_2: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 }; 176 }; 177 178 cpu9: cpu@20100 { 179 device_type = "cpu"; 180 compatible = "qcom,oryon"; 181 reg = <0x0 0x20100>; 182 enable-method = "psci"; 183 next-level-cache = <&l2_2>; 184 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 185 power-domain-names = "psci", "perf"; 186 }; 187 188 cpu10: cpu@20200 { 189 device_type = "cpu"; 190 compatible = "qcom,oryon"; 191 reg = <0x0 0x20200>; 192 enable-method = "psci"; 193 next-level-cache = <&l2_2>; 194 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 195 power-domain-names = "psci", "perf"; 196 }; 197 198 cpu11: cpu@20300 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon"; 201 reg = <0x0 0x20300>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_2>; 204 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 205 power-domain-names = "psci", "perf"; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&cpu0>; 212 }; 213 214 core1 { 215 cpu = <&cpu1>; 216 }; 217 218 core2 { 219 cpu = <&cpu2>; 220 }; 221 222 core3 { 223 cpu = <&cpu3>; 224 }; 225 }; 226 227 cluster1 { 228 core0 { 229 cpu = <&cpu4>; 230 }; 231 232 core1 { 233 cpu = <&cpu5>; 234 }; 235 236 core2 { 237 cpu = <&cpu6>; 238 }; 239 240 core3 { 241 cpu = <&cpu7>; 242 }; 243 }; 244 245 cpu_map_cluster2: cluster2 { 246 core0 { 247 cpu = <&cpu8>; 248 }; 249 250 core1 { 251 cpu = <&cpu9>; 252 }; 253 254 core2 { 255 cpu = <&cpu10>; 256 }; 257 258 core3 { 259 cpu = <&cpu11>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 cluster_c4: cpu-sleep-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "ret"; 270 arm,psci-suspend-param = <0x00000004>; 271 entry-latency-us = <180>; 272 exit-latency-us = <500>; 273 min-residency-us = <600>; 274 }; 275 }; 276 277 domain-idle-states { 278 cluster_cl4: cluster-sleep-0 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x01000044>; 281 entry-latency-us = <350>; 282 exit-latency-us = <500>; 283 min-residency-us = <2500>; 284 }; 285 286 cluster_cl5: cluster-sleep-1 { 287 compatible = "domain-idle-state"; 288 arm,psci-suspend-param = <0x01000054>; 289 entry-latency-us = <2200>; 290 exit-latency-us = <4000>; 291 min-residency-us = <7000>; 292 }; 293 }; 294 }; 295 296 dummy-sink { 297 compatible = "arm,coresight-dummy-sink"; 298 299 in-ports { 300 port { 301 eud_in: endpoint { 302 remote-endpoint = <&swao_rep_out1>; 303 }; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm: scm { 310 compatible = "qcom,scm-x1e80100", "qcom,scm"; 311 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 313 qcom,dload-mode = <&tcsr 0x19000>; 314 }; 315 316 scmi { 317 compatible = "arm,scmi"; 318 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 319 mbox-names = "tx", "rx"; 320 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 321 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 scmi_dvfs: protocol@13 { 326 reg = <0x13>; 327 #power-domain-cells = <1>; 328 }; 329 }; 330 }; 331 332 clk_virt: interconnect-0 { 333 compatible = "qcom,x1e80100-clk-virt"; 334 #interconnect-cells = <2>; 335 qcom,bcm-voters = <&apps_bcm_voter>; 336 }; 337 338 mc_virt: interconnect-1 { 339 compatible = "qcom,x1e80100-mc-virt"; 340 #interconnect-cells = <2>; 341 qcom,bcm-voters = <&apps_bcm_voter>; 342 }; 343 344 memory@80000000 { 345 device_type = "memory"; 346 /* We expect the bootloader to fill in the size */ 347 reg = <0 0x80000000 0 0>; 348 }; 349 350 pmu { 351 compatible = "arm,armv8-pmuv3"; 352 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 353 }; 354 355 psci { 356 compatible = "arm,psci-1.0"; 357 method = "smc"; 358 359 cpu_pd0: power-domain-cpu0 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd0>; 362 domain-idle-states = <&cluster_c4>; 363 }; 364 365 cpu_pd1: power-domain-cpu1 { 366 #power-domain-cells = <0>; 367 power-domains = <&cluster_pd0>; 368 domain-idle-states = <&cluster_c4>; 369 }; 370 371 cpu_pd2: power-domain-cpu2 { 372 #power-domain-cells = <0>; 373 power-domains = <&cluster_pd0>; 374 domain-idle-states = <&cluster_c4>; 375 }; 376 377 cpu_pd3: power-domain-cpu3 { 378 #power-domain-cells = <0>; 379 power-domains = <&cluster_pd0>; 380 domain-idle-states = <&cluster_c4>; 381 }; 382 383 cpu_pd4: power-domain-cpu4 { 384 #power-domain-cells = <0>; 385 power-domains = <&cluster_pd1>; 386 domain-idle-states = <&cluster_c4>; 387 }; 388 389 cpu_pd5: power-domain-cpu5 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd1>; 392 domain-idle-states = <&cluster_c4>; 393 }; 394 395 cpu_pd6: power-domain-cpu6 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster_pd1>; 398 domain-idle-states = <&cluster_c4>; 399 }; 400 401 cpu_pd7: power-domain-cpu7 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster_pd1>; 404 domain-idle-states = <&cluster_c4>; 405 }; 406 407 cpu_pd8: power-domain-cpu8 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster_pd2>; 410 domain-idle-states = <&cluster_c4>; 411 }; 412 413 cpu_pd9: power-domain-cpu9 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster_pd2>; 416 domain-idle-states = <&cluster_c4>; 417 }; 418 419 cpu_pd10: power-domain-cpu10 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster_pd2>; 422 domain-idle-states = <&cluster_c4>; 423 }; 424 425 cpu_pd11: power-domain-cpu11 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster_pd2>; 428 domain-idle-states = <&cluster_c4>; 429 }; 430 431 cluster_pd0: power-domain-cpu-cluster0 { 432 #power-domain-cells = <0>; 433 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 434 power-domains = <&system_pd>; 435 }; 436 437 cluster_pd1: power-domain-cpu-cluster1 { 438 #power-domain-cells = <0>; 439 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 440 power-domains = <&system_pd>; 441 }; 442 443 cluster_pd2: power-domain-cpu-cluster2 { 444 #power-domain-cells = <0>; 445 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 446 power-domains = <&system_pd>; 447 }; 448 449 system_pd: power-domain-system { 450 #power-domain-cells = <0>; 451 /* TODO: system-wide idle states */ 452 }; 453 }; 454 455 reserved-memory { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 460 gunyah_hyp_mem: gunyah-hyp@80000000 { 461 reg = <0x0 0x80000000 0x0 0x800000>; 462 no-map; 463 }; 464 465 hyp_elf_package_mem: hyp-elf-package@80800000 { 466 reg = <0x0 0x80800000 0x0 0x200000>; 467 no-map; 468 }; 469 470 ncc_mem: ncc@80a00000 { 471 reg = <0x0 0x80a00000 0x0 0x400000>; 472 no-map; 473 }; 474 475 cpucp_log_mem: cpucp-log@80e00000 { 476 reg = <0x0 0x80e00000 0x0 0x40000>; 477 no-map; 478 }; 479 480 cpucp_mem: cpucp@80e40000 { 481 reg = <0x0 0x80e40000 0x0 0x540000>; 482 no-map; 483 }; 484 485 reserved-region@81380000 { 486 reg = <0x0 0x81380000 0x0 0x80000>; 487 no-map; 488 }; 489 490 tags_mem: tags-region@81400000 { 491 reg = <0x0 0x81400000 0x0 0x1a0000>; 492 no-map; 493 }; 494 495 xbl_dtlog_mem: xbl-dtlog@81a00000 { 496 reg = <0x0 0x81a00000 0x0 0x40000>; 497 no-map; 498 }; 499 500 xbl_ramdump_mem: xbl-ramdump@81a40000 { 501 reg = <0x0 0x81a40000 0x0 0x1c0000>; 502 no-map; 503 }; 504 505 aop_image_mem: aop-image@81c00000 { 506 reg = <0x0 0x81c00000 0x0 0x60000>; 507 no-map; 508 }; 509 510 aop_cmd_db_mem: aop-cmd-db@81c60000 { 511 compatible = "qcom,cmd-db"; 512 reg = <0x0 0x81c60000 0x0 0x20000>; 513 no-map; 514 }; 515 516 aop_config_mem: aop-config@81c80000 { 517 reg = <0x0 0x81c80000 0x0 0x20000>; 518 no-map; 519 }; 520 521 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 522 reg = <0x0 0x81ca0000 0x0 0x40000>; 523 no-map; 524 }; 525 526 tme_log_mem: tme-log@81ce0000 { 527 reg = <0x0 0x81ce0000 0x0 0x4000>; 528 no-map; 529 }; 530 531 uefi_log_mem: uefi-log@81ce4000 { 532 reg = <0x0 0x81ce4000 0x0 0x10000>; 533 no-map; 534 }; 535 536 secdata_apss_mem: secdata-apss@81cff000 { 537 reg = <0x0 0x81cff000 0x0 0x1000>; 538 no-map; 539 }; 540 541 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 542 reg = <0x0 0x81e00000 0x0 0x100000>; 543 no-map; 544 }; 545 546 gpu_prr_mem: gpu-prr@81f00000 { 547 reg = <0x0 0x81f00000 0x0 0x10000>; 548 no-map; 549 }; 550 551 tpm_control_mem: tpm-control@81f10000 { 552 reg = <0x0 0x81f10000 0x0 0x10000>; 553 no-map; 554 }; 555 556 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 557 reg = <0x0 0x81f20000 0x0 0x10000>; 558 no-map; 559 }; 560 561 pld_pep_mem: pld-pep@81f30000 { 562 reg = <0x0 0x81f30000 0x0 0x6000>; 563 no-map; 564 }; 565 566 pld_gmu_mem: pld-gmu@81f36000 { 567 reg = <0x0 0x81f36000 0x0 0x1000>; 568 no-map; 569 }; 570 571 pld_pdp_mem: pld-pdp@81f37000 { 572 reg = <0x0 0x81f37000 0x0 0x1000>; 573 no-map; 574 }; 575 576 tz_stat_mem: tz-stat@82700000 { 577 reg = <0x0 0x82700000 0x0 0x100000>; 578 no-map; 579 }; 580 581 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 582 reg = <0x0 0x82800000 0x0 0xc00000>; 583 no-map; 584 }; 585 586 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 587 reg = <0x0 0x84b00000 0x0 0x800000>; 588 no-map; 589 }; 590 591 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 592 reg = <0x0 0x85300000 0x0 0x80000>; 593 no-map; 594 }; 595 596 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 597 reg = <0x0 0x866c0000 0x0 0x40000>; 598 no-map; 599 }; 600 601 spss_region_mem: spss-region@86700000 { 602 reg = <0x0 0x86700000 0x0 0x400000>; 603 no-map; 604 }; 605 606 adsp_boot_mem: adsp-boot@86b00000 { 607 reg = <0x0 0x86b00000 0x0 0xc00000>; 608 no-map; 609 }; 610 611 video_mem: video@87700000 { 612 reg = <0x0 0x87700000 0x0 0x700000>; 613 no-map; 614 }; 615 616 adspslpi_mem: adspslpi@87e00000 { 617 reg = <0x0 0x87e00000 0x0 0x3a00000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 622 reg = <0x0 0x8b800000 0x0 0x80000>; 623 no-map; 624 }; 625 626 cdsp_mem: cdsp@8b900000 { 627 reg = <0x0 0x8b900000 0x0 0x2000000>; 628 no-map; 629 }; 630 631 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 632 reg = <0x0 0x8d900000 0x0 0x80000>; 633 no-map; 634 }; 635 636 gpu_microcode_mem: gpu-microcode@8d9fe000 { 637 reg = <0x0 0x8d9fe000 0x0 0x2000>; 638 no-map; 639 }; 640 641 cvp_mem: cvp@8da00000 { 642 reg = <0x0 0x8da00000 0x0 0x700000>; 643 no-map; 644 }; 645 646 camera_mem: camera@8e100000 { 647 reg = <0x0 0x8e100000 0x0 0x800000>; 648 no-map; 649 }; 650 651 av1_encoder_mem: av1-encoder@8e900000 { 652 reg = <0x0 0x8e900000 0x0 0x700000>; 653 no-map; 654 }; 655 656 reserved-region@8f000000 { 657 reg = <0x0 0x8f000000 0x0 0xa00000>; 658 no-map; 659 }; 660 661 wpss_mem: wpss@8fa00000 { 662 reg = <0x0 0x8fa00000 0x0 0x1900000>; 663 no-map; 664 }; 665 666 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 667 reg = <0x0 0x91300000 0x0 0x80000>; 668 no-map; 669 }; 670 671 xbl_sc_mem: xbl-sc@d8000000 { 672 reg = <0x0 0xd8000000 0x0 0x40000>; 673 no-map; 674 }; 675 676 reserved-region@d8040000 { 677 reg = <0x0 0xd8040000 0x0 0xa0000>; 678 no-map; 679 }; 680 681 qtee_mem: qtee@d80e0000 { 682 reg = <0x0 0xd80e0000 0x0 0x520000>; 683 no-map; 684 }; 685 686 ta_mem: ta@d8600000 { 687 reg = <0x0 0xd8600000 0x0 0x8a00000>; 688 no-map; 689 }; 690 691 tags_mem1: tags@e1000000 { 692 reg = <0x0 0xe1000000 0x0 0x26a0000>; 693 no-map; 694 }; 695 696 llcc_lpi_mem: llcc-lpi@ff800000 { 697 reg = <0x0 0xff800000 0x0 0x600000>; 698 no-map; 699 }; 700 701 smem_mem: smem@ffe00000 { 702 compatible = "qcom,smem"; 703 reg = <0x0 0xffe00000 0x0 0x200000>; 704 hwlocks = <&tcsr_mutex 3>; 705 no-map; 706 }; 707 }; 708 709 qup_opp_table_100mhz: opp-table-qup100mhz { 710 compatible = "operating-points-v2"; 711 712 opp-75000000 { 713 opp-hz = /bits/ 64 <75000000>; 714 required-opps = <&rpmhpd_opp_low_svs>; 715 }; 716 717 opp-100000000 { 718 opp-hz = /bits/ 64 <100000000>; 719 required-opps = <&rpmhpd_opp_svs>; 720 }; 721 }; 722 723 qup_opp_table_120mhz: opp-table-qup120mhz { 724 compatible = "operating-points-v2"; 725 726 opp-75000000 { 727 opp-hz = /bits/ 64 <75000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 }; 730 731 opp-120000000 { 732 opp-hz = /bits/ 64 <120000000>; 733 required-opps = <&rpmhpd_opp_svs>; 734 }; 735 }; 736 737 smp2p-adsp { 738 compatible = "qcom,smp2p"; 739 740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 741 IPCC_MPROC_SIGNAL_SMP2P 742 IRQ_TYPE_EDGE_RISING>; 743 744 mboxes = <&ipcc IPCC_CLIENT_LPASS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,smem = <443>, <429>; 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <2>; 750 751 smp2p_adsp_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_adsp_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 smp2p-cdsp { 764 compatible = "qcom,smp2p"; 765 766 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 767 IPCC_MPROC_SIGNAL_SMP2P 768 IRQ_TYPE_EDGE_RISING>; 769 770 mboxes = <&ipcc IPCC_CLIENT_CDSP 771 IPCC_MPROC_SIGNAL_SMP2P>; 772 773 qcom,smem = <94>, <432>; 774 qcom,local-pid = <0>; 775 qcom,remote-pid = <5>; 776 777 smp2p_cdsp_out: master-kernel { 778 qcom,entry-name = "master-kernel"; 779 #qcom,smem-state-cells = <1>; 780 }; 781 782 smp2p_cdsp_in: slave-kernel { 783 qcom,entry-name = "slave-kernel"; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 }; 787 }; 788 789 soc: soc@0 { 790 compatible = "simple-bus"; 791 792 #address-cells = <2>; 793 #size-cells = <2>; 794 dma-ranges = <0 0 0 0 0x10 0>; 795 ranges = <0 0 0 0 0x10 0>; 796 797 gcc: clock-controller@100000 { 798 compatible = "qcom,x1e80100-gcc"; 799 reg = <0 0x00100000 0 0x200000>; 800 801 clocks = <&bi_tcxo_div2>, 802 <&sleep_clk>, 803 <&pcie3_phy>, 804 <&pcie4_phy>, 805 <&pcie5_phy>, 806 <&pcie6a_phy>, 807 <0>, 808 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 809 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 810 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 811 <0>, 812 <0>, 813 <0>, 814 <0>, 815 <0>, 816 <0>, 817 <0>, 818 <0>, 819 <0>, 820 <0>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>; 838 839 power-domains = <&rpmhpd RPMHPD_CX>; 840 #clock-cells = <1>; 841 #reset-cells = <1>; 842 #power-domain-cells = <1>; 843 }; 844 845 ipcc: mailbox@408000 { 846 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 847 reg = <0 0x00408000 0 0x1000>; 848 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-controller; 851 #interrupt-cells = <3>; 852 853 #mbox-cells = <2>; 854 }; 855 856 gpi_dma2: dma-controller@800000 { 857 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 858 reg = <0 0x00800000 0 0x60000>; 859 860 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 872 873 dma-channels = <12>; 874 dma-channel-mask = <0x3e>; 875 #dma-cells = <3>; 876 877 iommus = <&apps_smmu 0x436 0x0>; 878 879 status = "disabled"; 880 }; 881 882 qupv3_2: geniqup@8c0000 { 883 compatible = "qcom,geni-se-qup"; 884 reg = <0 0x008c0000 0 0x2000>; 885 886 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 887 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 888 clock-names = "m-ahb", 889 "s-ahb"; 890 891 iommus = <&apps_smmu 0x423 0x0>; 892 893 #address-cells = <2>; 894 #size-cells = <2>; 895 ranges; 896 897 status = "disabled"; 898 899 i2c16: i2c@880000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0 0x00880000 0 0x4000>; 902 903 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 904 905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 906 clock-names = "se"; 907 908 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 909 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 910 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 911 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 912 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 913 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 914 interconnect-names = "qup-core", 915 "qup-config", 916 "qup-memory"; 917 918 power-domains = <&rpmhpd RPMHPD_CX>; 919 required-opps = <&rpmhpd_opp_low_svs>; 920 921 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 922 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 923 dma-names = "tx", 924 "rx"; 925 926 pinctrl-0 = <&qup_i2c16_data_clk>; 927 pinctrl-names = "default"; 928 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 status = "disabled"; 933 }; 934 935 spi16: spi@880000 { 936 compatible = "qcom,geni-spi"; 937 reg = <0 0x00880000 0 0x4000>; 938 939 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 940 941 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 942 clock-names = "se"; 943 944 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 945 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 947 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 948 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 949 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 950 interconnect-names = "qup-core", 951 "qup-config", 952 "qup-memory"; 953 954 power-domains = <&rpmhpd RPMHPD_CX>; 955 operating-points-v2 = <&qup_opp_table_120mhz>; 956 957 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 958 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 959 dma-names = "tx", 960 "rx"; 961 962 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 963 pinctrl-names = "default"; 964 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 status = "disabled"; 969 }; 970 971 i2c17: i2c@884000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00884000 0 0x4000>; 974 975 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 976 977 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 978 clock-names = "se"; 979 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 981 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 983 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 984 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 986 interconnect-names = "qup-core", 987 "qup-config", 988 "qup-memory"; 989 990 power-domains = <&rpmhpd RPMHPD_CX>; 991 required-opps = <&rpmhpd_opp_low_svs>; 992 993 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 994 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 995 dma-names = "tx", 996 "rx"; 997 998 pinctrl-0 = <&qup_i2c17_data_clk>; 999 pinctrl-names = "default"; 1000 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 1004 status = "disabled"; 1005 }; 1006 1007 spi17: spi@884000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00884000 0 0x4000>; 1010 1011 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1014 clock-names = "se"; 1015 1016 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1017 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1018 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1019 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1020 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1021 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1022 interconnect-names = "qup-core", 1023 "qup-config", 1024 "qup-memory"; 1025 1026 power-domains = <&rpmhpd RPMHPD_CX>; 1027 operating-points-v2 = <&qup_opp_table_120mhz>; 1028 1029 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1030 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1031 dma-names = "tx", 1032 "rx"; 1033 1034 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1035 pinctrl-names = "default"; 1036 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 status = "disabled"; 1041 }; 1042 1043 i2c18: i2c@888000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00888000 0 0x4000>; 1046 1047 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1048 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1050 clock-names = "se"; 1051 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1055 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1056 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 1062 power-domains = <&rpmhpd RPMHPD_CX>; 1063 required-opps = <&rpmhpd_opp_low_svs>; 1064 1065 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1066 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1067 dma-names = "tx", 1068 "rx"; 1069 1070 pinctrl-0 = <&qup_i2c18_data_clk>; 1071 pinctrl-names = "default"; 1072 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 1076 status = "disabled"; 1077 }; 1078 1079 spi18: spi@888000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x00888000 0 0x4000>; 1082 1083 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1084 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1086 clock-names = "se"; 1087 1088 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1089 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1091 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1092 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1094 interconnect-names = "qup-core", 1095 "qup-config", 1096 "qup-memory"; 1097 1098 power-domains = <&rpmhpd RPMHPD_CX>; 1099 operating-points-v2 = <&qup_opp_table_100mhz>; 1100 1101 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1102 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1103 dma-names = "tx", 1104 "rx"; 1105 1106 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1107 pinctrl-names = "default"; 1108 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 status = "disabled"; 1113 }; 1114 1115 i2c19: i2c@88c000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0 0x0088c000 0 0x4000>; 1118 1119 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1120 1121 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1122 clock-names = "se"; 1123 1124 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1125 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1126 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1127 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1128 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1129 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1130 interconnect-names = "qup-core", 1131 "qup-config", 1132 "qup-memory"; 1133 1134 power-domains = <&rpmhpd RPMHPD_CX>; 1135 required-opps = <&rpmhpd_opp_low_svs>; 1136 1137 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1138 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1139 dma-names = "tx", 1140 "rx"; 1141 1142 pinctrl-0 = <&qup_i2c19_data_clk>; 1143 pinctrl-names = "default"; 1144 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 1148 status = "disabled"; 1149 }; 1150 1151 spi19: spi@88c000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0 0x0088c000 0 0x4000>; 1154 1155 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1156 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1158 clock-names = "se"; 1159 1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1161 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1162 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1163 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1164 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1166 interconnect-names = "qup-core", 1167 "qup-config", 1168 "qup-memory"; 1169 1170 power-domains = <&rpmhpd RPMHPD_CX>; 1171 operating-points-v2 = <&qup_opp_table_100mhz>; 1172 1173 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1174 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1175 dma-names = "tx", 1176 "rx"; 1177 1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1179 pinctrl-names = "default"; 1180 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 status = "disabled"; 1185 }; 1186 1187 i2c20: i2c@890000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0 0x00890000 0 0x4000>; 1190 1191 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1192 1193 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1194 clock-names = "se"; 1195 1196 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1197 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1198 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1199 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1200 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1201 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "qup-core", 1203 "qup-config", 1204 "qup-memory"; 1205 1206 power-domains = <&rpmhpd RPMHPD_CX>; 1207 required-opps = <&rpmhpd_opp_low_svs>; 1208 1209 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1210 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1211 dma-names = "tx", 1212 "rx"; 1213 1214 pinctrl-0 = <&qup_i2c20_data_clk>; 1215 pinctrl-names = "default"; 1216 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 1220 status = "disabled"; 1221 }; 1222 1223 spi20: spi@890000 { 1224 compatible = "qcom,geni-spi"; 1225 reg = <0 0x00890000 0 0x4000>; 1226 1227 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1228 1229 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1230 clock-names = "se"; 1231 1232 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1233 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1235 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1236 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1237 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1238 interconnect-names = "qup-core", 1239 "qup-config", 1240 "qup-memory"; 1241 1242 power-domains = <&rpmhpd RPMHPD_CX>; 1243 operating-points-v2 = <&qup_opp_table_100mhz>; 1244 1245 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1247 dma-names = "tx", 1248 "rx"; 1249 1250 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1251 pinctrl-names = "default"; 1252 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 1256 status = "disabled"; 1257 }; 1258 1259 i2c21: i2c@894000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00894000 0 0x4000>; 1262 1263 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1264 1265 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1266 clock-names = "se"; 1267 1268 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1269 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1270 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1271 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1272 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1273 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1274 interconnect-names = "qup-core", 1275 "qup-config", 1276 "qup-memory"; 1277 1278 power-domains = <&rpmhpd RPMHPD_CX>; 1279 required-opps = <&rpmhpd_opp_low_svs>; 1280 1281 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1282 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1283 dma-names = "tx", 1284 "rx"; 1285 1286 pinctrl-0 = <&qup_i2c21_data_clk>; 1287 pinctrl-names = "default"; 1288 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 1292 status = "disabled"; 1293 }; 1294 1295 spi21: spi@894000 { 1296 compatible = "qcom,geni-spi"; 1297 reg = <0 0x00894000 0 0x4000>; 1298 1299 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1300 1301 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1302 clock-names = "se"; 1303 1304 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1305 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1306 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1307 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1308 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1309 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1310 interconnect-names = "qup-core", 1311 "qup-config", 1312 "qup-memory"; 1313 1314 power-domains = <&rpmhpd RPMHPD_CX>; 1315 operating-points-v2 = <&qup_opp_table_100mhz>; 1316 1317 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1318 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1319 dma-names = "tx", 1320 "rx"; 1321 1322 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1323 pinctrl-names = "default"; 1324 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 status = "disabled"; 1329 }; 1330 1331 uart21: serial@894000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0 0x00894000 0 0x4000>; 1334 1335 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1336 1337 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1338 clock-names = "se"; 1339 1340 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1343 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1344 interconnect-names = "qup-core", 1345 "qup-config"; 1346 1347 power-domains = <&rpmhpd RPMHPD_CX>; 1348 operating-points-v2 = <&qup_opp_table_100mhz>; 1349 1350 pinctrl-0 = <&qup_uart21_default>; 1351 pinctrl-names = "default"; 1352 1353 status = "disabled"; 1354 }; 1355 1356 i2c22: i2c@898000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00898000 0 0x4000>; 1359 1360 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1361 1362 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1363 clock-names = "se"; 1364 1365 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1366 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1368 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1369 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1370 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1371 interconnect-names = "qup-core", 1372 "qup-config", 1373 "qup-memory"; 1374 1375 power-domains = <&rpmhpd RPMHPD_CX>; 1376 required-opps = <&rpmhpd_opp_low_svs>; 1377 1378 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1379 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1380 dma-names = "tx", 1381 "rx"; 1382 1383 pinctrl-0 = <&qup_i2c22_data_clk>; 1384 pinctrl-names = "default"; 1385 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 1389 status = "disabled"; 1390 }; 1391 1392 spi22: spi@898000 { 1393 compatible = "qcom,geni-spi"; 1394 reg = <0 0x00898000 0 0x4000>; 1395 1396 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1397 1398 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1399 clock-names = "se"; 1400 1401 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1402 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1403 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1404 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1405 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1406 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1407 interconnect-names = "qup-core", 1408 "qup-config", 1409 "qup-memory"; 1410 1411 power-domains = <&rpmhpd RPMHPD_CX>; 1412 operating-points-v2 = <&qup_opp_table_100mhz>; 1413 1414 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1415 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1416 dma-names = "tx", 1417 "rx"; 1418 1419 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1420 pinctrl-names = "default"; 1421 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 1425 status = "disabled"; 1426 }; 1427 1428 i2c23: i2c@89c000 { 1429 compatible = "qcom,geni-i2c"; 1430 reg = <0 0x0089c000 0 0x4000>; 1431 1432 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1433 1434 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1435 clock-names = "se"; 1436 1437 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1438 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1439 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1440 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1441 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1442 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1443 interconnect-names = "qup-core", 1444 "qup-config", 1445 "qup-memory"; 1446 1447 power-domains = <&rpmhpd RPMHPD_CX>; 1448 required-opps = <&rpmhpd_opp_low_svs>; 1449 1450 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1451 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1452 dma-names = "tx", 1453 "rx"; 1454 1455 pinctrl-0 = <&qup_i2c23_data_clk>; 1456 pinctrl-names = "default"; 1457 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 1461 status = "disabled"; 1462 }; 1463 1464 spi23: spi@89c000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x0089c000 0 0x4000>; 1467 1468 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1469 1470 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1471 clock-names = "se"; 1472 1473 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1474 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1475 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1476 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1477 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1478 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1479 interconnect-names = "qup-core", 1480 "qup-config", 1481 "qup-memory"; 1482 1483 power-domains = <&rpmhpd RPMHPD_CX>; 1484 operating-points-v2 = <&qup_opp_table_100mhz>; 1485 1486 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1487 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1488 dma-names = "tx", 1489 "rx"; 1490 1491 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1492 pinctrl-names = "default"; 1493 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 1497 status = "disabled"; 1498 }; 1499 }; 1500 1501 gpi_dma1: dma-controller@a00000 { 1502 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1503 reg = <0 0x00a00000 0 0x60000>; 1504 1505 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1517 1518 dma-channels = <12>; 1519 dma-channel-mask = <0x3e>; 1520 #dma-cells = <3>; 1521 1522 iommus = <&apps_smmu 0x136 0x0>; 1523 1524 status = "disabled"; 1525 }; 1526 1527 qupv3_1: geniqup@ac0000 { 1528 compatible = "qcom,geni-se-qup"; 1529 reg = <0 0x00ac0000 0 0x2000>; 1530 1531 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1532 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1533 clock-names = "m-ahb", 1534 "s-ahb"; 1535 1536 iommus = <&apps_smmu 0x123 0x0>; 1537 1538 #address-cells = <2>; 1539 #size-cells = <2>; 1540 ranges; 1541 1542 status = "disabled"; 1543 1544 i2c8: i2c@a80000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00a80000 0 0x4000>; 1547 1548 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1549 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1551 clock-names = "se"; 1552 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1554 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1555 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1556 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1557 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1558 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1559 interconnect-names = "qup-core", 1560 "qup-config", 1561 "qup-memory"; 1562 1563 power-domains = <&rpmhpd RPMHPD_CX>; 1564 required-opps = <&rpmhpd_opp_low_svs>; 1565 1566 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1568 dma-names = "tx", 1569 "rx"; 1570 1571 pinctrl-0 = <&qup_i2c8_data_clk>; 1572 pinctrl-names = "default"; 1573 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 status = "disabled"; 1578 }; 1579 1580 spi8: spi@a80000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a80000 0 0x4000>; 1583 1584 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1585 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1587 clock-names = "se"; 1588 1589 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1590 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1591 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1592 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1593 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1594 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1595 interconnect-names = "qup-core", 1596 "qup-config", 1597 "qup-memory"; 1598 1599 power-domains = <&rpmhpd RPMHPD_CX>; 1600 operating-points-v2 = <&qup_opp_table_120mhz>; 1601 1602 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1603 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1604 dma-names = "tx", 1605 "rx"; 1606 1607 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1608 pinctrl-names = "default"; 1609 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 1613 status = "disabled"; 1614 }; 1615 1616 i2c9: i2c@a84000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a84000 0 0x4000>; 1619 1620 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1621 1622 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1623 clock-names = "se"; 1624 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1626 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1627 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1628 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1629 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1630 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1631 interconnect-names = "qup-core", 1632 "qup-config", 1633 "qup-memory"; 1634 1635 power-domains = <&rpmhpd RPMHPD_CX>; 1636 required-opps = <&rpmhpd_opp_low_svs>; 1637 1638 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1639 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1640 dma-names = "tx", 1641 "rx"; 1642 1643 pinctrl-0 = <&qup_i2c9_data_clk>; 1644 pinctrl-names = "default"; 1645 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 spi9: spi@a84000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0 0x00a84000 0 0x4000>; 1655 1656 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1657 1658 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1659 clock-names = "se"; 1660 1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1662 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1663 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1664 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1665 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1666 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1667 interconnect-names = "qup-core", 1668 "qup-config", 1669 "qup-memory"; 1670 1671 power-domains = <&rpmhpd RPMHPD_CX>; 1672 operating-points-v2 = <&qup_opp_table_120mhz>; 1673 1674 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1675 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1676 dma-names = "tx", 1677 "rx"; 1678 1679 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1680 pinctrl-names = "default"; 1681 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 1685 status = "disabled"; 1686 }; 1687 1688 i2c10: i2c@a88000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a88000 0 0x4000>; 1691 1692 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1693 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1695 clock-names = "se"; 1696 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1698 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1699 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1700 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1701 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1702 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1703 interconnect-names = "qup-core", 1704 "qup-config", 1705 "qup-memory"; 1706 1707 power-domains = <&rpmhpd RPMHPD_CX>; 1708 required-opps = <&rpmhpd_opp_low_svs>; 1709 1710 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1711 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1712 dma-names = "tx", 1713 "rx"; 1714 1715 pinctrl-0 = <&qup_i2c10_data_clk>; 1716 pinctrl-names = "default"; 1717 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 1721 status = "disabled"; 1722 }; 1723 1724 spi10: spi@a88000 { 1725 compatible = "qcom,geni-spi"; 1726 reg = <0 0x00a88000 0 0x4000>; 1727 1728 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1729 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1731 clock-names = "se"; 1732 1733 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1734 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1735 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1736 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1737 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1738 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1739 interconnect-names = "qup-core", 1740 "qup-config", 1741 "qup-memory"; 1742 1743 power-domains = <&rpmhpd RPMHPD_CX>; 1744 operating-points-v2 = <&qup_opp_table_100mhz>; 1745 1746 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1747 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1748 dma-names = "tx", 1749 "rx"; 1750 1751 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1752 pinctrl-names = "default"; 1753 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 status = "disabled"; 1758 }; 1759 1760 i2c11: i2c@a8c000 { 1761 compatible = "qcom,geni-i2c"; 1762 reg = <0 0x00a8c000 0 0x4000>; 1763 1764 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1765 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1767 clock-names = "se"; 1768 1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1770 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1772 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1773 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1775 interconnect-names = "qup-core", 1776 "qup-config", 1777 "qup-memory"; 1778 1779 power-domains = <&rpmhpd RPMHPD_CX>; 1780 required-opps = <&rpmhpd_opp_low_svs>; 1781 1782 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1783 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1784 dma-names = "tx", 1785 "rx"; 1786 1787 pinctrl-0 = <&qup_i2c11_data_clk>; 1788 pinctrl-names = "default"; 1789 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 1793 status = "disabled"; 1794 }; 1795 1796 spi11: spi@a8c000 { 1797 compatible = "qcom,geni-spi"; 1798 reg = <0 0x00a8c000 0 0x4000>; 1799 1800 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1801 1802 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1803 clock-names = "se"; 1804 1805 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1806 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1807 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1808 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1809 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1810 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1811 interconnect-names = "qup-core", 1812 "qup-config", 1813 "qup-memory"; 1814 1815 power-domains = <&rpmhpd RPMHPD_CX>; 1816 operating-points-v2 = <&qup_opp_table_100mhz>; 1817 1818 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1819 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1820 dma-names = "tx", 1821 "rx"; 1822 1823 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1824 pinctrl-names = "default"; 1825 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 status = "disabled"; 1830 }; 1831 1832 i2c12: i2c@a90000 { 1833 compatible = "qcom,geni-i2c"; 1834 reg = <0 0x00a90000 0 0x4000>; 1835 1836 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1837 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1839 clock-names = "se"; 1840 1841 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1842 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1843 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1844 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1845 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1846 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1847 interconnect-names = "qup-core", 1848 "qup-config", 1849 "qup-memory"; 1850 1851 power-domains = <&rpmhpd RPMHPD_CX>; 1852 required-opps = <&rpmhpd_opp_low_svs>; 1853 1854 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1855 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1856 dma-names = "tx", 1857 "rx"; 1858 1859 pinctrl-0 = <&qup_i2c12_data_clk>; 1860 pinctrl-names = "default"; 1861 1862 #address-cells = <1>; 1863 #size-cells = <0>; 1864 1865 status = "disabled"; 1866 }; 1867 1868 spi12: spi@a90000 { 1869 compatible = "qcom,geni-spi"; 1870 reg = <0 0x00a90000 0 0x4000>; 1871 1872 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1873 1874 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1875 clock-names = "se"; 1876 1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1878 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1879 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1880 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1881 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1882 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1883 interconnect-names = "qup-core", 1884 "qup-config", 1885 "qup-memory"; 1886 1887 power-domains = <&rpmhpd RPMHPD_CX>; 1888 operating-points-v2 = <&qup_opp_table_100mhz>; 1889 1890 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1891 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1892 dma-names = "tx", 1893 "rx"; 1894 1895 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1896 pinctrl-names = "default"; 1897 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 status = "disabled"; 1902 }; 1903 1904 i2c13: i2c@a94000 { 1905 compatible = "qcom,geni-i2c"; 1906 reg = <0 0x00a94000 0 0x4000>; 1907 1908 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1909 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1911 clock-names = "se"; 1912 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1914 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1915 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1916 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1917 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1918 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1919 interconnect-names = "qup-core", 1920 "qup-config", 1921 "qup-memory"; 1922 1923 power-domains = <&rpmhpd RPMHPD_CX>; 1924 required-opps = <&rpmhpd_opp_low_svs>; 1925 1926 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1927 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1928 dma-names = "tx", 1929 "rx"; 1930 1931 pinctrl-0 = <&qup_i2c13_data_clk>; 1932 pinctrl-names = "default"; 1933 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 1937 status = "disabled"; 1938 }; 1939 1940 spi13: spi@a94000 { 1941 compatible = "qcom,geni-spi"; 1942 reg = <0 0x00a94000 0 0x4000>; 1943 1944 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1945 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1947 clock-names = "se"; 1948 1949 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1950 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1952 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1953 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1955 interconnect-names = "qup-core", 1956 "qup-config", 1957 "qup-memory"; 1958 1959 power-domains = <&rpmhpd RPMHPD_CX>; 1960 operating-points-v2 = <&qup_opp_table_100mhz>; 1961 1962 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1963 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1964 dma-names = "tx", 1965 "rx"; 1966 1967 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1968 pinctrl-names = "default"; 1969 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 status = "disabled"; 1974 }; 1975 1976 i2c14: i2c@a98000 { 1977 compatible = "qcom,geni-i2c"; 1978 reg = <0 0x00a98000 0 0x4000>; 1979 1980 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1981 1982 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1983 clock-names = "se"; 1984 1985 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1986 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1987 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1988 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1989 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1990 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1991 interconnect-names = "qup-core", 1992 "qup-config", 1993 "qup-memory"; 1994 1995 power-domains = <&rpmhpd RPMHPD_CX>; 1996 required-opps = <&rpmhpd_opp_low_svs>; 1997 1998 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1999 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2000 dma-names = "tx", 2001 "rx"; 2002 2003 pinctrl-0 = <&qup_i2c14_data_clk>; 2004 pinctrl-names = "default"; 2005 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 2009 status = "disabled"; 2010 }; 2011 2012 spi14: spi@a98000 { 2013 compatible = "qcom,geni-spi"; 2014 reg = <0 0x00a98000 0 0x4000>; 2015 2016 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2017 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2019 clock-names = "se"; 2020 2021 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2022 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2024 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2025 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2027 interconnect-names = "qup-core", 2028 "qup-config", 2029 "qup-memory"; 2030 2031 power-domains = <&rpmhpd RPMHPD_CX>; 2032 operating-points-v2 = <&qup_opp_table_100mhz>; 2033 2034 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2035 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2036 dma-names = "tx", 2037 "rx"; 2038 2039 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2040 pinctrl-names = "default"; 2041 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 2045 status = "disabled"; 2046 }; 2047 2048 uart14: serial@a98000 { 2049 compatible = "qcom,geni-uart"; 2050 reg = <0 0x00a98000 0 0x4000>; 2051 2052 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2053 2054 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2055 clock-names = "se"; 2056 2057 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2058 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2060 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2061 interconnect-names = "qup-core", 2062 "qup-config"; 2063 2064 power-domains = <&rpmhpd RPMHPD_CX>; 2065 operating-points-v2 = <&qup_opp_table_100mhz>; 2066 2067 pinctrl-0 = <&qup_uart14_default>; 2068 pinctrl-names = "default"; 2069 2070 status = "disabled"; 2071 }; 2072 2073 i2c15: i2c@a9c000 { 2074 compatible = "qcom,geni-i2c"; 2075 reg = <0 0x00a9c000 0 0x4000>; 2076 2077 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2078 2079 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2080 clock-names = "se"; 2081 2082 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2083 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2084 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2085 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2086 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2087 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2088 interconnect-names = "qup-core", 2089 "qup-config", 2090 "qup-memory"; 2091 2092 power-domains = <&rpmhpd RPMHPD_CX>; 2093 required-opps = <&rpmhpd_opp_low_svs>; 2094 2095 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2096 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2097 dma-names = "tx", 2098 "rx"; 2099 2100 pinctrl-0 = <&qup_i2c15_data_clk>; 2101 pinctrl-names = "default"; 2102 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 spi15: spi@a9c000 { 2110 compatible = "qcom,geni-spi"; 2111 reg = <0 0x00a9c000 0 0x4000>; 2112 2113 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2114 2115 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2116 clock-names = "se"; 2117 2118 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2119 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2121 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2122 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2124 interconnect-names = "qup-core", 2125 "qup-config", 2126 "qup-memory"; 2127 2128 power-domains = <&rpmhpd RPMHPD_CX>; 2129 operating-points-v2 = <&qup_opp_table_100mhz>; 2130 2131 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2132 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2133 dma-names = "tx", 2134 "rx"; 2135 2136 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2137 pinctrl-names = "default"; 2138 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 2142 status = "disabled"; 2143 }; 2144 }; 2145 2146 gpi_dma0: dma-controller@b00000 { 2147 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2148 reg = <0 0x00b00000 0 0x60000>; 2149 2150 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2162 2163 dma-channels = <12>; 2164 dma-channel-mask = <0x3e>; 2165 #dma-cells = <3>; 2166 2167 iommus = <&apps_smmu 0x456 0x0>; 2168 2169 status = "disabled"; 2170 }; 2171 2172 qupv3_0: geniqup@bc0000 { 2173 compatible = "qcom,geni-se-qup"; 2174 reg = <0 0x00bc0000 0 0x2000>; 2175 2176 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2177 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2178 clock-names = "m-ahb", 2179 "s-ahb"; 2180 2181 iommus = <&apps_smmu 0x443 0x0>; 2182 #address-cells = <2>; 2183 #size-cells = <2>; 2184 ranges; 2185 2186 status = "disabled"; 2187 2188 i2c0: i2c@b80000 { 2189 compatible = "qcom,geni-i2c"; 2190 reg = <0 0x00b80000 0 0x4000>; 2191 2192 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2193 2194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2195 clock-names = "se"; 2196 2197 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2198 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2200 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2201 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2203 interconnect-names = "qup-core", 2204 "qup-config", 2205 "qup-memory"; 2206 2207 power-domains = <&rpmhpd RPMHPD_CX>; 2208 required-opps = <&rpmhpd_opp_low_svs>; 2209 2210 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2211 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2212 dma-names = "tx", 2213 "rx"; 2214 2215 pinctrl-0 = <&qup_i2c0_data_clk>; 2216 pinctrl-names = "default"; 2217 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 2221 status = "disabled"; 2222 }; 2223 2224 spi0: spi@b80000 { 2225 compatible = "qcom,geni-spi"; 2226 reg = <0 0x00b80000 0 0x4000>; 2227 2228 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2229 2230 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2231 clock-names = "se"; 2232 2233 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2234 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2235 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2236 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2237 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2239 interconnect-names = "qup-core", 2240 "qup-config", 2241 "qup-memory"; 2242 2243 power-domains = <&rpmhpd RPMHPD_CX>; 2244 operating-points-v2 = <&qup_opp_table_120mhz>; 2245 2246 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2247 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2248 dma-names = "tx", 2249 "rx"; 2250 2251 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2252 pinctrl-names = "default"; 2253 2254 #address-cells = <1>; 2255 #size-cells = <0>; 2256 2257 status = "disabled"; 2258 }; 2259 2260 i2c1: i2c@b84000 { 2261 compatible = "qcom,geni-i2c"; 2262 reg = <0 0x00b84000 0 0x4000>; 2263 2264 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2265 2266 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2267 clock-names = "se"; 2268 2269 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2270 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2271 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2272 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2273 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2275 interconnect-names = "qup-core", 2276 "qup-config", 2277 "qup-memory"; 2278 2279 power-domains = <&rpmhpd RPMHPD_CX>; 2280 required-opps = <&rpmhpd_opp_low_svs>; 2281 2282 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2283 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2284 dma-names = "tx", 2285 "rx"; 2286 2287 pinctrl-0 = <&qup_i2c1_data_clk>; 2288 pinctrl-names = "default"; 2289 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 spi1: spi@b84000 { 2297 compatible = "qcom,geni-spi"; 2298 reg = <0 0x00b84000 0 0x4000>; 2299 2300 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2301 2302 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2303 clock-names = "se"; 2304 2305 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2306 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2307 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2308 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2309 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2311 interconnect-names = "qup-core", 2312 "qup-config", 2313 "qup-memory"; 2314 2315 power-domains = <&rpmhpd RPMHPD_CX>; 2316 operating-points-v2 = <&qup_opp_table_120mhz>; 2317 2318 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2319 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2320 dma-names = "tx", 2321 "rx"; 2322 2323 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2324 pinctrl-names = "default"; 2325 2326 #address-cells = <1>; 2327 #size-cells = <0>; 2328 2329 status = "disabled"; 2330 }; 2331 2332 i2c2: i2c@b88000 { 2333 compatible = "qcom,geni-i2c"; 2334 reg = <0 0x00b88000 0 0x4000>; 2335 2336 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2337 2338 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2339 clock-names = "se"; 2340 2341 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2342 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2343 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2344 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2345 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2347 interconnect-names = "qup-core", 2348 "qup-config", 2349 "qup-memory"; 2350 2351 power-domains = <&rpmhpd RPMHPD_CX>; 2352 required-opps = <&rpmhpd_opp_low_svs>; 2353 2354 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2355 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2356 dma-names = "tx", 2357 "rx"; 2358 2359 pinctrl-0 = <&qup_i2c2_data_clk>; 2360 pinctrl-names = "default"; 2361 2362 #address-cells = <1>; 2363 #size-cells = <0>; 2364 2365 status = "disabled"; 2366 }; 2367 2368 uart2: serial@b88000 { 2369 compatible = "qcom,geni-uart"; 2370 reg = <0 0x00b88000 0 0x4000>; 2371 2372 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2373 2374 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2375 clock-names = "se"; 2376 2377 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2378 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2379 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2380 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2381 interconnect-names = "qup-core", 2382 "qup-config"; 2383 2384 power-domains = <&rpmhpd RPMHPD_CX>; 2385 operating-points-v2 = <&qup_opp_table_100mhz>; 2386 2387 pinctrl-0 = <&qup_uart2_default>; 2388 pinctrl-names = "default"; 2389 2390 status = "disabled"; 2391 }; 2392 2393 spi2: spi@b88000 { 2394 compatible = "qcom,geni-spi"; 2395 reg = <0 0x00b88000 0 0x4000>; 2396 2397 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2398 2399 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2400 clock-names = "se"; 2401 2402 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2403 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2405 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2406 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2408 interconnect-names = "qup-core", 2409 "qup-config", 2410 "qup-memory"; 2411 2412 power-domains = <&rpmhpd RPMHPD_CX>; 2413 operating-points-v2 = <&qup_opp_table_100mhz>; 2414 2415 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2416 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2417 dma-names = "tx", 2418 "rx"; 2419 2420 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2421 pinctrl-names = "default"; 2422 2423 #address-cells = <1>; 2424 #size-cells = <0>; 2425 2426 status = "disabled"; 2427 }; 2428 2429 i2c3: i2c@b8c000 { 2430 compatible = "qcom,geni-i2c"; 2431 reg = <0 0x00b8c000 0 0x4000>; 2432 2433 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2434 2435 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2436 clock-names = "se"; 2437 2438 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2439 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2441 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2442 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2444 interconnect-names = "qup-core", 2445 "qup-config", 2446 "qup-memory"; 2447 2448 power-domains = <&rpmhpd RPMHPD_CX>; 2449 required-opps = <&rpmhpd_opp_low_svs>; 2450 2451 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2452 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2453 dma-names = "tx", 2454 "rx"; 2455 2456 pinctrl-0 = <&qup_i2c3_data_clk>; 2457 pinctrl-names = "default"; 2458 2459 #address-cells = <1>; 2460 #size-cells = <0>; 2461 2462 status = "disabled"; 2463 }; 2464 2465 spi3: spi@b8c000 { 2466 compatible = "qcom,geni-spi"; 2467 reg = <0 0x00b8c000 0 0x4000>; 2468 2469 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2470 2471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2472 clock-names = "se"; 2473 2474 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2475 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2477 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2478 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2480 interconnect-names = "qup-core", 2481 "qup-config", 2482 "qup-memory"; 2483 2484 power-domains = <&rpmhpd RPMHPD_CX>; 2485 operating-points-v2 = <&qup_opp_table_100mhz>; 2486 2487 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2488 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2489 dma-names = "tx", 2490 "rx"; 2491 2492 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2493 pinctrl-names = "default"; 2494 2495 #address-cells = <1>; 2496 #size-cells = <0>; 2497 2498 status = "disabled"; 2499 }; 2500 2501 i2c4: i2c@b90000 { 2502 compatible = "qcom,geni-i2c"; 2503 reg = <0 0x00b90000 0 0x4000>; 2504 2505 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2506 2507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2508 clock-names = "se"; 2509 2510 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2511 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2512 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2513 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2514 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2515 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2516 interconnect-names = "qup-core", 2517 "qup-config", 2518 "qup-memory"; 2519 2520 power-domains = <&rpmhpd RPMHPD_CX>; 2521 required-opps = <&rpmhpd_opp_low_svs>; 2522 2523 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2524 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2525 dma-names = "tx", 2526 "rx"; 2527 2528 pinctrl-0 = <&qup_i2c4_data_clk>; 2529 pinctrl-names = "default"; 2530 2531 #address-cells = <1>; 2532 #size-cells = <0>; 2533 2534 status = "disabled"; 2535 }; 2536 2537 spi4: spi@b90000 { 2538 compatible = "qcom,geni-spi"; 2539 reg = <0 0x00b90000 0 0x4000>; 2540 2541 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2542 2543 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2544 clock-names = "se"; 2545 2546 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2547 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2548 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2549 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2550 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2551 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2552 interconnect-names = "qup-core", 2553 "qup-config", 2554 "qup-memory"; 2555 2556 power-domains = <&rpmhpd RPMHPD_CX>; 2557 operating-points-v2 = <&qup_opp_table_100mhz>; 2558 2559 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2560 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2561 dma-names = "tx", 2562 "rx"; 2563 2564 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2565 pinctrl-names = "default"; 2566 2567 #address-cells = <1>; 2568 #size-cells = <0>; 2569 2570 status = "disabled"; 2571 }; 2572 2573 i2c5: i2c@b94000 { 2574 compatible = "qcom,geni-i2c"; 2575 reg = <0 0x00b94000 0 0x4000>; 2576 2577 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2578 2579 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2580 clock-names = "se"; 2581 2582 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2583 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2584 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2585 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2586 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2587 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2588 interconnect-names = "qup-core", 2589 "qup-config", 2590 "qup-memory"; 2591 2592 power-domains = <&rpmhpd RPMHPD_CX>; 2593 required-opps = <&rpmhpd_opp_low_svs>; 2594 2595 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2596 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2597 dma-names = "tx", 2598 "rx"; 2599 2600 pinctrl-0 = <&qup_i2c5_data_clk>; 2601 pinctrl-names = "default"; 2602 2603 #address-cells = <1>; 2604 #size-cells = <0>; 2605 2606 status = "disabled"; 2607 }; 2608 2609 spi5: spi@b94000 { 2610 compatible = "qcom,geni-spi"; 2611 reg = <0 0x00b94000 0 0x4000>; 2612 2613 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2614 2615 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2616 clock-names = "se"; 2617 2618 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2619 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2621 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2622 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2623 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2624 interconnect-names = "qup-core", 2625 "qup-config", 2626 "qup-memory"; 2627 2628 power-domains = <&rpmhpd RPMHPD_CX>; 2629 operating-points-v2 = <&qup_opp_table_100mhz>; 2630 2631 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2632 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2633 dma-names = "tx", 2634 "rx"; 2635 2636 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2637 pinctrl-names = "default"; 2638 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 status = "disabled"; 2643 }; 2644 2645 i2c6: i2c@b98000 { 2646 compatible = "qcom,geni-i2c"; 2647 reg = <0 0x00b98000 0 0x4000>; 2648 2649 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2650 2651 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2652 clock-names = "se"; 2653 2654 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2655 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2657 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2658 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2660 interconnect-names = "qup-core", 2661 "qup-config", 2662 "qup-memory"; 2663 2664 power-domains = <&rpmhpd RPMHPD_CX>; 2665 required-opps = <&rpmhpd_opp_low_svs>; 2666 2667 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2668 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2669 dma-names = "tx", 2670 "rx"; 2671 2672 pinctrl-0 = <&qup_i2c6_data_clk>; 2673 pinctrl-names = "default"; 2674 2675 #address-cells = <1>; 2676 #size-cells = <0>; 2677 2678 status = "disabled"; 2679 }; 2680 2681 spi6: spi@b98000 { 2682 compatible = "qcom,geni-spi"; 2683 reg = <0 0x00b98000 0 0x4000>; 2684 2685 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2686 2687 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2688 clock-names = "se"; 2689 2690 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2691 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2692 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2693 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2694 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2696 interconnect-names = "qup-core", 2697 "qup-config", 2698 "qup-memory"; 2699 2700 power-domains = <&rpmhpd RPMHPD_CX>; 2701 operating-points-v2 = <&qup_opp_table_100mhz>; 2702 2703 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2704 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2705 dma-names = "tx", 2706 "rx"; 2707 2708 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2709 pinctrl-names = "default"; 2710 2711 #address-cells = <1>; 2712 #size-cells = <0>; 2713 2714 status = "disabled"; 2715 }; 2716 2717 i2c7: i2c@b9c000 { 2718 compatible = "qcom,geni-i2c"; 2719 reg = <0 0x00b9c000 0 0x4000>; 2720 2721 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2722 2723 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2724 clock-names = "se"; 2725 2726 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2727 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2728 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2729 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2730 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2732 interconnect-names = "qup-core", 2733 "qup-config", 2734 "qup-memory"; 2735 2736 power-domains = <&rpmhpd RPMHPD_CX>; 2737 required-opps = <&rpmhpd_opp_low_svs>; 2738 2739 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2740 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2741 dma-names = "tx", 2742 "rx"; 2743 2744 pinctrl-0 = <&qup_i2c7_data_clk>; 2745 pinctrl-names = "default"; 2746 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 2750 status = "disabled"; 2751 }; 2752 2753 spi7: spi@b9c000 { 2754 compatible = "qcom,geni-spi"; 2755 reg = <0 0x00b9c000 0 0x4000>; 2756 2757 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2758 2759 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2760 clock-names = "se"; 2761 2762 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2763 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2764 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2765 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2766 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2768 interconnect-names = "qup-core", 2769 "qup-config", 2770 "qup-memory"; 2771 2772 power-domains = <&rpmhpd RPMHPD_CX>; 2773 operating-points-v2 = <&qup_opp_table_100mhz>; 2774 2775 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2776 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2777 dma-names = "tx", 2778 "rx"; 2779 2780 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2781 pinctrl-names = "default"; 2782 2783 #address-cells = <1>; 2784 #size-cells = <0>; 2785 2786 status = "disabled"; 2787 }; 2788 }; 2789 2790 tsens0: thermal-sensor@c271000 { 2791 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2792 reg = <0 0x0c271000 0 0x1000>, 2793 <0 0x0c222000 0 0x1000>; 2794 2795 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2796 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2797 interrupt-names = "uplow", 2798 "critical"; 2799 2800 #qcom,sensors = <16>; 2801 2802 #thermal-sensor-cells = <1>; 2803 }; 2804 2805 tsens1: thermal-sensor@c272000 { 2806 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2807 reg = <0 0x0c272000 0 0x1000>, 2808 <0 0x0c223000 0 0x1000>; 2809 2810 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2811 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2812 interrupt-names = "uplow", 2813 "critical"; 2814 2815 #qcom,sensors = <16>; 2816 2817 #thermal-sensor-cells = <1>; 2818 }; 2819 2820 tsens2: thermal-sensor@c273000 { 2821 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2822 reg = <0 0x0c273000 0 0x1000>, 2823 <0 0x0c224000 0 0x1000>; 2824 2825 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2826 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2827 interrupt-names = "uplow", 2828 "critical"; 2829 2830 #qcom,sensors = <16>; 2831 2832 #thermal-sensor-cells = <1>; 2833 }; 2834 2835 tsens3: thermal-sensor@c274000 { 2836 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2837 reg = <0 0x0c274000 0 0x1000>, 2838 <0 0x0c225000 0 0x1000>; 2839 2840 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2841 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2842 interrupt-names = "uplow", 2843 "critical"; 2844 2845 #qcom,sensors = <16>; 2846 2847 #thermal-sensor-cells = <1>; 2848 }; 2849 2850 usb_1_ss0_hsphy: phy@fd3000 { 2851 compatible = "qcom,x1e80100-snps-eusb2-phy", 2852 "qcom,sm8550-snps-eusb2-phy"; 2853 reg = <0 0x00fd3000 0 0x154>; 2854 #phy-cells = <0>; 2855 2856 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2857 clock-names = "ref"; 2858 2859 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2860 2861 status = "disabled"; 2862 }; 2863 2864 usb_1_ss0_qmpphy: phy@fd5000 { 2865 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2866 reg = <0 0x00fd5000 0 0x4000>; 2867 2868 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2869 <&rpmhcc RPMH_CXO_CLK>, 2870 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2871 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2872 clock-names = "aux", 2873 "ref", 2874 "com_aux", 2875 "usb3_pipe"; 2876 2877 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2878 2879 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2880 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2881 reset-names = "phy", 2882 "common"; 2883 2884 #clock-cells = <1>; 2885 #phy-cells = <1>; 2886 2887 mode-switch; 2888 orientation-switch; 2889 2890 status = "disabled"; 2891 2892 ports { 2893 #address-cells = <1>; 2894 #size-cells = <0>; 2895 2896 port@0 { 2897 reg = <0>; 2898 2899 usb_1_ss0_qmpphy_out: endpoint { 2900 }; 2901 }; 2902 2903 port@1 { 2904 reg = <1>; 2905 2906 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2907 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2908 }; 2909 }; 2910 2911 port@2 { 2912 reg = <2>; 2913 2914 usb_1_ss0_qmpphy_dp_in: endpoint { 2915 remote-endpoint = <&mdss_dp0_out>; 2916 }; 2917 }; 2918 }; 2919 }; 2920 2921 usb_1_ss1_hsphy: phy@fd9000 { 2922 compatible = "qcom,x1e80100-snps-eusb2-phy", 2923 "qcom,sm8550-snps-eusb2-phy"; 2924 reg = <0 0x00fd9000 0 0x154>; 2925 #phy-cells = <0>; 2926 2927 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2928 clock-names = "ref"; 2929 2930 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2931 2932 status = "disabled"; 2933 }; 2934 2935 usb_1_ss1_qmpphy: phy@fda000 { 2936 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2937 reg = <0 0x00fda000 0 0x4000>; 2938 2939 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2940 <&rpmhcc RPMH_CXO_CLK>, 2941 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2942 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2943 clock-names = "aux", 2944 "ref", 2945 "com_aux", 2946 "usb3_pipe"; 2947 2948 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2949 2950 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2951 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2952 reset-names = "phy", 2953 "common"; 2954 2955 #clock-cells = <1>; 2956 #phy-cells = <1>; 2957 2958 mode-switch; 2959 orientation-switch; 2960 2961 status = "disabled"; 2962 2963 ports { 2964 #address-cells = <1>; 2965 #size-cells = <0>; 2966 2967 port@0 { 2968 reg = <0>; 2969 2970 usb_1_ss1_qmpphy_out: endpoint { 2971 }; 2972 }; 2973 2974 port@1 { 2975 reg = <1>; 2976 2977 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2978 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2979 }; 2980 }; 2981 2982 port@2 { 2983 reg = <2>; 2984 2985 usb_1_ss1_qmpphy_dp_in: endpoint { 2986 remote-endpoint = <&mdss_dp1_out>; 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 usb_1_ss2_hsphy: phy@fde000 { 2993 compatible = "qcom,x1e80100-snps-eusb2-phy", 2994 "qcom,sm8550-snps-eusb2-phy"; 2995 reg = <0 0x00fde000 0 0x154>; 2996 #phy-cells = <0>; 2997 2998 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2999 clock-names = "ref"; 3000 3001 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3002 3003 status = "disabled"; 3004 }; 3005 3006 usb_1_ss2_qmpphy: phy@fdf000 { 3007 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 3008 reg = <0 0x00fdf000 0 0x4000>; 3009 3010 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3011 <&rpmhcc RPMH_CXO_CLK>, 3012 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3013 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 3014 clock-names = "aux", 3015 "ref", 3016 "com_aux", 3017 "usb3_pipe"; 3018 3019 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3020 3021 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3022 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 3023 reset-names = "phy", 3024 "common"; 3025 3026 #clock-cells = <1>; 3027 #phy-cells = <1>; 3028 3029 mode-switch; 3030 orientation-switch; 3031 3032 status = "disabled"; 3033 3034 ports { 3035 #address-cells = <1>; 3036 #size-cells = <0>; 3037 3038 port@0 { 3039 reg = <0>; 3040 3041 usb_1_ss2_qmpphy_out: endpoint { 3042 }; 3043 }; 3044 3045 port@1 { 3046 reg = <1>; 3047 3048 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3049 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3050 }; 3051 }; 3052 3053 port@2 { 3054 reg = <2>; 3055 3056 usb_1_ss2_qmpphy_dp_in: endpoint { 3057 remote-endpoint = <&mdss_dp2_out>; 3058 }; 3059 }; 3060 }; 3061 }; 3062 3063 cnoc_main: interconnect@1500000 { 3064 compatible = "qcom,x1e80100-cnoc-main"; 3065 reg = <0 0x01500000 0 0x14400>; 3066 3067 qcom,bcm-voters = <&apps_bcm_voter>; 3068 3069 #interconnect-cells = <2>; 3070 }; 3071 3072 config_noc: interconnect@1600000 { 3073 compatible = "qcom,x1e80100-cnoc-cfg"; 3074 reg = <0 0x01600000 0 0x6600>; 3075 3076 qcom,bcm-voters = <&apps_bcm_voter>; 3077 3078 #interconnect-cells = <2>; 3079 }; 3080 3081 system_noc: interconnect@1680000 { 3082 compatible = "qcom,x1e80100-system-noc"; 3083 reg = <0 0x01680000 0 0x1c080>; 3084 3085 qcom,bcm-voters = <&apps_bcm_voter>; 3086 3087 #interconnect-cells = <2>; 3088 }; 3089 3090 pcie_south_anoc: interconnect@16c0000 { 3091 compatible = "qcom,x1e80100-pcie-south-anoc"; 3092 reg = <0 0x016c0000 0 0xd080>; 3093 3094 qcom,bcm-voters = <&apps_bcm_voter>; 3095 3096 #interconnect-cells = <2>; 3097 }; 3098 3099 pcie_center_anoc: interconnect@16d0000 { 3100 compatible = "qcom,x1e80100-pcie-center-anoc"; 3101 reg = <0 0x016d0000 0 0x7000>; 3102 3103 qcom,bcm-voters = <&apps_bcm_voter>; 3104 3105 #interconnect-cells = <2>; 3106 }; 3107 3108 aggre1_noc: interconnect@16e0000 { 3109 compatible = "qcom,x1e80100-aggre1-noc"; 3110 reg = <0 0x016e0000 0 0x14400>; 3111 3112 qcom,bcm-voters = <&apps_bcm_voter>; 3113 3114 #interconnect-cells = <2>; 3115 }; 3116 3117 aggre2_noc: interconnect@1700000 { 3118 compatible = "qcom,x1e80100-aggre2-noc"; 3119 reg = <0 0x01700000 0 0x1c400>; 3120 3121 qcom,bcm-voters = <&apps_bcm_voter>; 3122 3123 #interconnect-cells = <2>; 3124 }; 3125 3126 pcie_north_anoc: interconnect@1740000 { 3127 compatible = "qcom,x1e80100-pcie-north-anoc"; 3128 reg = <0 0x01740000 0 0x9080>; 3129 3130 qcom,bcm-voters = <&apps_bcm_voter>; 3131 3132 #interconnect-cells = <2>; 3133 }; 3134 3135 usb_center_anoc: interconnect@1750000 { 3136 compatible = "qcom,x1e80100-usb-center-anoc"; 3137 reg = <0 0x01750000 0 0x8800>; 3138 3139 qcom,bcm-voters = <&apps_bcm_voter>; 3140 3141 #interconnect-cells = <2>; 3142 }; 3143 3144 usb_north_anoc: interconnect@1760000 { 3145 compatible = "qcom,x1e80100-usb-north-anoc"; 3146 reg = <0 0x01760000 0 0x7080>; 3147 3148 qcom,bcm-voters = <&apps_bcm_voter>; 3149 3150 #interconnect-cells = <2>; 3151 }; 3152 3153 usb_south_anoc: interconnect@1770000 { 3154 compatible = "qcom,x1e80100-usb-south-anoc"; 3155 reg = <0 0x01770000 0 0xf080>; 3156 3157 qcom,bcm-voters = <&apps_bcm_voter>; 3158 3159 #interconnect-cells = <2>; 3160 }; 3161 3162 mmss_noc: interconnect@1780000 { 3163 compatible = "qcom,x1e80100-mmss-noc"; 3164 reg = <0 0x01780000 0 0x5B800>; 3165 3166 qcom,bcm-voters = <&apps_bcm_voter>; 3167 3168 #interconnect-cells = <2>; 3169 }; 3170 3171 pcie3: pcie@1bd0000 { 3172 device_type = "pci"; 3173 compatible = "qcom,pcie-x1e80100"; 3174 reg = <0x0 0x01bd0000 0x0 0x3000>, 3175 <0x0 0x78000000 0x0 0xf20>, 3176 <0x0 0x78000f40 0x0 0xa8>, 3177 <0x0 0x78001000 0x0 0x1000>, 3178 <0x0 0x78100000 0x0 0x100000>, 3179 <0x0 0x01bd3000 0x0 0x1000>; 3180 reg-names = "parf", 3181 "dbi", 3182 "elbi", 3183 "atu", 3184 "config", 3185 "mhi"; 3186 #address-cells = <3>; 3187 #size-cells = <2>; 3188 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3189 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3190 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3191 bus-range = <0x00 0xff>; 3192 3193 dma-coherent; 3194 3195 linux,pci-domain = <3>; 3196 num-lanes = <8>; 3197 3198 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3207 interrupt-names = "msi0", 3208 "msi1", 3209 "msi2", 3210 "msi3", 3211 "msi4", 3212 "msi5", 3213 "msi6", 3214 "msi7", 3215 "global"; 3216 3217 #interrupt-cells = <1>; 3218 interrupt-map-mask = <0 0 0 0x7>; 3219 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3220 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3221 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3222 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3223 3224 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3225 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3226 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3227 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3228 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3229 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3230 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3231 clock-names = "aux", 3232 "cfg", 3233 "bus_master", 3234 "bus_slave", 3235 "slave_q2a", 3236 "noc_aggr", 3237 "cnoc_sf_axi"; 3238 3239 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3240 assigned-clock-rates = <19200000>; 3241 3242 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3245 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3246 interconnect-names = "pcie-mem", 3247 "cpu-pcie"; 3248 3249 resets = <&gcc GCC_PCIE_3_BCR>, 3250 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3251 reset-names = "pci", 3252 "link_down"; 3253 3254 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3255 3256 phys = <&pcie3_phy>; 3257 phy-names = "pciephy"; 3258 3259 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3260 0x5555 0x5555 0x5555 0x5555>; 3261 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3262 3263 operating-points-v2 = <&pcie3_opp_table>; 3264 3265 status = "disabled"; 3266 3267 pcie3_opp_table: opp-table { 3268 compatible = "operating-points-v2"; 3269 3270 /* 2.5GT/s x1 */ 3271 opp-2500000-1 { 3272 opp-hz = /bits/ 64 <2500000>; 3273 required-opps = <&rpmhpd_opp_low_svs>; 3274 opp-peak-kBps = <250000 1>; 3275 opp-level = <1>; 3276 }; 3277 3278 /* 2.5 GT/s x2 */ 3279 opp-5000000-1 { 3280 opp-hz = /bits/ 64 <5000000>; 3281 required-opps = <&rpmhpd_opp_low_svs>; 3282 opp-peak-kBps = <500000 1>; 3283 opp-level = <1>; 3284 }; 3285 3286 /* 2.5 GT/s x4 */ 3287 opp-10000000-1 { 3288 opp-hz = /bits/ 64 <10000000>; 3289 required-opps = <&rpmhpd_opp_low_svs>; 3290 opp-peak-kBps = <1000000 1>; 3291 opp-level = <1>; 3292 }; 3293 3294 /* 2.5 GT/s x8 */ 3295 opp-20000000-1 { 3296 opp-hz = /bits/ 64 <20000000>; 3297 required-opps = <&rpmhpd_opp_low_svs>; 3298 opp-peak-kBps = <2000000 1>; 3299 opp-level = <1>; 3300 }; 3301 3302 /* 5 GT/s x1 */ 3303 opp-5000000-2 { 3304 opp-hz = /bits/ 64 <5000000>; 3305 required-opps = <&rpmhpd_opp_low_svs>; 3306 opp-peak-kBps = <500000 1>; 3307 opp-level = <2>; 3308 }; 3309 3310 /* 5 GT/s x2 */ 3311 opp-10000000-2 { 3312 opp-hz = /bits/ 64 <10000000>; 3313 required-opps = <&rpmhpd_opp_low_svs>; 3314 opp-peak-kBps = <1000000 1>; 3315 opp-level = <2>; 3316 }; 3317 3318 /* 5 GT/s x4 */ 3319 opp-20000000-2 { 3320 opp-hz = /bits/ 64 <20000000>; 3321 required-opps = <&rpmhpd_opp_low_svs>; 3322 opp-peak-kBps = <2000000 1>; 3323 opp-level = <2>; 3324 }; 3325 3326 /* 5 GT/s x8 */ 3327 opp-40000000-2 { 3328 opp-hz = /bits/ 64 <40000000>; 3329 required-opps = <&rpmhpd_opp_low_svs>; 3330 opp-peak-kBps = <4000000 1>; 3331 opp-level = <2>; 3332 }; 3333 3334 /* 8 GT/s x1 */ 3335 opp-8000000-3 { 3336 opp-hz = /bits/ 64 <8000000>; 3337 required-opps = <&rpmhpd_opp_svs>; 3338 opp-peak-kBps = <984500 1>; 3339 opp-level = <3>; 3340 }; 3341 3342 /* 8 GT/s x2 */ 3343 opp-16000000-3 { 3344 opp-hz = /bits/ 64 <16000000>; 3345 required-opps = <&rpmhpd_opp_svs>; 3346 opp-peak-kBps = <1969000 1>; 3347 opp-level = <3>; 3348 }; 3349 3350 /* 8 GT/s x4 */ 3351 opp-32000000-3 { 3352 opp-hz = /bits/ 64 <32000000>; 3353 required-opps = <&rpmhpd_opp_svs>; 3354 opp-peak-kBps = <3938000 1>; 3355 opp-level = <3>; 3356 }; 3357 3358 /* 8 GT/s x8 */ 3359 opp-64000000-3 { 3360 opp-hz = /bits/ 64 <64000000>; 3361 required-opps = <&rpmhpd_opp_svs>; 3362 opp-peak-kBps = <7876000 1>; 3363 opp-level = <3>; 3364 }; 3365 3366 /* 16 GT/s x1 */ 3367 opp-16000000-4 { 3368 opp-hz = /bits/ 64 <16000000>; 3369 required-opps = <&rpmhpd_opp_svs>; 3370 opp-peak-kBps = <1969000 1>; 3371 opp-level = <4>; 3372 }; 3373 3374 /* 16 GT/s x2 */ 3375 opp-32000000-4 { 3376 opp-hz = /bits/ 64 <32000000>; 3377 required-opps = <&rpmhpd_opp_svs>; 3378 opp-peak-kBps = <3938000 1>; 3379 opp-level = <4>; 3380 }; 3381 3382 /* 16 GT/s x4 */ 3383 opp-64000000-4 { 3384 opp-hz = /bits/ 64 <64000000>; 3385 required-opps = <&rpmhpd_opp_svs>; 3386 opp-peak-kBps = <7876000 1>; 3387 opp-level = <4>; 3388 }; 3389 3390 /* 16 GT/s x8 */ 3391 opp-128000000-4 { 3392 opp-hz = /bits/ 64 <128000000>; 3393 required-opps = <&rpmhpd_opp_svs>; 3394 opp-peak-kBps = <15753000 1>; 3395 opp-level = <4>; 3396 }; 3397 }; 3398 3399 pcie3_port: pcie@0 { 3400 device_type = "pci"; 3401 compatible = "pciclass,0604"; 3402 reg = <0x0 0x0 0x0 0x0 0x0>; 3403 bus-range = <0x01 0xff>; 3404 3405 #address-cells = <3>; 3406 #size-cells = <2>; 3407 ranges; 3408 }; 3409 }; 3410 3411 pcie3_phy: phy@1be0000 { 3412 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3413 reg = <0 0x01be0000 0 0x10000>; 3414 3415 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3416 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3417 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3418 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3419 <&gcc GCC_PCIE_3_PIPE_CLK>, 3420 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3421 clock-names = "aux", 3422 "cfg_ahb", 3423 "ref", 3424 "rchng", 3425 "pipe", 3426 "pipediv2"; 3427 3428 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3429 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3430 reset-names = "phy", 3431 "phy_nocsr"; 3432 3433 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3434 assigned-clock-rates = <100000000>; 3435 3436 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3437 3438 #clock-cells = <0>; 3439 clock-output-names = "pcie3_pipe_clk"; 3440 3441 #phy-cells = <0>; 3442 3443 status = "disabled"; 3444 }; 3445 3446 pcie6a: pci@1bf8000 { 3447 device_type = "pci"; 3448 compatible = "qcom,pcie-x1e80100"; 3449 reg = <0 0x01bf8000 0 0x3000>, 3450 <0 0x70000000 0 0xf20>, 3451 <0 0x70000f40 0 0xa8>, 3452 <0 0x70001000 0 0x1000>, 3453 <0 0x70100000 0 0x100000>, 3454 <0 0x01bfb000 0 0x1000>; 3455 reg-names = "parf", 3456 "dbi", 3457 "elbi", 3458 "atu", 3459 "config", 3460 "mhi"; 3461 #address-cells = <3>; 3462 #size-cells = <2>; 3463 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3464 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3465 bus-range = <0x00 0xff>; 3466 3467 dma-coherent; 3468 3469 linux,pci-domain = <6>; 3470 num-lanes = <4>; 3471 3472 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3473 3474 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3483 interrupt-names = "msi0", 3484 "msi1", 3485 "msi2", 3486 "msi3", 3487 "msi4", 3488 "msi5", 3489 "msi6", 3490 "msi7", 3491 "global"; 3492 3493 #interrupt-cells = <1>; 3494 interrupt-map-mask = <0 0 0 0x7>; 3495 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3496 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3497 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3498 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 3499 3500 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3501 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3502 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3503 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3504 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3505 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3506 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3507 clock-names = "aux", 3508 "cfg", 3509 "bus_master", 3510 "bus_slave", 3511 "slave_q2a", 3512 "noc_aggr", 3513 "cnoc_sf_axi"; 3514 3515 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3516 assigned-clock-rates = <19200000>; 3517 3518 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3519 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3521 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3522 interconnect-names = "pcie-mem", 3523 "cpu-pcie"; 3524 3525 resets = <&gcc GCC_PCIE_6A_BCR>, 3526 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3527 reset-names = "pci", 3528 "link_down"; 3529 3530 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3531 required-opps = <&rpmhpd_opp_nom>; 3532 3533 phys = <&pcie6a_phy>; 3534 phy-names = "pciephy"; 3535 3536 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3537 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3538 3539 status = "disabled"; 3540 }; 3541 3542 pcie6a_phy: phy@1bfc000 { 3543 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3544 reg = <0 0x01bfc000 0 0x2000>, 3545 <0 0x01bfe000 0 0x2000>; 3546 3547 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3548 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3549 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3550 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3551 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3552 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3553 clock-names = "aux", 3554 "cfg_ahb", 3555 "ref", 3556 "rchng", 3557 "pipe", 3558 "pipediv2"; 3559 3560 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3561 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3562 reset-names = "phy", 3563 "phy_nocsr"; 3564 3565 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3566 assigned-clock-rates = <100000000>; 3567 3568 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3569 3570 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3571 3572 #clock-cells = <0>; 3573 clock-output-names = "pcie6a_pipe_clk"; 3574 3575 #phy-cells = <0>; 3576 3577 status = "disabled"; 3578 }; 3579 3580 pcie5: pci@1c00000 { 3581 device_type = "pci"; 3582 compatible = "qcom,pcie-x1e80100"; 3583 reg = <0 0x01c00000 0 0x3000>, 3584 <0 0x7e000000 0 0xf1d>, 3585 <0 0x7e000f40 0 0xa8>, 3586 <0 0x7e001000 0 0x1000>, 3587 <0 0x7e100000 0 0x100000>, 3588 <0 0x01c03000 0 0x1000>; 3589 reg-names = "parf", 3590 "dbi", 3591 "elbi", 3592 "atu", 3593 "config", 3594 "mhi"; 3595 #address-cells = <3>; 3596 #size-cells = <2>; 3597 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3598 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3599 bus-range = <0x00 0xff>; 3600 3601 dma-coherent; 3602 3603 linux,pci-domain = <5>; 3604 num-lanes = <2>; 3605 3606 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3615 interrupt-names = "msi0", 3616 "msi1", 3617 "msi2", 3618 "msi3", 3619 "msi4", 3620 "msi5", 3621 "msi6", 3622 "msi7", 3623 "global"; 3624 3625 #interrupt-cells = <1>; 3626 interrupt-map-mask = <0 0 0 0x7>; 3627 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 3628 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 3629 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 3630 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 3631 3632 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3633 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3634 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3635 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3636 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3637 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3638 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3639 clock-names = "aux", 3640 "cfg", 3641 "bus_master", 3642 "bus_slave", 3643 "slave_q2a", 3644 "noc_aggr", 3645 "cnoc_sf_axi"; 3646 3647 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3648 assigned-clock-rates = <19200000>; 3649 3650 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3651 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3653 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3654 interconnect-names = "pcie-mem", 3655 "cpu-pcie"; 3656 3657 resets = <&gcc GCC_PCIE_5_BCR>, 3658 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3659 reset-names = "pci", 3660 "link_down"; 3661 3662 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3663 required-opps = <&rpmhpd_opp_nom>; 3664 3665 phys = <&pcie5_phy>; 3666 phy-names = "pciephy"; 3667 3668 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3669 3670 status = "disabled"; 3671 }; 3672 3673 pcie5_phy: phy@1c06000 { 3674 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3675 reg = <0 0x01c06000 0 0x2000>; 3676 3677 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3678 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3679 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3680 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3681 <&gcc GCC_PCIE_5_PIPE_CLK>, 3682 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3683 clock-names = "aux", 3684 "cfg_ahb", 3685 "ref", 3686 "rchng", 3687 "pipe", 3688 "pipediv2"; 3689 3690 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3691 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3692 reset-names = "phy", 3693 "phy_nocsr"; 3694 3695 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3696 assigned-clock-rates = <100000000>; 3697 3698 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3699 3700 #clock-cells = <0>; 3701 clock-output-names = "pcie5_pipe_clk"; 3702 3703 #phy-cells = <0>; 3704 3705 status = "disabled"; 3706 }; 3707 3708 pcie4: pci@1c08000 { 3709 device_type = "pci"; 3710 compatible = "qcom,pcie-x1e80100"; 3711 reg = <0 0x01c08000 0 0x3000>, 3712 <0 0x7c000000 0 0xf1d>, 3713 <0 0x7c000f40 0 0xa8>, 3714 <0 0x7c001000 0 0x1000>, 3715 <0 0x7c100000 0 0x100000>, 3716 <0 0x01c0b000 0 0x1000>; 3717 reg-names = "parf", 3718 "dbi", 3719 "elbi", 3720 "atu", 3721 "config", 3722 "mhi"; 3723 #address-cells = <3>; 3724 #size-cells = <2>; 3725 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3726 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3727 bus-range = <0x00 0xff>; 3728 3729 dma-coherent; 3730 3731 linux,pci-domain = <4>; 3732 num-lanes = <2>; 3733 3734 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3735 3736 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3745 interrupt-names = "msi0", 3746 "msi1", 3747 "msi2", 3748 "msi3", 3749 "msi4", 3750 "msi5", 3751 "msi6", 3752 "msi7", 3753 "global"; 3754 3755 #interrupt-cells = <1>; 3756 interrupt-map-mask = <0 0 0 0x7>; 3757 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3758 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3759 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3760 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 3761 3762 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3763 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3764 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3765 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3766 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3767 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3768 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3769 clock-names = "aux", 3770 "cfg", 3771 "bus_master", 3772 "bus_slave", 3773 "slave_q2a", 3774 "noc_aggr", 3775 "cnoc_sf_axi"; 3776 3777 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3778 assigned-clock-rates = <19200000>; 3779 3780 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3781 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3783 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3784 interconnect-names = "pcie-mem", 3785 "cpu-pcie"; 3786 3787 resets = <&gcc GCC_PCIE_4_BCR>, 3788 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3789 reset-names = "pci", 3790 "link_down"; 3791 3792 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3793 required-opps = <&rpmhpd_opp_nom>; 3794 3795 phys = <&pcie4_phy>; 3796 phy-names = "pciephy"; 3797 3798 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3799 3800 status = "disabled"; 3801 3802 pcie4_port0: pcie@0 { 3803 device_type = "pci"; 3804 reg = <0x0 0x0 0x0 0x0 0x0>; 3805 bus-range = <0x01 0xff>; 3806 3807 #address-cells = <3>; 3808 #size-cells = <2>; 3809 ranges; 3810 }; 3811 }; 3812 3813 pcie4_phy: phy@1c0e000 { 3814 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3815 reg = <0 0x01c0e000 0 0x2000>; 3816 3817 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3818 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3819 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3820 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3821 <&gcc GCC_PCIE_4_PIPE_CLK>, 3822 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3823 clock-names = "aux", 3824 "cfg_ahb", 3825 "ref", 3826 "rchng", 3827 "pipe", 3828 "pipediv2"; 3829 3830 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3831 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3832 reset-names = "phy", 3833 "phy_nocsr"; 3834 3835 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3836 assigned-clock-rates = <100000000>; 3837 3838 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3839 3840 #clock-cells = <0>; 3841 clock-output-names = "pcie4_pipe_clk"; 3842 3843 #phy-cells = <0>; 3844 3845 status = "disabled"; 3846 }; 3847 3848 tcsr_mutex: hwlock@1f40000 { 3849 compatible = "qcom,tcsr-mutex"; 3850 reg = <0 0x01f40000 0 0x20000>; 3851 #hwlock-cells = <1>; 3852 }; 3853 3854 tcsr: clock-controller@1fc0000 { 3855 compatible = "qcom,x1e80100-tcsr", "syscon"; 3856 reg = <0 0x01fc0000 0 0x30000>; 3857 clocks = <&rpmhcc RPMH_CXO_CLK>; 3858 #clock-cells = <1>; 3859 #reset-cells = <1>; 3860 }; 3861 3862 gpu: gpu@3d00000 { 3863 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3864 reg = <0x0 0x03d00000 0x0 0x40000>, 3865 <0x0 0x03d9e000 0x0 0x1000>, 3866 <0x0 0x03d61000 0x0 0x800>; 3867 3868 reg-names = "kgsl_3d0_reg_memory", 3869 "cx_mem", 3870 "cx_dbgc"; 3871 3872 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3873 3874 iommus = <&adreno_smmu 0 0x0>, 3875 <&adreno_smmu 1 0x0>; 3876 3877 operating-points-v2 = <&gpu_opp_table>; 3878 3879 qcom,gmu = <&gmu>; 3880 #cooling-cells = <2>; 3881 3882 nvmem-cells = <&gpu_speed_bin>; 3883 nvmem-cell-names = "speed_bin"; 3884 3885 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3886 interconnect-names = "gfx-mem"; 3887 3888 status = "disabled"; 3889 3890 gpu_zap_shader: zap-shader { 3891 memory-region = <&gpu_microcode_mem>; 3892 }; 3893 3894 gpu_opp_table: opp-table { 3895 compatible = "operating-points-v2-adreno", "operating-points-v2"; 3896 3897 opp-1500000000 { 3898 opp-hz = /bits/ 64 <1500000000>; 3899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 3900 opp-peak-kBps = <16500000>; 3901 qcom,opp-acd-level = <0xa82a5ffd>; 3902 opp-supported-hw = <0x03>; 3903 }; 3904 3905 opp-1375000000 { 3906 opp-hz = /bits/ 64 <1375000000>; 3907 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3908 opp-peak-kBps = <16500000>; 3909 qcom,opp-acd-level = <0xa82a5ffd>; 3910 opp-supported-hw = <0x03>; 3911 }; 3912 3913 opp-1250000000 { 3914 opp-hz = /bits/ 64 <1250000000>; 3915 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3916 opp-peak-kBps = <16500000>; 3917 qcom,opp-acd-level = <0xa82a5ffd>; 3918 opp-supported-hw = <0x07>; 3919 }; 3920 3921 opp-1175000000 { 3922 opp-hz = /bits/ 64 <1175000000>; 3923 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3924 opp-peak-kBps = <14398438>; 3925 qcom,opp-acd-level = <0xa82a5ffd>; 3926 opp-supported-hw = <0x07>; 3927 }; 3928 3929 opp-1100000000-0 { 3930 opp-hz = /bits/ 64 <1100000000>; 3931 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3932 opp-peak-kBps = <14398438>; 3933 qcom,opp-acd-level = <0xa82a5ffd>; 3934 opp-supported-hw = <0x07>; 3935 }; 3936 3937 /* Only applicable for SKUs which has 1100Mhz as Fmax */ 3938 opp-1100000000-1 { 3939 opp-hz = /bits/ 64 <1100000000>; 3940 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3941 opp-peak-kBps = <16500000>; 3942 qcom,opp-acd-level = <0xa82a5ffd>; 3943 opp-supported-hw = <0x08>; 3944 }; 3945 3946 opp-1000000000 { 3947 opp-hz = /bits/ 64 <1000000000>; 3948 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3949 opp-peak-kBps = <14398438>; 3950 qcom,opp-acd-level = <0xa82b5ffd>; 3951 opp-supported-hw = <0x0f>; 3952 }; 3953 3954 opp-925000000 { 3955 opp-hz = /bits/ 64 <925000000>; 3956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3957 opp-peak-kBps = <14398438>; 3958 qcom,opp-acd-level = <0xa82b5ffd>; 3959 opp-supported-hw = <0x0f>; 3960 }; 3961 3962 opp-800000000 { 3963 opp-hz = /bits/ 64 <800000000>; 3964 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3965 opp-peak-kBps = <12449219>; 3966 qcom,opp-acd-level = <0xa82c5ffd>; 3967 opp-supported-hw = <0x0f>; 3968 }; 3969 3970 opp-744000000 { 3971 opp-hz = /bits/ 64 <744000000>; 3972 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3973 opp-peak-kBps = <10687500>; 3974 qcom,opp-acd-level = <0x882e5ffd>; 3975 opp-supported-hw = <0x0f>; 3976 }; 3977 3978 opp-687000000-0 { 3979 opp-hz = /bits/ 64 <687000000>; 3980 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3981 opp-peak-kBps = <8171875>; 3982 qcom,opp-acd-level = <0x882e5ffd>; 3983 opp-supported-hw = <0x0f>; 3984 }; 3985 3986 /* Only applicable for SKUs which has 687Mhz as Fmax */ 3987 opp-687000000-1 { 3988 opp-hz = /bits/ 64 <687000000>; 3989 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3990 opp-peak-kBps = <16500000>; 3991 qcom,opp-acd-level = <0x882e5ffd>; 3992 opp-supported-hw = <0x10>; 3993 }; 3994 3995 opp-550000000 { 3996 opp-hz = /bits/ 64 <550000000>; 3997 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3998 opp-peak-kBps = <6074219>; 3999 qcom,opp-acd-level = <0xc0285ffd>; 4000 opp-supported-hw = <0x1f>; 4001 }; 4002 4003 opp-390000000 { 4004 opp-hz = /bits/ 64 <390000000>; 4005 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4006 opp-peak-kBps = <3000000>; 4007 qcom,opp-acd-level = <0xc0285ffd>; 4008 opp-supported-hw = <0x1f>; 4009 }; 4010 4011 opp-300000000 { 4012 opp-hz = /bits/ 64 <300000000>; 4013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4014 opp-peak-kBps = <2136719>; 4015 qcom,opp-acd-level = <0xc02b5ffd>; 4016 opp-supported-hw = <0x1f>; 4017 }; 4018 }; 4019 }; 4020 4021 gmu: gmu@3d6a000 { 4022 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 4023 reg = <0x0 0x03d6a000 0x0 0x35000>, 4024 <0x0 0x03d50000 0x0 0x10000>, 4025 <0x0 0x0b280000 0x0 0x10000>; 4026 reg-names = "gmu", "rscc", "gmu_pdc"; 4027 4028 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4030 interrupt-names = "hfi", "gmu"; 4031 4032 clocks = <&gpucc GPU_CC_AHB_CLK>, 4033 <&gpucc GPU_CC_CX_GMU_CLK>, 4034 <&gpucc GPU_CC_CXO_CLK>, 4035 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4036 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4037 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4038 <&gpucc GPU_CC_DEMET_CLK>; 4039 clock-names = "ahb", 4040 "gmu", 4041 "cxo", 4042 "axi", 4043 "memnoc", 4044 "hub", 4045 "demet"; 4046 4047 power-domains = <&gpucc GPU_CX_GDSC>, 4048 <&gpucc GPU_GX_GDSC>; 4049 power-domain-names = "cx", 4050 "gx"; 4051 4052 iommus = <&adreno_smmu 5 0x0>; 4053 4054 qcom,qmp = <&aoss_qmp>; 4055 4056 operating-points-v2 = <&gmu_opp_table>; 4057 4058 gmu_opp_table: opp-table { 4059 compatible = "operating-points-v2"; 4060 4061 opp-550000000 { 4062 opp-hz = /bits/ 64 <550000000>; 4063 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4064 }; 4065 4066 opp-220000000 { 4067 opp-hz = /bits/ 64 <220000000>; 4068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4069 }; 4070 }; 4071 }; 4072 4073 gpucc: clock-controller@3d90000 { 4074 compatible = "qcom,x1e80100-gpucc"; 4075 reg = <0 0x03d90000 0 0xa000>; 4076 clocks = <&bi_tcxo_div2>, 4077 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 4078 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 4079 #clock-cells = <1>; 4080 #reset-cells = <1>; 4081 #power-domain-cells = <1>; 4082 }; 4083 4084 adreno_smmu: iommu@3da0000 { 4085 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 4086 "qcom,smmu-500", "arm,mmu-500"; 4087 reg = <0x0 0x03da0000 0x0 0x40000>; 4088 #iommu-cells = <2>; 4089 #global-interrupts = <1>; 4090 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4116 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4117 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4118 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4119 <&gpucc GPU_CC_AHB_CLK>; 4120 clock-names = "hlos", 4121 "bus", 4122 "iface", 4123 "ahb"; 4124 power-domains = <&gpucc GPU_CX_GDSC>; 4125 dma-coherent; 4126 }; 4127 4128 gem_noc: interconnect@26400000 { 4129 compatible = "qcom,x1e80100-gem-noc"; 4130 reg = <0 0x26400000 0 0x311200>; 4131 4132 qcom,bcm-voters = <&apps_bcm_voter>; 4133 4134 #interconnect-cells = <2>; 4135 }; 4136 4137 nsp_noc: interconnect@320c0000 { 4138 compatible = "qcom,x1e80100-nsp-noc"; 4139 reg = <0 0x320C0000 0 0xe080>; 4140 4141 qcom,bcm-voters = <&apps_bcm_voter>; 4142 4143 #interconnect-cells = <2>; 4144 }; 4145 4146 remoteproc_adsp: remoteproc@6800000 { 4147 compatible = "qcom,x1e80100-adsp-pas"; 4148 reg = <0x0 0x06800000 0x0 0x10000>; 4149 4150 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4151 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4152 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4153 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4154 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4155 interrupt-names = "wdog", 4156 "fatal", 4157 "ready", 4158 "handover", 4159 "stop-ack"; 4160 4161 clocks = <&rpmhcc RPMH_CXO_CLK>; 4162 clock-names = "xo"; 4163 4164 power-domains = <&rpmhpd RPMHPD_LCX>, 4165 <&rpmhpd RPMHPD_LMX>; 4166 power-domain-names = "lcx", 4167 "lmx"; 4168 4169 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4171 4172 memory-region = <&adspslpi_mem>, 4173 <&q6_adsp_dtb_mem>; 4174 4175 qcom,qmp = <&aoss_qmp>; 4176 4177 qcom,smem-states = <&smp2p_adsp_out 0>; 4178 qcom,smem-state-names = "stop"; 4179 4180 status = "disabled"; 4181 4182 glink-edge { 4183 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4184 IPCC_MPROC_SIGNAL_GLINK_QMP 4185 IRQ_TYPE_EDGE_RISING>; 4186 mboxes = <&ipcc IPCC_CLIENT_LPASS 4187 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4188 4189 label = "lpass"; 4190 qcom,remote-pid = <2>; 4191 4192 fastrpc { 4193 compatible = "qcom,fastrpc"; 4194 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4195 label = "adsp"; 4196 qcom,non-secure-domain; 4197 #address-cells = <1>; 4198 #size-cells = <0>; 4199 4200 compute-cb@3 { 4201 compatible = "qcom,fastrpc-compute-cb"; 4202 reg = <3>; 4203 iommus = <&apps_smmu 0x1003 0x80>, 4204 <&apps_smmu 0x1063 0x0>; 4205 dma-coherent; 4206 }; 4207 4208 compute-cb@4 { 4209 compatible = "qcom,fastrpc-compute-cb"; 4210 reg = <4>; 4211 iommus = <&apps_smmu 0x1004 0x80>, 4212 <&apps_smmu 0x1064 0x0>; 4213 dma-coherent; 4214 }; 4215 4216 compute-cb@5 { 4217 compatible = "qcom,fastrpc-compute-cb"; 4218 reg = <5>; 4219 iommus = <&apps_smmu 0x1005 0x80>, 4220 <&apps_smmu 0x1065 0x0>; 4221 dma-coherent; 4222 }; 4223 4224 compute-cb@6 { 4225 compatible = "qcom,fastrpc-compute-cb"; 4226 reg = <6>; 4227 iommus = <&apps_smmu 0x1006 0x80>, 4228 <&apps_smmu 0x1066 0x0>; 4229 dma-coherent; 4230 }; 4231 4232 compute-cb@7 { 4233 compatible = "qcom,fastrpc-compute-cb"; 4234 reg = <7>; 4235 iommus = <&apps_smmu 0x1007 0x80>, 4236 <&apps_smmu 0x1067 0x0>; 4237 dma-coherent; 4238 }; 4239 }; 4240 4241 gpr { 4242 compatible = "qcom,gpr"; 4243 qcom,glink-channels = "adsp_apps"; 4244 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4245 qcom,intents = <512 20>; 4246 #address-cells = <1>; 4247 #size-cells = <0>; 4248 4249 q6apm: service@1 { 4250 compatible = "qcom,q6apm"; 4251 reg = <GPR_APM_MODULE_IID>; 4252 #sound-dai-cells = <0>; 4253 qcom,protection-domain = "avs/audio", 4254 "msm/adsp/audio_pd"; 4255 4256 q6apmbedai: bedais { 4257 compatible = "qcom,q6apm-lpass-dais"; 4258 #sound-dai-cells = <1>; 4259 }; 4260 4261 q6apmdai: dais { 4262 compatible = "qcom,q6apm-dais"; 4263 iommus = <&apps_smmu 0x1001 0x80>, 4264 <&apps_smmu 0x1061 0x0>; 4265 }; 4266 }; 4267 4268 q6prm: service@2 { 4269 compatible = "qcom,q6prm"; 4270 reg = <GPR_PRM_MODULE_IID>; 4271 qcom,protection-domain = "avs/audio", 4272 "msm/adsp/audio_pd"; 4273 4274 q6prmcc: clock-controller { 4275 compatible = "qcom,q6prm-lpass-clocks"; 4276 #clock-cells = <2>; 4277 }; 4278 }; 4279 }; 4280 }; 4281 }; 4282 4283 lpass_wsa2macro: codec@6aa0000 { 4284 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4285 reg = <0 0x06aa0000 0 0x1000>; 4286 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4287 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4288 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4289 <&lpass_vamacro>; 4290 clock-names = "mclk", 4291 "macro", 4292 "dcodec", 4293 "fsgen"; 4294 4295 #clock-cells = <0>; 4296 clock-output-names = "wsa2-mclk"; 4297 #sound-dai-cells = <1>; 4298 sound-name-prefix = "WSA2"; 4299 }; 4300 4301 swr3: soundwire@6ab0000 { 4302 compatible = "qcom,soundwire-v2.0.0"; 4303 reg = <0 0x06ab0000 0 0x10000>; 4304 clocks = <&lpass_wsa2macro>; 4305 clock-names = "iface"; 4306 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4307 label = "WSA2"; 4308 4309 pinctrl-0 = <&wsa2_swr_active>; 4310 pinctrl-names = "default"; 4311 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4312 reset-names = "swr_audio_cgcr"; 4313 4314 qcom,din-ports = <4>; 4315 qcom,dout-ports = <9>; 4316 4317 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4318 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4319 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4320 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4321 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4322 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4323 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4324 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4325 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4326 4327 #address-cells = <2>; 4328 #size-cells = <0>; 4329 #sound-dai-cells = <1>; 4330 status = "disabled"; 4331 }; 4332 4333 lpass_rxmacro: codec@6ac0000 { 4334 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4335 reg = <0 0x06ac0000 0 0x1000>; 4336 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4337 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4338 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4339 <&lpass_vamacro>; 4340 clock-names = "mclk", 4341 "macro", 4342 "dcodec", 4343 "fsgen"; 4344 4345 #clock-cells = <0>; 4346 clock-output-names = "mclk"; 4347 #sound-dai-cells = <1>; 4348 }; 4349 4350 swr1: soundwire@6ad0000 { 4351 compatible = "qcom,soundwire-v2.0.0"; 4352 reg = <0 0x06ad0000 0 0x10000>; 4353 clocks = <&lpass_rxmacro>; 4354 clock-names = "iface"; 4355 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4356 label = "RX"; 4357 4358 pinctrl-0 = <&rx_swr_active>; 4359 pinctrl-names = "default"; 4360 4361 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4362 reset-names = "swr_audio_cgcr"; 4363 qcom,din-ports = <1>; 4364 qcom,dout-ports = <11>; 4365 4366 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4367 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4368 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4369 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4370 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4371 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4372 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4373 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4374 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4375 4376 #address-cells = <2>; 4377 #size-cells = <0>; 4378 #sound-dai-cells = <1>; 4379 status = "disabled"; 4380 }; 4381 4382 lpass_txmacro: codec@6ae0000 { 4383 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4384 reg = <0 0x06ae0000 0 0x1000>; 4385 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4386 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4387 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4388 <&lpass_vamacro>; 4389 clock-names = "mclk", 4390 "macro", 4391 "dcodec", 4392 "fsgen"; 4393 4394 #clock-cells = <0>; 4395 clock-output-names = "mclk"; 4396 #sound-dai-cells = <1>; 4397 }; 4398 4399 lpass_wsamacro: codec@6b00000 { 4400 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4401 reg = <0 0x06b00000 0 0x1000>; 4402 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4403 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4404 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4405 <&lpass_vamacro>; 4406 clock-names = "mclk", 4407 "macro", 4408 "dcodec", 4409 "fsgen"; 4410 4411 #clock-cells = <0>; 4412 clock-output-names = "mclk"; 4413 #sound-dai-cells = <1>; 4414 sound-name-prefix = "WSA"; 4415 }; 4416 4417 swr0: soundwire@6b10000 { 4418 compatible = "qcom,soundwire-v2.0.0"; 4419 reg = <0 0x06b10000 0 0x10000>; 4420 clocks = <&lpass_wsamacro>; 4421 clock-names = "iface"; 4422 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4423 label = "WSA"; 4424 4425 pinctrl-0 = <&wsa_swr_active>; 4426 pinctrl-names = "default"; 4427 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4428 reset-names = "swr_audio_cgcr"; 4429 4430 qcom,din-ports = <4>; 4431 qcom,dout-ports = <9>; 4432 4433 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4434 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4435 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4436 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4437 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4438 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4439 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4440 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4441 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4442 4443 #address-cells = <2>; 4444 #size-cells = <0>; 4445 #sound-dai-cells = <1>; 4446 status = "disabled"; 4447 }; 4448 4449 lpass_audiocc: clock-controller@6b6c000 { 4450 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4451 reg = <0 0x06b6c000 0 0x1000>; 4452 #clock-cells = <1>; 4453 #reset-cells = <1>; 4454 }; 4455 4456 swr2: soundwire@6d30000 { 4457 compatible = "qcom,soundwire-v2.0.0"; 4458 reg = <0 0x06d30000 0 0x10000>; 4459 clocks = <&lpass_txmacro>; 4460 clock-names = "iface"; 4461 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4462 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4463 interrupt-names = "core", "wakeup"; 4464 label = "TX"; 4465 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4466 reset-names = "swr_audio_cgcr"; 4467 4468 pinctrl-0 = <&tx_swr_active>; 4469 pinctrl-names = "default"; 4470 4471 qcom,din-ports = <4>; 4472 qcom,dout-ports = <1>; 4473 4474 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4475 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4476 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4477 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4478 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4479 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4480 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4481 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4482 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4483 4484 #address-cells = <2>; 4485 #size-cells = <0>; 4486 #sound-dai-cells = <1>; 4487 status = "disabled"; 4488 }; 4489 4490 lpass_vamacro: codec@6d44000 { 4491 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4492 reg = <0 0x06d44000 0 0x1000>; 4493 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4494 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4495 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4496 clock-names = "mclk", 4497 "macro", 4498 "dcodec"; 4499 4500 #clock-cells = <0>; 4501 clock-output-names = "fsgen"; 4502 #sound-dai-cells = <1>; 4503 }; 4504 4505 lpass_tlmm: pinctrl@6e80000 { 4506 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4507 reg = <0 0x06e80000 0 0x20000>, 4508 <0 0x07250000 0 0x10000>; 4509 4510 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4511 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4512 clock-names = "core", "audio"; 4513 4514 gpio-controller; 4515 #gpio-cells = <2>; 4516 gpio-ranges = <&lpass_tlmm 0 0 23>; 4517 4518 tx_swr_active: tx-swr-active-state { 4519 clk-pins { 4520 pins = "gpio0"; 4521 function = "swr_tx_clk"; 4522 drive-strength = <2>; 4523 slew-rate = <1>; 4524 bias-disable; 4525 }; 4526 4527 data-pins { 4528 pins = "gpio1", "gpio2"; 4529 function = "swr_tx_data"; 4530 drive-strength = <2>; 4531 slew-rate = <1>; 4532 bias-bus-hold; 4533 }; 4534 }; 4535 4536 rx_swr_active: rx-swr-active-state { 4537 clk-pins { 4538 pins = "gpio3"; 4539 function = "swr_rx_clk"; 4540 drive-strength = <2>; 4541 slew-rate = <1>; 4542 bias-disable; 4543 }; 4544 4545 data-pins { 4546 pins = "gpio4", "gpio5"; 4547 function = "swr_rx_data"; 4548 drive-strength = <2>; 4549 slew-rate = <1>; 4550 bias-bus-hold; 4551 }; 4552 }; 4553 4554 dmic01_default: dmic01-default-state { 4555 clk-pins { 4556 pins = "gpio6"; 4557 function = "dmic1_clk"; 4558 drive-strength = <8>; 4559 output-high; 4560 }; 4561 4562 data-pins { 4563 pins = "gpio7"; 4564 function = "dmic1_data"; 4565 drive-strength = <8>; 4566 input-enable; 4567 }; 4568 }; 4569 4570 dmic23_default: dmic23-default-state { 4571 clk-pins { 4572 pins = "gpio8"; 4573 function = "dmic2_clk"; 4574 drive-strength = <8>; 4575 output-high; 4576 }; 4577 4578 data-pins { 4579 pins = "gpio9"; 4580 function = "dmic2_data"; 4581 drive-strength = <8>; 4582 input-enable; 4583 }; 4584 }; 4585 4586 wsa_swr_active: wsa-swr-active-state { 4587 clk-pins { 4588 pins = "gpio10"; 4589 function = "wsa_swr_clk"; 4590 drive-strength = <2>; 4591 slew-rate = <1>; 4592 bias-disable; 4593 }; 4594 4595 data-pins { 4596 pins = "gpio11"; 4597 function = "wsa_swr_data"; 4598 drive-strength = <2>; 4599 slew-rate = <1>; 4600 bias-bus-hold; 4601 }; 4602 }; 4603 4604 wsa2_swr_active: wsa2-swr-active-state { 4605 clk-pins { 4606 pins = "gpio15"; 4607 function = "wsa2_swr_clk"; 4608 drive-strength = <2>; 4609 slew-rate = <1>; 4610 bias-disable; 4611 }; 4612 4613 data-pins { 4614 pins = "gpio16"; 4615 function = "wsa2_swr_data"; 4616 drive-strength = <2>; 4617 slew-rate = <1>; 4618 bias-bus-hold; 4619 }; 4620 }; 4621 }; 4622 4623 lpasscc: clock-controller@6ea0000 { 4624 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4625 reg = <0 0x06ea0000 0 0x12000>; 4626 #clock-cells = <1>; 4627 #reset-cells = <1>; 4628 }; 4629 4630 lpass_ag_noc: interconnect@7e40000 { 4631 compatible = "qcom,x1e80100-lpass-ag-noc"; 4632 reg = <0 0x07e40000 0 0xe080>; 4633 4634 qcom,bcm-voters = <&apps_bcm_voter>; 4635 4636 #interconnect-cells = <2>; 4637 }; 4638 4639 lpass_lpiaon_noc: interconnect@7400000 { 4640 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4641 reg = <0 0x07400000 0 0x19080>; 4642 4643 qcom,bcm-voters = <&apps_bcm_voter>; 4644 4645 #interconnect-cells = <2>; 4646 }; 4647 4648 lpass_lpicx_noc: interconnect@7430000 { 4649 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4650 reg = <0 0x07430000 0 0x3A200>; 4651 4652 qcom,bcm-voters = <&apps_bcm_voter>; 4653 4654 #interconnect-cells = <2>; 4655 }; 4656 4657 sdhc_2: mmc@8804000 { 4658 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4659 reg = <0 0x08804000 0 0x1000>; 4660 4661 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4663 interrupt-names = "hc_irq", "pwr_irq"; 4664 4665 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4666 <&gcc GCC_SDCC2_APPS_CLK>, 4667 <&rpmhcc RPMH_CXO_CLK>; 4668 clock-names = "iface", "core", "xo"; 4669 iommus = <&apps_smmu 0x520 0>; 4670 qcom,dll-config = <0x0007642c>; 4671 qcom,ddr-config = <0x80040868>; 4672 power-domains = <&rpmhpd RPMHPD_CX>; 4673 operating-points-v2 = <&sdhc2_opp_table>; 4674 4675 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4676 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4678 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4679 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4680 bus-width = <4>; 4681 dma-coherent; 4682 4683 status = "disabled"; 4684 4685 sdhc2_opp_table: opp-table { 4686 compatible = "operating-points-v2"; 4687 4688 opp-19200000 { 4689 opp-hz = /bits/ 64 <19200000>; 4690 required-opps = <&rpmhpd_opp_min_svs>; 4691 }; 4692 4693 opp-50000000 { 4694 opp-hz = /bits/ 64 <50000000>; 4695 required-opps = <&rpmhpd_opp_low_svs>; 4696 }; 4697 4698 opp-100000000 { 4699 opp-hz = /bits/ 64 <100000000>; 4700 required-opps = <&rpmhpd_opp_svs>; 4701 }; 4702 4703 opp-202000000 { 4704 opp-hz = /bits/ 64 <202000000>; 4705 required-opps = <&rpmhpd_opp_svs_l1>; 4706 }; 4707 }; 4708 }; 4709 4710 sdhc_4: mmc@8844000 { 4711 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4712 reg = <0 0x08844000 0 0x1000>; 4713 4714 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4716 interrupt-names = "hc_irq", "pwr_irq"; 4717 4718 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4719 <&gcc GCC_SDCC4_APPS_CLK>, 4720 <&rpmhcc RPMH_CXO_CLK>; 4721 clock-names = "iface", "core", "xo"; 4722 iommus = <&apps_smmu 0x160 0>; 4723 qcom,dll-config = <0x0007642c>; 4724 qcom,ddr-config = <0x80040868>; 4725 power-domains = <&rpmhpd RPMHPD_CX>; 4726 operating-points-v2 = <&sdhc4_opp_table>; 4727 4728 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4729 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4730 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4731 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4732 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4733 bus-width = <4>; 4734 dma-coherent; 4735 4736 status = "disabled"; 4737 4738 sdhc4_opp_table: opp-table { 4739 compatible = "operating-points-v2"; 4740 4741 opp-19200000 { 4742 opp-hz = /bits/ 64 <19200000>; 4743 required-opps = <&rpmhpd_opp_min_svs>; 4744 }; 4745 4746 opp-50000000 { 4747 opp-hz = /bits/ 64 <50000000>; 4748 required-opps = <&rpmhpd_opp_low_svs>; 4749 }; 4750 4751 opp-100000000 { 4752 opp-hz = /bits/ 64 <100000000>; 4753 required-opps = <&rpmhpd_opp_svs>; 4754 }; 4755 4756 opp-202000000 { 4757 opp-hz = /bits/ 64 <202000000>; 4758 required-opps = <&rpmhpd_opp_svs_l1>; 4759 }; 4760 }; 4761 }; 4762 4763 usb_2_hsphy: phy@88e0000 { 4764 compatible = "qcom,x1e80100-snps-eusb2-phy", 4765 "qcom,sm8550-snps-eusb2-phy"; 4766 reg = <0 0x088e0000 0 0x154>; 4767 #phy-cells = <0>; 4768 4769 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4770 clock-names = "ref"; 4771 4772 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4773 4774 status = "disabled"; 4775 }; 4776 4777 usb_mp_hsphy0: phy@88e1000 { 4778 compatible = "qcom,x1e80100-snps-eusb2-phy", 4779 "qcom,sm8550-snps-eusb2-phy"; 4780 reg = <0 0x088e1000 0 0x154>; 4781 #phy-cells = <0>; 4782 4783 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4784 clock-names = "ref"; 4785 4786 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4787 4788 status = "disabled"; 4789 }; 4790 4791 usb_mp_hsphy1: phy@88e2000 { 4792 compatible = "qcom,x1e80100-snps-eusb2-phy", 4793 "qcom,sm8550-snps-eusb2-phy"; 4794 reg = <0 0x088e2000 0 0x154>; 4795 #phy-cells = <0>; 4796 4797 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4798 clock-names = "ref"; 4799 4800 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4801 4802 status = "disabled"; 4803 }; 4804 4805 usb_mp_qmpphy0: phy@88e3000 { 4806 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4807 reg = <0 0x088e3000 0 0x2000>; 4808 4809 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4810 <&rpmhcc RPMH_CXO_CLK>, 4811 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4812 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4813 clock-names = "aux", 4814 "ref", 4815 "com_aux", 4816 "pipe"; 4817 4818 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4819 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4820 reset-names = "phy", 4821 "phy_phy"; 4822 4823 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4824 4825 #clock-cells = <0>; 4826 clock-output-names = "usb_mp_phy0_pipe_clk"; 4827 4828 #phy-cells = <0>; 4829 4830 status = "disabled"; 4831 }; 4832 4833 usb_mp_qmpphy1: phy@88e5000 { 4834 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4835 reg = <0 0x088e5000 0 0x2000>; 4836 4837 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4838 <&rpmhcc RPMH_CXO_CLK>, 4839 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4840 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4841 clock-names = "aux", 4842 "ref", 4843 "com_aux", 4844 "pipe"; 4845 4846 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4847 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4848 reset-names = "phy", 4849 "phy_phy"; 4850 4851 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4852 4853 #clock-cells = <0>; 4854 clock-output-names = "usb_mp_phy1_pipe_clk"; 4855 4856 #phy-cells = <0>; 4857 4858 status = "disabled"; 4859 }; 4860 4861 usb_1_ss2: usb@a0f8800 { 4862 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4863 reg = <0 0x0a0f8800 0 0x400>; 4864 4865 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4866 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4867 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4868 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4869 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4870 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4871 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4872 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4873 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4874 clock-names = "cfg_noc", 4875 "core", 4876 "iface", 4877 "sleep", 4878 "mock_utmi", 4879 "noc_aggr", 4880 "noc_aggr_north", 4881 "noc_aggr_south", 4882 "noc_sys"; 4883 4884 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4885 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4886 assigned-clock-rates = <19200000>, 4887 <200000000>; 4888 4889 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4890 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4891 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4892 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4893 interrupt-names = "pwr_event", 4894 "dp_hs_phy_irq", 4895 "dm_hs_phy_irq", 4896 "ss_phy_irq"; 4897 4898 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4899 required-opps = <&rpmhpd_opp_nom>; 4900 4901 resets = <&gcc GCC_USB30_TERT_BCR>; 4902 4903 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4905 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4906 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4907 interconnect-names = "usb-ddr", 4908 "apps-usb"; 4909 4910 wakeup-source; 4911 4912 #address-cells = <2>; 4913 #size-cells = <2>; 4914 ranges; 4915 4916 status = "disabled"; 4917 4918 usb_1_ss2_dwc3: usb@a000000 { 4919 compatible = "snps,dwc3"; 4920 reg = <0 0x0a000000 0 0xcd00>; 4921 4922 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4923 4924 iommus = <&apps_smmu 0x14a0 0x0>; 4925 4926 phys = <&usb_1_ss2_hsphy>, 4927 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4928 phy-names = "usb2-phy", 4929 "usb3-phy"; 4930 4931 snps,dis_u2_susphy_quirk; 4932 snps,dis_enblslpm_quirk; 4933 snps,usb3_lpm_capable; 4934 snps,dis-u1-entry-quirk; 4935 snps,dis-u2-entry-quirk; 4936 4937 dma-coherent; 4938 4939 ports { 4940 #address-cells = <1>; 4941 #size-cells = <0>; 4942 4943 port@0 { 4944 reg = <0>; 4945 4946 usb_1_ss2_dwc3_hs: endpoint { 4947 }; 4948 }; 4949 4950 port@1 { 4951 reg = <1>; 4952 4953 usb_1_ss2_dwc3_ss: endpoint { 4954 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4955 }; 4956 }; 4957 }; 4958 }; 4959 }; 4960 4961 usb_2: usb@a2f8800 { 4962 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4963 reg = <0 0x0a2f8800 0 0x400>; 4964 #address-cells = <2>; 4965 #size-cells = <2>; 4966 ranges; 4967 4968 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4969 <&gcc GCC_USB20_MASTER_CLK>, 4970 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4971 <&gcc GCC_USB20_SLEEP_CLK>, 4972 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4973 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4974 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4975 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4976 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4977 clock-names = "cfg_noc", 4978 "core", 4979 "iface", 4980 "sleep", 4981 "mock_utmi", 4982 "noc_aggr", 4983 "noc_aggr_north", 4984 "noc_aggr_south", 4985 "noc_sys"; 4986 4987 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4988 <&gcc GCC_USB20_MASTER_CLK>; 4989 assigned-clock-rates = <19200000>, <200000000>; 4990 4991 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4992 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4993 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4994 interrupt-names = "pwr_event", 4995 "dp_hs_phy_irq", 4996 "dm_hs_phy_irq"; 4997 4998 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4999 required-opps = <&rpmhpd_opp_nom>; 5000 5001 resets = <&gcc GCC_USB20_PRIM_BCR>; 5002 5003 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5004 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5005 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5006 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5007 interconnect-names = "usb-ddr", 5008 "apps-usb"; 5009 5010 qcom,select-utmi-as-pipe-clk; 5011 wakeup-source; 5012 5013 status = "disabled"; 5014 5015 usb_2_dwc3: usb@a200000 { 5016 compatible = "snps,dwc3"; 5017 reg = <0 0x0a200000 0 0xcd00>; 5018 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 5019 iommus = <&apps_smmu 0x14e0 0x0>; 5020 phys = <&usb_2_hsphy>; 5021 phy-names = "usb2-phy"; 5022 maximum-speed = "high-speed"; 5023 snps,dis-u1-entry-quirk; 5024 snps,dis-u2-entry-quirk; 5025 5026 dma-coherent; 5027 5028 port { 5029 usb_2_dwc3_hs: endpoint { 5030 }; 5031 }; 5032 }; 5033 }; 5034 5035 usb_mp: usb@a4f8800 { 5036 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 5037 reg = <0 0x0a4f8800 0 0x400>; 5038 5039 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 5040 <&gcc GCC_USB30_MP_MASTER_CLK>, 5041 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 5042 <&gcc GCC_USB30_MP_SLEEP_CLK>, 5043 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5044 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5045 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5046 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5047 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5048 clock-names = "cfg_noc", 5049 "core", 5050 "iface", 5051 "sleep", 5052 "mock_utmi", 5053 "noc_aggr", 5054 "noc_aggr_north", 5055 "noc_aggr_south", 5056 "noc_sys"; 5057 5058 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5059 <&gcc GCC_USB30_MP_MASTER_CLK>; 5060 assigned-clock-rates = <19200000>, 5061 <200000000>; 5062 5063 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 5064 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 5065 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 5066 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 5067 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 5068 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 5069 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 5070 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 5071 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 5072 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 5073 interrupt-names = "pwr_event_1", "pwr_event_2", 5074 "hs_phy_1", "hs_phy_2", 5075 "dp_hs_phy_1", "dm_hs_phy_1", 5076 "dp_hs_phy_2", "dm_hs_phy_2", 5077 "ss_phy_1", "ss_phy_2"; 5078 5079 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5080 required-opps = <&rpmhpd_opp_nom>; 5081 5082 resets = <&gcc GCC_USB30_MP_BCR>; 5083 5084 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5086 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5087 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5088 interconnect-names = "usb-ddr", 5089 "apps-usb"; 5090 5091 wakeup-source; 5092 5093 #address-cells = <2>; 5094 #size-cells = <2>; 5095 ranges; 5096 5097 status = "disabled"; 5098 5099 usb_mp_dwc3: usb@a400000 { 5100 compatible = "snps,dwc3"; 5101 reg = <0 0x0a400000 0 0xcd00>; 5102 5103 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 5104 5105 iommus = <&apps_smmu 0x1400 0x0>; 5106 5107 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 5108 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 5109 phy-names = "usb2-0", "usb3-0", 5110 "usb2-1", "usb3-1"; 5111 dr_mode = "host"; 5112 5113 snps,dis_u2_susphy_quirk; 5114 snps,dis_enblslpm_quirk; 5115 snps,usb3_lpm_capable; 5116 snps,dis-u1-entry-quirk; 5117 snps,dis-u2-entry-quirk; 5118 5119 dma-coherent; 5120 }; 5121 }; 5122 5123 usb_1_ss0: usb@a6f8800 { 5124 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5125 reg = <0 0x0a6f8800 0 0x400>; 5126 5127 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5128 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5129 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5130 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5131 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5132 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5133 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 5134 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 5135 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5136 clock-names = "cfg_noc", 5137 "core", 5138 "iface", 5139 "sleep", 5140 "mock_utmi", 5141 "noc_aggr", 5142 "noc_aggr_north", 5143 "noc_aggr_south", 5144 "noc_sys"; 5145 5146 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5147 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5148 assigned-clock-rates = <19200000>, 5149 <200000000>; 5150 5151 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5152 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5153 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5154 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5155 interrupt-names = "pwr_event", 5156 "dp_hs_phy_irq", 5157 "dm_hs_phy_irq", 5158 "ss_phy_irq"; 5159 5160 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5161 required-opps = <&rpmhpd_opp_nom>; 5162 5163 resets = <&gcc GCC_USB30_PRIM_BCR>; 5164 5165 wakeup-source; 5166 5167 #address-cells = <2>; 5168 #size-cells = <2>; 5169 ranges; 5170 5171 status = "disabled"; 5172 5173 usb_1_ss0_dwc3: usb@a600000 { 5174 compatible = "snps,dwc3"; 5175 reg = <0 0x0a600000 0 0xcd00>; 5176 5177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 5178 5179 iommus = <&apps_smmu 0x1420 0x0>; 5180 5181 phys = <&usb_1_ss0_hsphy>, 5182 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5183 phy-names = "usb2-phy", 5184 "usb3-phy"; 5185 5186 snps,dis_u2_susphy_quirk; 5187 snps,dis_enblslpm_quirk; 5188 snps,usb3_lpm_capable; 5189 snps,dis-u1-entry-quirk; 5190 snps,dis-u2-entry-quirk; 5191 5192 dma-coherent; 5193 5194 ports { 5195 #address-cells = <1>; 5196 #size-cells = <0>; 5197 5198 port@0 { 5199 reg = <0>; 5200 5201 usb_1_ss0_dwc3_hs: endpoint { 5202 }; 5203 }; 5204 5205 port@1 { 5206 reg = <1>; 5207 5208 usb_1_ss0_dwc3_ss: endpoint { 5209 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5210 }; 5211 }; 5212 }; 5213 }; 5214 }; 5215 5216 usb_1_ss1: usb@a8f8800 { 5217 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5218 reg = <0 0x0a8f8800 0 0x400>; 5219 5220 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5221 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5222 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5223 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5224 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5225 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5226 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5227 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5228 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5229 clock-names = "cfg_noc", 5230 "core", 5231 "iface", 5232 "sleep", 5233 "mock_utmi", 5234 "noc_aggr", 5235 "noc_aggr_north", 5236 "noc_aggr_south", 5237 "noc_sys"; 5238 5239 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5240 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5241 assigned-clock-rates = <19200000>, 5242 <200000000>; 5243 5244 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5245 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5246 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5247 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5248 interrupt-names = "pwr_event", 5249 "dp_hs_phy_irq", 5250 "dm_hs_phy_irq", 5251 "ss_phy_irq"; 5252 5253 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5254 required-opps = <&rpmhpd_opp_nom>; 5255 5256 resets = <&gcc GCC_USB30_SEC_BCR>; 5257 5258 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5259 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5260 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5261 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5262 interconnect-names = "usb-ddr", 5263 "apps-usb"; 5264 5265 wakeup-source; 5266 5267 #address-cells = <2>; 5268 #size-cells = <2>; 5269 ranges; 5270 5271 status = "disabled"; 5272 5273 usb_1_ss1_dwc3: usb@a800000 { 5274 compatible = "snps,dwc3"; 5275 reg = <0 0x0a800000 0 0xcd00>; 5276 5277 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5278 5279 iommus = <&apps_smmu 0x1460 0x0>; 5280 5281 phys = <&usb_1_ss1_hsphy>, 5282 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5283 phy-names = "usb2-phy", 5284 "usb3-phy"; 5285 5286 snps,dis_u2_susphy_quirk; 5287 snps,dis_enblslpm_quirk; 5288 snps,usb3_lpm_capable; 5289 snps,dis-u1-entry-quirk; 5290 snps,dis-u2-entry-quirk; 5291 5292 dma-coherent; 5293 5294 ports { 5295 #address-cells = <1>; 5296 #size-cells = <0>; 5297 5298 port@0 { 5299 reg = <0>; 5300 5301 usb_1_ss1_dwc3_hs: endpoint { 5302 }; 5303 }; 5304 5305 port@1 { 5306 reg = <1>; 5307 5308 usb_1_ss1_dwc3_ss: endpoint { 5309 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5310 }; 5311 }; 5312 }; 5313 }; 5314 }; 5315 5316 iris: video-codec@aa00000 { 5317 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; 5318 5319 reg = <0 0x0aa00000 0 0xf0000>; 5320 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5321 5322 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5323 <&videocc VIDEO_CC_MVS0_GDSC>, 5324 <&rpmhpd RPMHPD_MXC>, 5325 <&rpmhpd RPMHPD_MMCX>; 5326 power-domain-names = "venus", 5327 "vcodec0", 5328 "mxc", 5329 "mmcx"; 5330 operating-points-v2 = <&iris_opp_table>; 5331 5332 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5333 <&videocc VIDEO_CC_MVS0C_CLK>, 5334 <&videocc VIDEO_CC_MVS0_CLK>; 5335 clock-names = "iface", 5336 "core", 5337 "vcodec0_core"; 5338 5339 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5340 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5341 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5342 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5343 interconnect-names = "cpu-cfg", 5344 "video-mem"; 5345 5346 memory-region = <&video_mem>; 5347 5348 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5349 reset-names = "bus"; 5350 5351 iommus = <&apps_smmu 0x1940 0>, 5352 <&apps_smmu 0x1947 0>; 5353 dma-coherent; 5354 5355 /* 5356 * IRIS firmware is signed by vendors, only 5357 * enable on boards where the proper signed firmware 5358 * is available. 5359 */ 5360 status = "disabled"; 5361 5362 iris_opp_table: opp-table { 5363 compatible = "operating-points-v2"; 5364 5365 opp-192000000 { 5366 opp-hz = /bits/ 64 <192000000>; 5367 required-opps = <&rpmhpd_opp_low_svs_d1>, 5368 <&rpmhpd_opp_low_svs_d1>; 5369 }; 5370 5371 opp-240000000 { 5372 opp-hz = /bits/ 64 <240000000>; 5373 required-opps = <&rpmhpd_opp_svs>, 5374 <&rpmhpd_opp_low_svs>; 5375 }; 5376 5377 opp-338000000 { 5378 opp-hz = /bits/ 64 <338000000>; 5379 required-opps = <&rpmhpd_opp_svs>, 5380 <&rpmhpd_opp_svs>; 5381 }; 5382 5383 opp-366000000 { 5384 opp-hz = /bits/ 64 <366000000>; 5385 required-opps = <&rpmhpd_opp_svs_l1>, 5386 <&rpmhpd_opp_svs_l1>; 5387 }; 5388 5389 opp-444000000 { 5390 opp-hz = /bits/ 64 <444000000>; 5391 required-opps = <&rpmhpd_opp_nom>, 5392 <&rpmhpd_opp_nom>; 5393 }; 5394 5395 opp-481000000 { 5396 opp-hz = /bits/ 64 <481000000>; 5397 required-opps = <&rpmhpd_opp_turbo>, 5398 <&rpmhpd_opp_turbo>; 5399 }; 5400 }; 5401 }; 5402 5403 videocc: clock-controller@aaf0000 { 5404 compatible = "qcom,x1e80100-videocc"; 5405 reg = <0 0x0aaf0000 0 0x10000>; 5406 clocks = <&bi_tcxo_div2>, 5407 <&gcc GCC_VIDEO_AHB_CLK>; 5408 power-domains = <&rpmhpd RPMHPD_MMCX>, 5409 <&rpmhpd RPMHPD_MXC>; 5410 required-opps = <&rpmhpd_opp_low_svs>, 5411 <&rpmhpd_opp_low_svs>; 5412 #clock-cells = <1>; 5413 #reset-cells = <1>; 5414 #power-domain-cells = <1>; 5415 }; 5416 5417 mdss: display-subsystem@ae00000 { 5418 compatible = "qcom,x1e80100-mdss"; 5419 reg = <0 0x0ae00000 0 0x1000>; 5420 reg-names = "mdss"; 5421 5422 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5423 5424 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5425 <&gcc GCC_DISP_HF_AXI_CLK>, 5426 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5427 5428 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5429 5430 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5431 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5432 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5433 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5434 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5435 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5436 interconnect-names = "mdp0-mem", 5437 "mdp1-mem", 5438 "cpu-cfg"; 5439 5440 power-domains = <&dispcc MDSS_GDSC>; 5441 5442 iommus = <&apps_smmu 0x1c00 0x2>; 5443 5444 interrupt-controller; 5445 #interrupt-cells = <1>; 5446 5447 #address-cells = <2>; 5448 #size-cells = <2>; 5449 ranges; 5450 5451 status = "disabled"; 5452 5453 mdss_mdp: display-controller@ae01000 { 5454 compatible = "qcom,x1e80100-dpu"; 5455 reg = <0 0x0ae01000 0 0x8f000>, 5456 <0 0x0aeb0000 0 0x2008>; 5457 reg-names = "mdp", 5458 "vbif"; 5459 5460 interrupts-extended = <&mdss 0>; 5461 5462 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5463 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5464 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5465 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5466 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5467 clock-names = "nrt_bus", 5468 "iface", 5469 "lut", 5470 "core", 5471 "vsync"; 5472 5473 operating-points-v2 = <&mdp_opp_table>; 5474 5475 power-domains = <&rpmhpd RPMHPD_MMCX>; 5476 5477 ports { 5478 #address-cells = <1>; 5479 #size-cells = <0>; 5480 5481 port@0 { 5482 reg = <0>; 5483 5484 mdss_intf0_out: endpoint { 5485 remote-endpoint = <&mdss_dp0_in>; 5486 }; 5487 }; 5488 5489 port@4 { 5490 reg = <4>; 5491 5492 mdss_intf4_out: endpoint { 5493 remote-endpoint = <&mdss_dp1_in>; 5494 }; 5495 }; 5496 5497 port@5 { 5498 reg = <5>; 5499 5500 mdss_intf5_out: endpoint { 5501 remote-endpoint = <&mdss_dp3_in>; 5502 }; 5503 }; 5504 5505 port@6 { 5506 reg = <6>; 5507 5508 mdss_intf6_out: endpoint { 5509 remote-endpoint = <&mdss_dp2_in>; 5510 }; 5511 }; 5512 }; 5513 5514 mdp_opp_table: opp-table { 5515 compatible = "operating-points-v2"; 5516 5517 opp-200000000 { 5518 opp-hz = /bits/ 64 <200000000>; 5519 required-opps = <&rpmhpd_opp_low_svs>; 5520 }; 5521 5522 opp-325000000 { 5523 opp-hz = /bits/ 64 <325000000>; 5524 required-opps = <&rpmhpd_opp_svs>; 5525 }; 5526 5527 opp-375000000 { 5528 opp-hz = /bits/ 64 <375000000>; 5529 required-opps = <&rpmhpd_opp_svs_l1>; 5530 }; 5531 5532 opp-514000000 { 5533 opp-hz = /bits/ 64 <514000000>; 5534 required-opps = <&rpmhpd_opp_nom>; 5535 }; 5536 5537 opp-575000000 { 5538 opp-hz = /bits/ 64 <575000000>; 5539 required-opps = <&rpmhpd_opp_nom_l1>; 5540 }; 5541 }; 5542 }; 5543 5544 mdss_dp0: displayport-controller@ae90000 { 5545 compatible = "qcom,x1e80100-dp"; 5546 reg = <0 0x0ae90000 0 0x200>, 5547 <0 0x0ae90200 0 0x200>, 5548 <0 0x0ae90400 0 0xc00>, 5549 <0 0x0ae91000 0 0x400>, 5550 <0 0x0ae91400 0 0x400>; 5551 5552 interrupts-extended = <&mdss 12>; 5553 5554 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5555 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5556 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5557 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5558 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5559 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5560 clock-names = "core_iface", 5561 "core_aux", 5562 "ctrl_link", 5563 "ctrl_link_iface", 5564 "stream_pixel", 5565 "stream_1_pixel"; 5566 5567 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5568 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5569 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5570 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5571 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5572 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5573 5574 operating-points-v2 = <&mdss_dp0_opp_table>; 5575 5576 power-domains = <&rpmhpd RPMHPD_MMCX>; 5577 5578 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5579 phy-names = "dp"; 5580 5581 #sound-dai-cells = <0>; 5582 5583 status = "disabled"; 5584 5585 ports { 5586 #address-cells = <1>; 5587 #size-cells = <0>; 5588 5589 port@0 { 5590 reg = <0>; 5591 5592 mdss_dp0_in: endpoint { 5593 remote-endpoint = <&mdss_intf0_out>; 5594 }; 5595 }; 5596 5597 port@1 { 5598 reg = <1>; 5599 5600 mdss_dp0_out: endpoint { 5601 data-lanes = <0 1 2 3>; 5602 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5603 }; 5604 }; 5605 }; 5606 5607 mdss_dp0_opp_table: opp-table { 5608 compatible = "operating-points-v2"; 5609 5610 opp-160000000 { 5611 opp-hz = /bits/ 64 <160000000>; 5612 required-opps = <&rpmhpd_opp_low_svs>; 5613 }; 5614 5615 opp-270000000 { 5616 opp-hz = /bits/ 64 <270000000>; 5617 required-opps = <&rpmhpd_opp_svs>; 5618 }; 5619 5620 opp-540000000 { 5621 opp-hz = /bits/ 64 <540000000>; 5622 required-opps = <&rpmhpd_opp_svs_l1>; 5623 }; 5624 5625 opp-810000000 { 5626 opp-hz = /bits/ 64 <810000000>; 5627 required-opps = <&rpmhpd_opp_nom>; 5628 }; 5629 }; 5630 }; 5631 5632 mdss_dp1: displayport-controller@ae98000 { 5633 compatible = "qcom,x1e80100-dp"; 5634 reg = <0 0x0ae98000 0 0x200>, 5635 <0 0x0ae98200 0 0x200>, 5636 <0 0x0ae98400 0 0xc00>, 5637 <0 0x0ae99000 0 0x400>, 5638 <0 0x0ae99400 0 0x400>; 5639 5640 interrupts-extended = <&mdss 13>; 5641 5642 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5643 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5644 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5645 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5646 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5647 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5648 clock-names = "core_iface", 5649 "core_aux", 5650 "ctrl_link", 5651 "ctrl_link_iface", 5652 "stream_pixel", 5653 "stream_1_pixel"; 5654 5655 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5656 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5657 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5658 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5659 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5660 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5661 5662 operating-points-v2 = <&mdss_dp1_opp_table>; 5663 5664 power-domains = <&rpmhpd RPMHPD_MMCX>; 5665 5666 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5667 phy-names = "dp"; 5668 5669 #sound-dai-cells = <0>; 5670 5671 status = "disabled"; 5672 5673 ports { 5674 #address-cells = <1>; 5675 #size-cells = <0>; 5676 5677 port@0 { 5678 reg = <0>; 5679 5680 mdss_dp1_in: endpoint { 5681 remote-endpoint = <&mdss_intf4_out>; 5682 }; 5683 }; 5684 5685 port@1 { 5686 reg = <1>; 5687 5688 mdss_dp1_out: endpoint { 5689 data-lanes = <0 1 2 3>; 5690 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5691 }; 5692 }; 5693 }; 5694 5695 mdss_dp1_opp_table: opp-table { 5696 compatible = "operating-points-v2"; 5697 5698 opp-160000000 { 5699 opp-hz = /bits/ 64 <160000000>; 5700 required-opps = <&rpmhpd_opp_low_svs>; 5701 }; 5702 5703 opp-270000000 { 5704 opp-hz = /bits/ 64 <270000000>; 5705 required-opps = <&rpmhpd_opp_svs>; 5706 }; 5707 5708 opp-540000000 { 5709 opp-hz = /bits/ 64 <540000000>; 5710 required-opps = <&rpmhpd_opp_svs_l1>; 5711 }; 5712 5713 opp-810000000 { 5714 opp-hz = /bits/ 64 <810000000>; 5715 required-opps = <&rpmhpd_opp_nom>; 5716 }; 5717 }; 5718 }; 5719 5720 mdss_dp2: displayport-controller@ae9a000 { 5721 compatible = "qcom,x1e80100-dp"; 5722 reg = <0 0x0ae9a000 0 0x200>, 5723 <0 0x0ae9a200 0 0x200>, 5724 <0 0x0ae9a400 0 0xc00>, 5725 <0 0x0ae9b000 0 0x400>, 5726 <0 0x0ae9b400 0 0x400>; 5727 5728 interrupts-extended = <&mdss 14>; 5729 5730 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5731 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5732 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5733 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5734 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5735 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5736 clock-names = "core_iface", 5737 "core_aux", 5738 "ctrl_link", 5739 "ctrl_link_iface", 5740 "stream_pixel", 5741 "stream_1_pixel"; 5742 5743 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5744 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5745 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5746 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5747 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5748 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5749 5750 operating-points-v2 = <&mdss_dp2_opp_table>; 5751 5752 power-domains = <&rpmhpd RPMHPD_MMCX>; 5753 5754 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5755 phy-names = "dp"; 5756 5757 #sound-dai-cells = <0>; 5758 5759 status = "disabled"; 5760 5761 ports { 5762 #address-cells = <1>; 5763 #size-cells = <0>; 5764 5765 port@0 { 5766 reg = <0>; 5767 mdss_dp2_in: endpoint { 5768 remote-endpoint = <&mdss_intf6_out>; 5769 }; 5770 }; 5771 5772 port@1 { 5773 reg = <1>; 5774 5775 mdss_dp2_out: endpoint { 5776 data-lanes = <0 1 2 3>; 5777 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5778 }; 5779 }; 5780 }; 5781 5782 mdss_dp2_opp_table: opp-table { 5783 compatible = "operating-points-v2"; 5784 5785 opp-160000000 { 5786 opp-hz = /bits/ 64 <160000000>; 5787 required-opps = <&rpmhpd_opp_low_svs>; 5788 }; 5789 5790 opp-270000000 { 5791 opp-hz = /bits/ 64 <270000000>; 5792 required-opps = <&rpmhpd_opp_svs>; 5793 }; 5794 5795 opp-540000000 { 5796 opp-hz = /bits/ 64 <540000000>; 5797 required-opps = <&rpmhpd_opp_svs_l1>; 5798 }; 5799 5800 opp-810000000 { 5801 opp-hz = /bits/ 64 <810000000>; 5802 required-opps = <&rpmhpd_opp_nom>; 5803 }; 5804 }; 5805 }; 5806 5807 mdss_dp3: displayport-controller@aea0000 { 5808 compatible = "qcom,x1e80100-dp"; 5809 reg = <0 0x0aea0000 0 0x200>, 5810 <0 0x0aea0200 0 0x200>, 5811 <0 0x0aea0400 0 0xc00>, 5812 <0 0x0aea1000 0 0x400>, 5813 <0 0x0aea1400 0 0x400>; 5814 5815 interrupts-extended = <&mdss 15>; 5816 5817 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5818 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5819 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5820 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5821 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5822 clock-names = "core_iface", 5823 "core_aux", 5824 "ctrl_link", 5825 "ctrl_link_iface", 5826 "stream_pixel"; 5827 5828 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5829 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5830 assigned-clock-parents = <&mdss_dp3_phy 0>, 5831 <&mdss_dp3_phy 1>; 5832 5833 operating-points-v2 = <&mdss_dp3_opp_table>; 5834 5835 power-domains = <&rpmhpd RPMHPD_MMCX>; 5836 5837 phys = <&mdss_dp3_phy>; 5838 phy-names = "dp"; 5839 5840 #sound-dai-cells = <0>; 5841 5842 status = "disabled"; 5843 5844 ports { 5845 #address-cells = <1>; 5846 #size-cells = <0>; 5847 5848 port@0 { 5849 reg = <0>; 5850 5851 mdss_dp3_in: endpoint { 5852 remote-endpoint = <&mdss_intf5_out>; 5853 }; 5854 }; 5855 5856 port@1 { 5857 reg = <1>; 5858 5859 mdss_dp3_out: endpoint { 5860 }; 5861 }; 5862 }; 5863 5864 mdss_dp3_opp_table: opp-table { 5865 compatible = "operating-points-v2"; 5866 5867 opp-160000000 { 5868 opp-hz = /bits/ 64 <160000000>; 5869 required-opps = <&rpmhpd_opp_low_svs>; 5870 }; 5871 5872 opp-270000000 { 5873 opp-hz = /bits/ 64 <270000000>; 5874 required-opps = <&rpmhpd_opp_svs>; 5875 }; 5876 5877 opp-540000000 { 5878 opp-hz = /bits/ 64 <540000000>; 5879 required-opps = <&rpmhpd_opp_svs_l1>; 5880 }; 5881 5882 opp-810000000 { 5883 opp-hz = /bits/ 64 <810000000>; 5884 required-opps = <&rpmhpd_opp_nom>; 5885 }; 5886 }; 5887 }; 5888 5889 }; 5890 5891 mdss_dp2_phy: phy@aec2a00 { 5892 compatible = "qcom,x1e80100-dp-phy"; 5893 reg = <0 0x0aec2a00 0 0x19c>, 5894 <0 0x0aec2200 0 0xec>, 5895 <0 0x0aec2600 0 0xec>, 5896 <0 0x0aec2000 0 0x1c8>; 5897 5898 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5899 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5900 clock-names = "aux", 5901 "cfg_ahb"; 5902 5903 power-domains = <&rpmhpd RPMHPD_MX>; 5904 5905 #clock-cells = <1>; 5906 #phy-cells = <0>; 5907 5908 status = "disabled"; 5909 }; 5910 5911 mdss_dp3_phy: phy@aec5a00 { 5912 compatible = "qcom,x1e80100-dp-phy"; 5913 reg = <0 0x0aec5a00 0 0x19c>, 5914 <0 0x0aec5200 0 0xec>, 5915 <0 0x0aec5600 0 0xec>, 5916 <0 0x0aec5000 0 0x1c8>; 5917 5918 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5919 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5920 clock-names = "aux", 5921 "cfg_ahb"; 5922 5923 power-domains = <&rpmhpd RPMHPD_MX>; 5924 5925 #clock-cells = <1>; 5926 #phy-cells = <0>; 5927 5928 status = "disabled"; 5929 }; 5930 5931 dispcc: clock-controller@af00000 { 5932 compatible = "qcom,x1e80100-dispcc"; 5933 reg = <0 0x0af00000 0 0x20000>; 5934 clocks = <&bi_tcxo_div2>, 5935 <&bi_tcxo_ao_div2>, 5936 <&gcc GCC_DISP_AHB_CLK>, 5937 <&sleep_clk>, 5938 <0>, /* dsi0 */ 5939 <0>, 5940 <0>, /* dsi1 */ 5941 <0>, 5942 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5943 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5944 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5945 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5946 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5947 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5948 <&mdss_dp3_phy 0>, /* dp3 */ 5949 <&mdss_dp3_phy 1>; 5950 power-domains = <&rpmhpd RPMHPD_MMCX>; 5951 required-opps = <&rpmhpd_opp_low_svs>; 5952 #clock-cells = <1>; 5953 #reset-cells = <1>; 5954 #power-domain-cells = <1>; 5955 }; 5956 5957 pdc: interrupt-controller@b220000 { 5958 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5959 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5960 5961 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5962 <47 522 52>, <99 609 32>, 5963 <131 717 12>, <143 816 19>; 5964 #interrupt-cells = <2>; 5965 interrupt-parent = <&intc>; 5966 interrupt-controller; 5967 }; 5968 5969 aoss_qmp: power-management@c300000 { 5970 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5971 reg = <0 0x0c300000 0 0x400>; 5972 interrupt-parent = <&ipcc>; 5973 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5974 IRQ_TYPE_EDGE_RISING>; 5975 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5976 5977 #clock-cells = <0>; 5978 }; 5979 5980 sram@c3f0000 { 5981 compatible = "qcom,rpmh-stats"; 5982 reg = <0 0x0c3f0000 0 0x400>; 5983 }; 5984 5985 spmi: arbiter@c400000 { 5986 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5987 reg = <0 0x0c400000 0 0x3000>, 5988 <0 0x0c500000 0 0x400000>, 5989 <0 0x0c440000 0 0x80000>; 5990 reg-names = "core", "chnls", "obsrvr"; 5991 5992 qcom,ee = <0>; 5993 qcom,channel = <0>; 5994 5995 #address-cells = <2>; 5996 #size-cells = <2>; 5997 ranges; 5998 5999 spmi_bus0: spmi@c42d000 { 6000 reg = <0 0x0c42d000 0 0x4000>, 6001 <0 0x0c4c0000 0 0x10000>; 6002 reg-names = "cnfg", "intr"; 6003 6004 interrupt-names = "periph_irq"; 6005 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6006 interrupt-controller; 6007 #interrupt-cells = <4>; 6008 6009 #address-cells = <2>; 6010 #size-cells = <0>; 6011 }; 6012 6013 spmi_bus1: spmi@c432000 { 6014 reg = <0 0x0c432000 0 0x4000>, 6015 <0 0x0c4d0000 0 0x10000>; 6016 reg-names = "cnfg", "intr"; 6017 6018 interrupt-names = "periph_irq"; 6019 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 6020 interrupt-controller; 6021 #interrupt-cells = <4>; 6022 6023 #address-cells = <2>; 6024 #size-cells = <0>; 6025 }; 6026 }; 6027 6028 tlmm: pinctrl@f100000 { 6029 compatible = "qcom,x1e80100-tlmm"; 6030 reg = <0 0x0f100000 0 0xf00000>; 6031 6032 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6033 6034 gpio-controller; 6035 #gpio-cells = <2>; 6036 6037 interrupt-controller; 6038 #interrupt-cells = <2>; 6039 6040 gpio-ranges = <&tlmm 0 0 239>; 6041 wakeup-parent = <&pdc>; 6042 6043 edp0_hpd_default: edp0-hpd-default-state { 6044 pins = "gpio119"; 6045 function = "edp0_hot"; 6046 bias-disable; 6047 }; 6048 6049 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6050 /* SDA, SCL */ 6051 pins = "gpio0", "gpio1"; 6052 function = "qup0_se0"; 6053 drive-strength = <2>; 6054 bias-pull-up = <2200>; 6055 }; 6056 6057 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6058 /* SDA, SCL */ 6059 pins = "gpio4", "gpio5"; 6060 function = "qup0_se1"; 6061 drive-strength = <2>; 6062 bias-pull-up = <2200>; 6063 }; 6064 6065 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6066 /* SDA, SCL */ 6067 pins = "gpio8", "gpio9"; 6068 function = "qup0_se2"; 6069 drive-strength = <2>; 6070 bias-pull-up = <2200>; 6071 }; 6072 6073 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6074 /* SDA, SCL */ 6075 pins = "gpio12", "gpio13"; 6076 function = "qup0_se3"; 6077 drive-strength = <2>; 6078 bias-pull-up = <2200>; 6079 }; 6080 6081 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6082 /* SDA, SCL */ 6083 pins = "gpio16", "gpio17"; 6084 function = "qup0_se4"; 6085 drive-strength = <2>; 6086 bias-pull-up = <2200>; 6087 }; 6088 6089 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6090 /* SDA, SCL */ 6091 pins = "gpio20", "gpio21"; 6092 function = "qup0_se5"; 6093 drive-strength = <2>; 6094 bias-pull-up = <2200>; 6095 }; 6096 6097 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6098 /* SDA, SCL */ 6099 pins = "gpio24", "gpio25"; 6100 function = "qup0_se6"; 6101 drive-strength = <2>; 6102 bias-pull-up = <2200>; 6103 }; 6104 6105 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6106 /* SDA, SCL */ 6107 pins = "gpio14", "gpio15"; 6108 function = "qup0_se7"; 6109 drive-strength = <2>; 6110 bias-pull-up = <2200>; 6111 }; 6112 6113 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6114 /* SDA, SCL */ 6115 pins = "gpio32", "gpio33"; 6116 function = "qup1_se0"; 6117 drive-strength = <2>; 6118 bias-pull-up = <2200>; 6119 }; 6120 6121 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6122 /* SDA, SCL */ 6123 pins = "gpio36", "gpio37"; 6124 function = "qup1_se1"; 6125 drive-strength = <2>; 6126 bias-pull-up = <2200>; 6127 }; 6128 6129 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6130 /* SDA, SCL */ 6131 pins = "gpio40", "gpio41"; 6132 function = "qup1_se2"; 6133 drive-strength = <2>; 6134 bias-pull-up = <2200>; 6135 }; 6136 6137 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6138 /* SDA, SCL */ 6139 pins = "gpio44", "gpio45"; 6140 function = "qup1_se3"; 6141 drive-strength = <2>; 6142 bias-pull-up = <2200>; 6143 }; 6144 6145 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6146 /* SDA, SCL */ 6147 pins = "gpio48", "gpio49"; 6148 function = "qup1_se4"; 6149 drive-strength = <2>; 6150 bias-pull-up = <2200>; 6151 }; 6152 6153 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6154 /* SDA, SCL */ 6155 pins = "gpio52", "gpio53"; 6156 function = "qup1_se5"; 6157 drive-strength = <2>; 6158 bias-pull-up = <2200>; 6159 }; 6160 6161 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6162 /* SDA, SCL */ 6163 pins = "gpio56", "gpio57"; 6164 function = "qup1_se6"; 6165 drive-strength = <2>; 6166 bias-pull-up = <2200>; 6167 }; 6168 6169 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6170 /* SDA, SCL */ 6171 pins = "gpio54", "gpio55"; 6172 function = "qup1_se7"; 6173 drive-strength = <2>; 6174 bias-pull-up = <2200>; 6175 }; 6176 6177 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6178 /* SDA, SCL */ 6179 pins = "gpio64", "gpio65"; 6180 function = "qup2_se0"; 6181 drive-strength = <2>; 6182 bias-pull-up = <2200>; 6183 }; 6184 6185 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6186 /* SDA, SCL */ 6187 pins = "gpio68", "gpio69"; 6188 function = "qup2_se1"; 6189 drive-strength = <2>; 6190 bias-pull-up = <2200>; 6191 }; 6192 6193 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6194 /* SDA, SCL */ 6195 pins = "gpio72", "gpio73"; 6196 function = "qup2_se2"; 6197 drive-strength = <2>; 6198 bias-pull-up = <2200>; 6199 }; 6200 6201 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6202 /* SDA, SCL */ 6203 pins = "gpio76", "gpio77"; 6204 function = "qup2_se3"; 6205 drive-strength = <2>; 6206 bias-pull-up = <2200>; 6207 }; 6208 6209 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6210 /* SDA, SCL */ 6211 pins = "gpio80", "gpio81"; 6212 function = "qup2_se4"; 6213 drive-strength = <2>; 6214 bias-pull-up = <2200>; 6215 }; 6216 6217 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6218 /* SDA, SCL */ 6219 pins = "gpio84", "gpio85"; 6220 function = "qup2_se5"; 6221 drive-strength = <2>; 6222 bias-pull-up = <2200>; 6223 }; 6224 6225 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6226 /* SDA, SCL */ 6227 pins = "gpio88", "gpio89"; 6228 function = "qup2_se6"; 6229 drive-strength = <2>; 6230 bias-pull-up = <2200>; 6231 }; 6232 6233 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6234 /* SDA, SCL */ 6235 pins = "gpio86", "gpio87"; 6236 function = "qup2_se7"; 6237 drive-strength = <2>; 6238 bias-pull-up = <2200>; 6239 }; 6240 6241 qup_spi0_cs: qup-spi0-cs-state { 6242 pins = "gpio3"; 6243 function = "qup0_se0"; 6244 drive-strength = <6>; 6245 bias-disable; 6246 }; 6247 6248 qup_spi0_data_clk: qup-spi0-data-clk-state { 6249 /* MISO, MOSI, CLK */ 6250 pins = "gpio0", "gpio1", "gpio2"; 6251 function = "qup0_se0"; 6252 drive-strength = <6>; 6253 bias-disable; 6254 }; 6255 6256 qup_spi1_cs: qup-spi1-cs-state { 6257 pins = "gpio7"; 6258 function = "qup0_se1"; 6259 drive-strength = <6>; 6260 bias-disable; 6261 }; 6262 6263 qup_spi1_data_clk: qup-spi1-data-clk-state { 6264 /* MISO, MOSI, CLK */ 6265 pins = "gpio4", "gpio5", "gpio6"; 6266 function = "qup0_se1"; 6267 drive-strength = <6>; 6268 bias-disable; 6269 }; 6270 6271 qup_spi2_cs: qup-spi2-cs-state { 6272 pins = "gpio11"; 6273 function = "qup0_se2"; 6274 drive-strength = <6>; 6275 bias-disable; 6276 }; 6277 6278 qup_spi2_data_clk: qup-spi2-data-clk-state { 6279 /* MISO, MOSI, CLK */ 6280 pins = "gpio8", "gpio9", "gpio10"; 6281 function = "qup0_se2"; 6282 drive-strength = <6>; 6283 bias-disable; 6284 }; 6285 6286 qup_spi3_cs: qup-spi3-cs-state { 6287 pins = "gpio15"; 6288 function = "qup0_se3"; 6289 drive-strength = <6>; 6290 bias-disable; 6291 }; 6292 6293 qup_spi3_data_clk: qup-spi3-data-clk-state { 6294 /* MISO, MOSI, CLK */ 6295 pins = "gpio12", "gpio13", "gpio14"; 6296 function = "qup0_se3"; 6297 drive-strength = <6>; 6298 bias-disable; 6299 }; 6300 6301 qup_spi4_cs: qup-spi4-cs-state { 6302 pins = "gpio19"; 6303 function = "qup0_se4"; 6304 drive-strength = <6>; 6305 bias-disable; 6306 }; 6307 6308 qup_spi4_data_clk: qup-spi4-data-clk-state { 6309 /* MISO, MOSI, CLK */ 6310 pins = "gpio16", "gpio17", "gpio18"; 6311 function = "qup0_se4"; 6312 drive-strength = <6>; 6313 bias-disable; 6314 }; 6315 6316 qup_spi5_cs: qup-spi5-cs-state { 6317 pins = "gpio23"; 6318 function = "qup0_se5"; 6319 drive-strength = <6>; 6320 bias-disable; 6321 }; 6322 6323 qup_spi5_data_clk: qup-spi5-data-clk-state { 6324 /* MISO, MOSI, CLK */ 6325 pins = "gpio20", "gpio21", "gpio22"; 6326 function = "qup0_se5"; 6327 drive-strength = <6>; 6328 bias-disable; 6329 }; 6330 6331 qup_spi6_cs: qup-spi6-cs-state { 6332 pins = "gpio27"; 6333 function = "qup0_se6"; 6334 drive-strength = <6>; 6335 bias-disable; 6336 }; 6337 6338 qup_spi6_data_clk: qup-spi6-data-clk-state { 6339 /* MISO, MOSI, CLK */ 6340 pins = "gpio24", "gpio25", "gpio26"; 6341 function = "qup0_se6"; 6342 drive-strength = <6>; 6343 bias-disable; 6344 }; 6345 6346 qup_spi7_cs: qup-spi7-cs-state { 6347 pins = "gpio13"; 6348 function = "qup0_se7"; 6349 drive-strength = <6>; 6350 bias-disable; 6351 }; 6352 6353 qup_spi7_data_clk: qup-spi7-data-clk-state { 6354 /* MISO, MOSI, CLK */ 6355 pins = "gpio14", "gpio15", "gpio12"; 6356 function = "qup0_se7"; 6357 drive-strength = <6>; 6358 bias-disable; 6359 }; 6360 6361 qup_spi8_cs: qup-spi8-cs-state { 6362 pins = "gpio35"; 6363 function = "qup1_se0"; 6364 drive-strength = <6>; 6365 bias-disable; 6366 }; 6367 6368 qup_spi8_data_clk: qup-spi8-data-clk-state { 6369 /* MISO, MOSI, CLK */ 6370 pins = "gpio32", "gpio33", "gpio34"; 6371 function = "qup1_se0"; 6372 drive-strength = <6>; 6373 bias-disable; 6374 }; 6375 6376 qup_spi9_cs: qup-spi9-cs-state { 6377 pins = "gpio39"; 6378 function = "qup1_se1"; 6379 drive-strength = <6>; 6380 bias-disable; 6381 }; 6382 6383 qup_spi9_data_clk: qup-spi9-data-clk-state { 6384 /* MISO, MOSI, CLK */ 6385 pins = "gpio36", "gpio37", "gpio38"; 6386 function = "qup1_se1"; 6387 drive-strength = <6>; 6388 bias-disable; 6389 }; 6390 6391 qup_spi10_cs: qup-spi10-cs-state { 6392 pins = "gpio43"; 6393 function = "qup1_se2"; 6394 drive-strength = <6>; 6395 bias-disable; 6396 }; 6397 6398 qup_spi10_data_clk: qup-spi10-data-clk-state { 6399 /* MISO, MOSI, CLK */ 6400 pins = "gpio40", "gpio41", "gpio42"; 6401 function = "qup1_se2"; 6402 drive-strength = <6>; 6403 bias-disable; 6404 }; 6405 6406 qup_spi11_cs: qup-spi11-cs-state { 6407 pins = "gpio47"; 6408 function = "qup1_se3"; 6409 drive-strength = <6>; 6410 bias-disable; 6411 }; 6412 6413 qup_spi11_data_clk: qup-spi11-data-clk-state { 6414 /* MISO, MOSI, CLK */ 6415 pins = "gpio44", "gpio45", "gpio46"; 6416 function = "qup1_se3"; 6417 drive-strength = <6>; 6418 bias-disable; 6419 }; 6420 6421 qup_spi12_cs: qup-spi12-cs-state { 6422 pins = "gpio51"; 6423 function = "qup1_se4"; 6424 drive-strength = <6>; 6425 bias-disable; 6426 }; 6427 6428 qup_spi12_data_clk: qup-spi12-data-clk-state { 6429 /* MISO, MOSI, CLK */ 6430 pins = "gpio48", "gpio49", "gpio50"; 6431 function = "qup1_se4"; 6432 drive-strength = <6>; 6433 bias-disable; 6434 }; 6435 6436 qup_spi13_cs: qup-spi13-cs-state { 6437 pins = "gpio55"; 6438 function = "qup1_se5"; 6439 drive-strength = <6>; 6440 bias-disable; 6441 }; 6442 6443 qup_spi13_data_clk: qup-spi13-data-clk-state { 6444 /* MISO, MOSI, CLK */ 6445 pins = "gpio52", "gpio53", "gpio54"; 6446 function = "qup1_se5"; 6447 drive-strength = <6>; 6448 bias-disable; 6449 }; 6450 6451 qup_spi14_cs: qup-spi14-cs-state { 6452 pins = "gpio59"; 6453 function = "qup1_se6"; 6454 drive-strength = <6>; 6455 bias-disable; 6456 }; 6457 6458 qup_spi14_data_clk: qup-spi14-data-clk-state { 6459 /* MISO, MOSI, CLK */ 6460 pins = "gpio56", "gpio57", "gpio58"; 6461 function = "qup1_se6"; 6462 drive-strength = <6>; 6463 bias-disable; 6464 }; 6465 6466 qup_spi15_cs: qup-spi15-cs-state { 6467 pins = "gpio53"; 6468 function = "qup1_se7"; 6469 drive-strength = <6>; 6470 bias-disable; 6471 }; 6472 6473 qup_spi15_data_clk: qup-spi15-data-clk-state { 6474 /* MISO, MOSI, CLK */ 6475 pins = "gpio54", "gpio55", "gpio52"; 6476 function = "qup1_se7"; 6477 drive-strength = <6>; 6478 bias-disable; 6479 }; 6480 6481 qup_spi16_cs: qup-spi16-cs-state { 6482 pins = "gpio67"; 6483 function = "qup2_se0"; 6484 drive-strength = <6>; 6485 bias-disable; 6486 }; 6487 6488 qup_spi16_data_clk: qup-spi16-data-clk-state { 6489 /* MISO, MOSI, CLK */ 6490 pins = "gpio64", "gpio65", "gpio66"; 6491 function = "qup2_se0"; 6492 drive-strength = <6>; 6493 bias-disable; 6494 }; 6495 6496 qup_spi17_cs: qup-spi17-cs-state { 6497 pins = "gpio71"; 6498 function = "qup2_se1"; 6499 drive-strength = <6>; 6500 bias-disable; 6501 }; 6502 6503 qup_spi17_data_clk: qup-spi17-data-clk-state { 6504 /* MISO, MOSI, CLK */ 6505 pins = "gpio68", "gpio69", "gpio70"; 6506 function = "qup2_se1"; 6507 drive-strength = <6>; 6508 bias-disable; 6509 }; 6510 6511 qup_spi18_cs: qup-spi18-cs-state { 6512 pins = "gpio75"; 6513 function = "qup2_se2"; 6514 drive-strength = <6>; 6515 bias-disable; 6516 }; 6517 6518 qup_spi18_data_clk: qup-spi18-data-clk-state { 6519 /* MISO, MOSI, CLK */ 6520 pins = "gpio72", "gpio73", "gpio74"; 6521 function = "qup2_se2"; 6522 drive-strength = <6>; 6523 bias-disable; 6524 }; 6525 6526 qup_spi19_cs: qup-spi19-cs-state { 6527 pins = "gpio79"; 6528 function = "qup2_se3"; 6529 drive-strength = <6>; 6530 bias-disable; 6531 }; 6532 6533 qup_spi19_data_clk: qup-spi19-data-clk-state { 6534 /* MISO, MOSI, CLK */ 6535 pins = "gpio76", "gpio77", "gpio78"; 6536 function = "qup2_se3"; 6537 drive-strength = <6>; 6538 bias-disable; 6539 }; 6540 6541 qup_spi20_cs: qup-spi20-cs-state { 6542 pins = "gpio83"; 6543 function = "qup2_se4"; 6544 drive-strength = <6>; 6545 bias-disable; 6546 }; 6547 6548 qup_spi20_data_clk: qup-spi20-data-clk-state { 6549 /* MISO, MOSI, CLK */ 6550 pins = "gpio80", "gpio81", "gpio82"; 6551 function = "qup2_se4"; 6552 drive-strength = <6>; 6553 bias-disable; 6554 }; 6555 6556 qup_spi21_cs: qup-spi21-cs-state { 6557 pins = "gpio87"; 6558 function = "qup2_se5"; 6559 drive-strength = <6>; 6560 bias-disable; 6561 }; 6562 6563 qup_spi21_data_clk: qup-spi21-data-clk-state { 6564 /* MISO, MOSI, CLK */ 6565 pins = "gpio84", "gpio85", "gpio86"; 6566 function = "qup2_se5"; 6567 drive-strength = <6>; 6568 bias-disable; 6569 }; 6570 6571 qup_spi22_cs: qup-spi22-cs-state { 6572 pins = "gpio91"; 6573 function = "qup2_se6"; 6574 drive-strength = <6>; 6575 bias-disable; 6576 }; 6577 6578 qup_spi22_data_clk: qup-spi22-data-clk-state { 6579 /* MISO, MOSI, CLK */ 6580 pins = "gpio88", "gpio89", "gpio90"; 6581 function = "qup2_se6"; 6582 drive-strength = <6>; 6583 bias-disable; 6584 }; 6585 6586 qup_spi23_cs: qup-spi23-cs-state { 6587 pins = "gpio85"; 6588 function = "qup2_se7"; 6589 drive-strength = <6>; 6590 bias-disable; 6591 }; 6592 6593 qup_spi23_data_clk: qup-spi23-data-clk-state { 6594 /* MISO, MOSI, CLK */ 6595 pins = "gpio86", "gpio87", "gpio84"; 6596 function = "qup2_se7"; 6597 drive-strength = <6>; 6598 bias-disable; 6599 }; 6600 6601 qup_uart2_default: qup-uart2-default-state { 6602 cts-pins { 6603 pins = "gpio8"; 6604 function = "qup0_se2"; 6605 drive-strength = <2>; 6606 bias-disable; 6607 }; 6608 6609 rts-pins { 6610 pins = "gpio9"; 6611 function = "qup0_se2"; 6612 drive-strength = <2>; 6613 bias-disable; 6614 }; 6615 6616 tx-pins { 6617 pins = "gpio10"; 6618 function = "qup0_se2"; 6619 drive-strength = <2>; 6620 bias-disable; 6621 }; 6622 6623 rx-pins { 6624 pins = "gpio11"; 6625 function = "qup0_se2"; 6626 drive-strength = <2>; 6627 bias-disable; 6628 }; 6629 }; 6630 6631 qup_uart14_default: qup-uart14-default-state { 6632 cts-pins { 6633 pins = "gpio56"; 6634 function = "qup1_se6"; 6635 bias-bus-hold; 6636 }; 6637 6638 rts-pins { 6639 pins = "gpio57"; 6640 function = "qup1_se6"; 6641 drive-strength = <2>; 6642 bias-disable; 6643 }; 6644 6645 tx-pins { 6646 pins = "gpio58"; 6647 function = "qup1_se6"; 6648 drive-strength = <2>; 6649 bias-disable; 6650 }; 6651 6652 rx-pins { 6653 pins = "gpio59"; 6654 function = "qup1_se6"; 6655 bias-pull-up; 6656 }; 6657 }; 6658 6659 qup_uart21_default: qup-uart21-default-state { 6660 tx-pins { 6661 pins = "gpio86"; 6662 function = "qup2_se5"; 6663 drive-strength = <2>; 6664 bias-disable; 6665 }; 6666 6667 rx-pins { 6668 pins = "gpio87"; 6669 function = "qup2_se5"; 6670 drive-strength = <2>; 6671 bias-disable; 6672 }; 6673 }; 6674 6675 sdc2_default: sdc2-default-state { 6676 clk-pins { 6677 pins = "sdc2_clk"; 6678 drive-strength = <16>; 6679 bias-disable; 6680 }; 6681 6682 cmd-pins { 6683 pins = "sdc2_cmd"; 6684 drive-strength = <10>; 6685 bias-pull-up; 6686 }; 6687 6688 data-pins { 6689 pins = "sdc2_data"; 6690 drive-strength = <10>; 6691 bias-pull-up; 6692 }; 6693 }; 6694 6695 sdc2_sleep: sdc2-sleep-state { 6696 clk-pins { 6697 pins = "sdc2_clk"; 6698 drive-strength = <2>; 6699 bias-disable; 6700 }; 6701 6702 cmd-pins { 6703 pins = "sdc2_cmd"; 6704 drive-strength = <2>; 6705 bias-pull-up; 6706 }; 6707 6708 data-pins { 6709 pins = "sdc2_data"; 6710 drive-strength = <2>; 6711 bias-pull-up; 6712 }; 6713 }; 6714 }; 6715 6716 stm@10002000 { 6717 compatible = "arm,coresight-stm", "arm,primecell"; 6718 reg = <0x0 0x10002000 0x0 0x1000>, 6719 <0x0 0x16280000 0x0 0x180000>; 6720 reg-names = "stm-base", 6721 "stm-stimulus-base"; 6722 6723 clocks = <&aoss_qmp>; 6724 clock-names = "apb_pclk"; 6725 6726 out-ports { 6727 port { 6728 stm_out: endpoint { 6729 remote-endpoint = <&funnel0_in7>; 6730 }; 6731 }; 6732 }; 6733 }; 6734 6735 tpdm@10003000 { 6736 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6737 reg = <0x0 0x10003000 0x0 0x1000>; 6738 6739 clocks = <&aoss_qmp>; 6740 clock-names = "apb_pclk"; 6741 6742 qcom,cmb-element-bits = <32>; 6743 qcom,cmb-msrs-num = <32>; 6744 status = "disabled"; 6745 6746 out-ports { 6747 port { 6748 dcc_tpdm_out: endpoint { 6749 remote-endpoint = <&qdss_tpda_in0>; 6750 }; 6751 }; 6752 }; 6753 }; 6754 6755 tpda@10004000 { 6756 compatible = "qcom,coresight-tpda", "arm,primecell"; 6757 reg = <0x0 0x10004000 0x0 0x1000>; 6758 6759 clocks = <&aoss_qmp>; 6760 clock-names = "apb_pclk"; 6761 6762 in-ports { 6763 #address-cells = <1>; 6764 #size-cells = <0>; 6765 6766 port@0 { 6767 reg = <0>; 6768 6769 qdss_tpda_in0: endpoint { 6770 remote-endpoint = <&dcc_tpdm_out>; 6771 }; 6772 }; 6773 6774 port@1 { 6775 reg = <1>; 6776 6777 qdss_tpda_in1: endpoint { 6778 remote-endpoint = <&qdss_tpdm_out>; 6779 }; 6780 }; 6781 }; 6782 6783 out-ports { 6784 port { 6785 qdss_tpda_out: endpoint { 6786 remote-endpoint = <&funnel0_in6>; 6787 }; 6788 }; 6789 }; 6790 }; 6791 6792 tpdm@1000f000 { 6793 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6794 reg = <0x0 0x1000f000 0x0 0x1000>; 6795 6796 clocks = <&aoss_qmp>; 6797 clock-names = "apb_pclk"; 6798 6799 qcom,cmb-element-bits = <32>; 6800 qcom,cmb-msrs-num = <32>; 6801 6802 out-ports { 6803 port { 6804 qdss_tpdm_out: endpoint { 6805 remote-endpoint = <&qdss_tpda_in1>; 6806 }; 6807 }; 6808 }; 6809 }; 6810 6811 funnel@10041000 { 6812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6813 reg = <0x0 0x10041000 0x0 0x1000>; 6814 6815 clocks = <&aoss_qmp>; 6816 clock-names = "apb_pclk"; 6817 6818 in-ports { 6819 #address-cells = <1>; 6820 #size-cells = <0>; 6821 6822 port@6 { 6823 reg = <6>; 6824 6825 funnel0_in6: endpoint { 6826 remote-endpoint = <&qdss_tpda_out>; 6827 }; 6828 }; 6829 6830 port@7 { 6831 reg = <7>; 6832 6833 funnel0_in7: endpoint { 6834 remote-endpoint = <&stm_out>; 6835 }; 6836 }; 6837 }; 6838 6839 out-ports { 6840 port { 6841 funnel0_out: endpoint { 6842 remote-endpoint = <&qdss_funnel_in0>; 6843 }; 6844 }; 6845 }; 6846 }; 6847 6848 funnel@10042000 { 6849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6850 reg = <0x0 0x10042000 0x0 0x1000>; 6851 6852 clocks = <&aoss_qmp>; 6853 clock-names = "apb_pclk"; 6854 6855 in-ports { 6856 #address-cells = <1>; 6857 #size-cells = <0>; 6858 6859 port@2 { 6860 reg = <2>; 6861 6862 funnel1_in2: endpoint { 6863 remote-endpoint = <&tmess_funnel_out>; 6864 }; 6865 }; 6866 6867 port@5 { 6868 reg = <5>; 6869 6870 funnel1_in5: endpoint { 6871 remote-endpoint = <&dlst_funnel_out>; 6872 }; 6873 }; 6874 6875 port@6 { 6876 reg = <6>; 6877 6878 funnel1_in6: endpoint { 6879 remote-endpoint = <&dlct1_funnel_out>; 6880 }; 6881 }; 6882 }; 6883 6884 out-ports { 6885 port { 6886 funnel1_out: endpoint { 6887 remote-endpoint = <&qdss_funnel_in1>; 6888 }; 6889 }; 6890 }; 6891 }; 6892 6893 funnel@10045000 { 6894 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6895 reg = <0x0 0x10045000 0x0 0x1000>; 6896 6897 clocks = <&aoss_qmp>; 6898 clock-names = "apb_pclk"; 6899 6900 in-ports { 6901 #address-cells = <1>; 6902 #size-cells = <0>; 6903 6904 port@0 { 6905 reg = <0>; 6906 6907 qdss_funnel_in0: endpoint { 6908 remote-endpoint = <&funnel0_out>; 6909 }; 6910 }; 6911 6912 port@1 { 6913 reg = <1>; 6914 6915 qdss_funnel_in1: endpoint { 6916 remote-endpoint = <&funnel1_out>; 6917 }; 6918 }; 6919 }; 6920 6921 out-ports { 6922 port { 6923 qdss_funnel_out: endpoint { 6924 remote-endpoint = <&aoss_funnel_in7>; 6925 }; 6926 }; 6927 }; 6928 }; 6929 6930 tpdm@10800000 { 6931 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6932 reg = <0x0 0x10800000 0x0 0x1000>; 6933 6934 clocks = <&aoss_qmp>; 6935 clock-names = "apb_pclk"; 6936 6937 qcom,cmb-element-bits = <64>; 6938 qcom,cmb-msrs-num = <32>; 6939 6940 out-ports { 6941 port { 6942 mxa_tpdm_out: endpoint { 6943 remote-endpoint = <&dlct2_tpda_in15>; 6944 }; 6945 }; 6946 }; 6947 }; 6948 6949 tpdm@1082c000 { 6950 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6951 reg = <0x0 0x1082c000 0x0 0x1000>; 6952 6953 clocks = <&aoss_qmp>; 6954 clock-names = "apb_pclk"; 6955 6956 qcom,dsb-element-bits = <32>; 6957 qcom,dsb-msrs-num = <32>; 6958 6959 out-ports { 6960 port { 6961 gcc_tpdm_out: endpoint { 6962 remote-endpoint = <&dlct1_tpda_in21>; 6963 }; 6964 }; 6965 }; 6966 }; 6967 6968 tpdm@10841000 { 6969 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6970 reg = <0x0 0x10841000 0x0 0x1000>; 6971 6972 clocks = <&aoss_qmp>; 6973 clock-names = "apb_pclk"; 6974 6975 qcom,cmb-element-bits = <32>; 6976 qcom,cmb-msrs-num = <32>; 6977 6978 out-ports { 6979 port { 6980 prng_tpdm_out: endpoint { 6981 remote-endpoint = <&dlct1_tpda_in19>; 6982 }; 6983 }; 6984 }; 6985 }; 6986 6987 tpdm@10844000 { 6988 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6989 reg = <0x0 0x10844000 0x0 0x1000>; 6990 6991 clocks = <&aoss_qmp>; 6992 clock-names = "apb_pclk"; 6993 6994 qcom,dsb-element-bits = <32>; 6995 qcom,dsb-msrs-num = <32>; 6996 6997 out-ports { 6998 port { 6999 lpass_cx_tpdm_out: endpoint { 7000 remote-endpoint = <&lpass_cx_funnel_in0>; 7001 }; 7002 }; 7003 }; 7004 }; 7005 7006 funnel@10846000 { 7007 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7008 reg = <0x0 0x10846000 0x0 0x1000>; 7009 7010 clocks = <&aoss_qmp>; 7011 clock-names = "apb_pclk"; 7012 7013 in-ports { 7014 port { 7015 lpass_cx_funnel_in0: endpoint { 7016 remote-endpoint = <&lpass_cx_tpdm_out>; 7017 }; 7018 }; 7019 }; 7020 7021 out-ports { 7022 port { 7023 lpass_cx_funnel_out: endpoint { 7024 remote-endpoint = <&dlct1_tpda_in4>; 7025 }; 7026 }; 7027 }; 7028 }; 7029 7030 cti@1098b000 { 7031 compatible = "arm,coresight-cti", "arm,primecell"; 7032 reg = <0x0 0x1098b000 0x0 0x1000>; 7033 7034 clocks = <&aoss_qmp>; 7035 clock-names = "apb_pclk"; 7036 }; 7037 7038 tpdm@109d0000 { 7039 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7040 reg = <0x0 0x109d0000 0x0 0x1000>; 7041 7042 clocks = <&aoss_qmp>; 7043 clock-names = "apb_pclk"; 7044 7045 qcom,dsb-element-bits = <32>; 7046 qcom,dsb-msrs-num = <32>; 7047 status = "disabled"; 7048 7049 out-ports { 7050 port { 7051 qm_tpdm_out: endpoint { 7052 remote-endpoint = <&dlct1_tpda_in20>; 7053 }; 7054 }; 7055 }; 7056 }; 7057 7058 tpdm@10ac0000 { 7059 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7060 reg = <0x0 0x10ac0000 0x0 0x1000>; 7061 7062 clocks = <&aoss_qmp>; 7063 clock-names = "apb_pclk"; 7064 7065 qcom,dsb-element-bits = <32>; 7066 qcom,dsb-msrs-num = <32>; 7067 status = "disabled"; 7068 7069 out-ports { 7070 port { 7071 dlst_tpdm0_out: endpoint { 7072 remote-endpoint = <&dlst_tpda_in8>; 7073 }; 7074 }; 7075 }; 7076 }; 7077 7078 tpdm@10ac1000 { 7079 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7080 reg = <0x0 0x10ac1000 0x0 0x1000>; 7081 7082 clocks = <&aoss_qmp>; 7083 clock-names = "apb_pclk"; 7084 7085 qcom,cmb-element-bits = <64>; 7086 qcom,cmb-msrs-num = <32>; 7087 7088 out-ports { 7089 port { 7090 dlst_tpdm1_out: endpoint { 7091 remote-endpoint = <&dlst_tpda_in9>; 7092 }; 7093 }; 7094 }; 7095 }; 7096 7097 tpda@10ac4000 { 7098 compatible = "qcom,coresight-tpda", "arm,primecell"; 7099 reg = <0x0 0x10ac4000 0x0 0x1000>; 7100 7101 clocks = <&aoss_qmp>; 7102 clock-names = "apb_pclk"; 7103 7104 in-ports { 7105 #address-cells = <1>; 7106 #size-cells = <0>; 7107 7108 port@8 { 7109 reg = <8>; 7110 7111 dlst_tpda_in8: endpoint { 7112 remote-endpoint = <&dlst_tpdm0_out>; 7113 }; 7114 }; 7115 7116 port@9 { 7117 reg = <9>; 7118 7119 dlst_tpda_in9: endpoint { 7120 remote-endpoint = <&dlst_tpdm1_out>; 7121 }; 7122 }; 7123 }; 7124 7125 out-ports { 7126 port { 7127 dlst_tpda_out: endpoint { 7128 remote-endpoint = <&dlst_funnel_in0>; 7129 }; 7130 }; 7131 }; 7132 }; 7133 7134 funnel@10ac5000 { 7135 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7136 reg = <0x0 0x10ac5000 0x0 0x1000>; 7137 7138 clocks = <&aoss_qmp>; 7139 clock-names = "apb_pclk"; 7140 7141 in-ports { 7142 port { 7143 dlst_funnel_in0: endpoint { 7144 remote-endpoint = <&dlst_tpda_out>; 7145 }; 7146 }; 7147 }; 7148 7149 out-ports { 7150 port { 7151 dlst_funnel_out: endpoint { 7152 remote-endpoint = <&funnel1_in5>; 7153 }; 7154 }; 7155 }; 7156 }; 7157 7158 funnel@10b04000 { 7159 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7160 reg = <0x0 0x10b04000 0x0 0x1000>; 7161 7162 clocks = <&aoss_qmp>; 7163 clock-names = "apb_pclk"; 7164 7165 in-ports { 7166 #address-cells = <1>; 7167 #size-cells = <0>; 7168 7169 port@3 { 7170 reg = <3>; 7171 7172 aoss_funnel_in3: endpoint { 7173 remote-endpoint = <&ddr_lpi_funnel_out>; 7174 }; 7175 }; 7176 7177 port@6 { 7178 reg = <6>; 7179 7180 aoss_funnel_in6: endpoint { 7181 remote-endpoint = <&aoss_tpda_out>; 7182 }; 7183 }; 7184 7185 port@7 { 7186 reg = <7>; 7187 7188 aoss_funnel_in7: endpoint { 7189 remote-endpoint = <&qdss_funnel_out>; 7190 }; 7191 }; 7192 }; 7193 7194 out-ports { 7195 port { 7196 aoss_funnel_out: endpoint { 7197 remote-endpoint = <&etf0_in>; 7198 }; 7199 }; 7200 }; 7201 }; 7202 7203 etf0: tmc@10b05000 { 7204 compatible = "arm,coresight-tmc", "arm,primecell"; 7205 reg = <0x0 0x10b05000 0x0 0x1000>; 7206 7207 clocks = <&aoss_qmp>; 7208 clock-names = "apb_pclk"; 7209 7210 in-ports { 7211 port { 7212 etf0_in: endpoint { 7213 remote-endpoint = <&aoss_funnel_out>; 7214 }; 7215 }; 7216 }; 7217 7218 out-ports { 7219 port { 7220 etf0_out: endpoint { 7221 remote-endpoint = <&swao_rep_in>; 7222 }; 7223 }; 7224 }; 7225 }; 7226 7227 replicator@10b06000 { 7228 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7229 reg = <0x0 0x10b06000 0x0 0x1000>; 7230 7231 clocks = <&aoss_qmp>; 7232 clock-names = "apb_pclk"; 7233 7234 in-ports { 7235 port { 7236 swao_rep_in: endpoint { 7237 remote-endpoint = <&etf0_out>; 7238 }; 7239 }; 7240 }; 7241 7242 out-ports { 7243 port { 7244 swao_rep_out1: endpoint { 7245 remote-endpoint = <&eud_in>; 7246 }; 7247 }; 7248 }; 7249 }; 7250 7251 tpda@10b08000 { 7252 compatible = "qcom,coresight-tpda", "arm,primecell"; 7253 reg = <0x0 0x10b08000 0x0 0x1000>; 7254 7255 clocks = <&aoss_qmp>; 7256 clock-names = "apb_pclk"; 7257 7258 in-ports { 7259 #address-cells = <1>; 7260 #size-cells = <0>; 7261 7262 port@0 { 7263 reg = <0>; 7264 7265 aoss_tpda_in0: endpoint { 7266 remote-endpoint = <&aoss_tpdm0_out>; 7267 }; 7268 }; 7269 7270 port@1 { 7271 reg = <1>; 7272 7273 aoss_tpda_in1: endpoint { 7274 remote-endpoint = <&aoss_tpdm1_out>; 7275 }; 7276 }; 7277 7278 port@2 { 7279 reg = <2>; 7280 7281 aoss_tpda_in2: endpoint { 7282 remote-endpoint = <&aoss_tpdm2_out>; 7283 }; 7284 }; 7285 7286 port@3 { 7287 reg = <3>; 7288 7289 aoss_tpda_in3: endpoint { 7290 remote-endpoint = <&aoss_tpdm3_out>; 7291 }; 7292 }; 7293 7294 port@4 { 7295 reg = <4>; 7296 7297 aoss_tpda_in4: endpoint { 7298 remote-endpoint = <&aoss_tpdm4_out>; 7299 }; 7300 }; 7301 }; 7302 7303 out-ports { 7304 port { 7305 aoss_tpda_out: endpoint { 7306 remote-endpoint = <&aoss_funnel_in6>; 7307 }; 7308 }; 7309 }; 7310 }; 7311 7312 tpdm@10b09000 { 7313 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7314 reg = <0x0 0x10b09000 0x0 0x1000>; 7315 7316 clocks = <&aoss_qmp>; 7317 clock-names = "apb_pclk"; 7318 7319 qcom,cmb-element-bits = <64>; 7320 qcom,cmb-msrs-num = <32>; 7321 7322 out-ports { 7323 port { 7324 aoss_tpdm0_out: endpoint { 7325 remote-endpoint = <&aoss_tpda_in0>; 7326 }; 7327 }; 7328 }; 7329 }; 7330 7331 tpdm@10b0a000 { 7332 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7333 reg = <0x0 0x10b0a000 0x0 0x1000>; 7334 7335 clocks = <&aoss_qmp>; 7336 clock-names = "apb_pclk"; 7337 7338 qcom,cmb-element-bits = <64>; 7339 qcom,cmb-msrs-num = <32>; 7340 7341 out-ports { 7342 port { 7343 aoss_tpdm1_out: endpoint { 7344 remote-endpoint = <&aoss_tpda_in1>; 7345 }; 7346 }; 7347 }; 7348 }; 7349 7350 tpdm@10b0b000 { 7351 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7352 reg = <0x0 0x10b0b000 0x0 0x1000>; 7353 7354 clocks = <&aoss_qmp>; 7355 clock-names = "apb_pclk"; 7356 7357 qcom,cmb-element-bits = <64>; 7358 qcom,cmb-msrs-num = <32>; 7359 7360 out-ports { 7361 port { 7362 aoss_tpdm2_out: endpoint { 7363 remote-endpoint = <&aoss_tpda_in2>; 7364 }; 7365 }; 7366 }; 7367 }; 7368 7369 tpdm@10b0c000 { 7370 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7371 reg = <0x0 0x10b0c000 0x0 0x1000>; 7372 7373 clocks = <&aoss_qmp>; 7374 clock-names = "apb_pclk"; 7375 7376 qcom,cmb-element-bits = <64>; 7377 qcom,cmb-msrs-num = <32>; 7378 7379 out-ports { 7380 port { 7381 aoss_tpdm3_out: endpoint { 7382 remote-endpoint = <&aoss_tpda_in3>; 7383 }; 7384 }; 7385 }; 7386 }; 7387 7388 tpdm@10b0d000 { 7389 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7390 reg = <0x0 0x10b0d000 0x0 0x1000>; 7391 7392 clocks = <&aoss_qmp>; 7393 clock-names = "apb_pclk"; 7394 7395 qcom,dsb-element-bits = <32>; 7396 qcom,dsb-msrs-num = <32>; 7397 7398 out-ports { 7399 port { 7400 aoss_tpdm4_out: endpoint { 7401 remote-endpoint = <&aoss_tpda_in4>; 7402 }; 7403 }; 7404 }; 7405 }; 7406 7407 tpdm@10b20000 { 7408 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7409 reg = <0x0 0x10b20000 0x0 0x1000>; 7410 7411 clocks = <&aoss_qmp>; 7412 clock-names = "apb_pclk"; 7413 7414 qcom,dsb-element-bits = <32>; 7415 qcom,dsb-msrs-num = <32>; 7416 status = "disabled"; 7417 7418 out-ports { 7419 port { 7420 lpicc_tpdm_out: endpoint { 7421 remote-endpoint = <&ddr_lpi_tpda_in>; 7422 }; 7423 }; 7424 }; 7425 }; 7426 7427 tpda@10b23000 { 7428 compatible = "qcom,coresight-tpda", "arm,primecell"; 7429 reg = <0x0 0x10b23000 0x0 0x1000>; 7430 7431 clocks = <&aoss_qmp>; 7432 clock-names = "apb_pclk"; 7433 status = "disabled"; 7434 7435 in-ports { 7436 port { 7437 ddr_lpi_tpda_in: endpoint { 7438 remote-endpoint = <&lpicc_tpdm_out>; 7439 }; 7440 }; 7441 }; 7442 7443 out-ports { 7444 port { 7445 ddr_lpi_tpda_out: endpoint { 7446 remote-endpoint = <&ddr_lpi_funnel_in0>; 7447 }; 7448 }; 7449 }; 7450 }; 7451 7452 funnel@10b24000 { 7453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7454 reg = <0x0 0x10b24000 0x0 0x1000>; 7455 7456 clocks = <&aoss_qmp>; 7457 clock-names = "apb_pclk"; 7458 status = "disabled"; 7459 7460 in-ports { 7461 port { 7462 ddr_lpi_funnel_in0: endpoint { 7463 remote-endpoint = <&ddr_lpi_tpda_out>; 7464 }; 7465 }; 7466 }; 7467 7468 out-ports { 7469 port { 7470 ddr_lpi_funnel_out: endpoint { 7471 remote-endpoint = <&aoss_funnel_in3>; 7472 }; 7473 }; 7474 }; 7475 }; 7476 7477 tpdm@10c08000 { 7478 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7479 reg = <0x0 0x10c08000 0x0 0x1000>; 7480 7481 clocks = <&aoss_qmp>; 7482 clock-names = "apb_pclk"; 7483 7484 qcom,dsb-element-bits = <32>; 7485 qcom,dsb-msrs-num = <32>; 7486 7487 out-ports { 7488 port { 7489 mm_tpdm_out: endpoint { 7490 remote-endpoint = <&mm_funnel_in4>; 7491 }; 7492 }; 7493 }; 7494 }; 7495 7496 funnel@10c0b000 { 7497 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7498 reg = <0x0 0x10c0b000 0x0 0x1000>; 7499 7500 clocks = <&aoss_qmp>; 7501 clock-names = "apb_pclk"; 7502 7503 in-ports { 7504 #address-cells = <1>; 7505 #size-cells = <0>; 7506 7507 port@4 { 7508 reg = <4>; 7509 7510 mm_funnel_in4: endpoint { 7511 remote-endpoint = <&mm_tpdm_out>; 7512 }; 7513 }; 7514 }; 7515 7516 out-ports { 7517 port { 7518 mm_funnel_out: endpoint { 7519 remote-endpoint = <&dlct2_tpda_in4>; 7520 }; 7521 }; 7522 }; 7523 }; 7524 7525 tpdm@10c28000 { 7526 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7527 reg = <0x0 0x10c28000 0x0 0x1000>; 7528 7529 clocks = <&aoss_qmp>; 7530 clock-names = "apb_pclk"; 7531 7532 qcom,dsb-element-bits = <32>; 7533 qcom,dsb-msrs-num = <32>; 7534 7535 out-ports { 7536 port { 7537 dlct1_tpdm_out: endpoint { 7538 remote-endpoint = <&dlct1_tpda_in26>; 7539 }; 7540 }; 7541 }; 7542 }; 7543 7544 tpdm@10c29000 { 7545 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7546 reg = <0x0 0x10c29000 0x0 0x1000>; 7547 7548 clocks = <&aoss_qmp>; 7549 clock-names = "apb_pclk"; 7550 7551 qcom,cmb-element-bits = <64>; 7552 qcom,cmb-msrs-num = <32>; 7553 7554 out-ports { 7555 port { 7556 ipcc_tpdm_out: endpoint { 7557 remote-endpoint = <&dlct1_tpda_in27>; 7558 }; 7559 }; 7560 }; 7561 }; 7562 7563 tpda@10c2b000 { 7564 compatible = "qcom,coresight-tpda", "arm,primecell"; 7565 reg = <0x0 0x10c2b000 0x0 0x1000>; 7566 7567 clocks = <&aoss_qmp>; 7568 clock-names = "apb_pclk"; 7569 7570 in-ports { 7571 #address-cells = <1>; 7572 #size-cells = <0>; 7573 7574 port@4 { 7575 reg = <4>; 7576 7577 dlct1_tpda_in4: endpoint { 7578 remote-endpoint = <&lpass_cx_funnel_out>; 7579 }; 7580 }; 7581 7582 port@13 { 7583 reg = <19>; 7584 7585 dlct1_tpda_in19: endpoint { 7586 remote-endpoint = <&prng_tpdm_out>; 7587 }; 7588 }; 7589 7590 port@14 { 7591 reg = <20>; 7592 7593 dlct1_tpda_in20: endpoint { 7594 remote-endpoint = <&qm_tpdm_out>; 7595 }; 7596 }; 7597 7598 port@15 { 7599 reg = <21>; 7600 7601 dlct1_tpda_in21: endpoint { 7602 remote-endpoint = <&gcc_tpdm_out>; 7603 }; 7604 }; 7605 7606 port@1a { 7607 reg = <26>; 7608 7609 dlct1_tpda_in26: endpoint { 7610 remote-endpoint = <&dlct1_tpdm_out>; 7611 }; 7612 }; 7613 7614 port@1b { 7615 reg = <27>; 7616 7617 dlct1_tpda_in27: endpoint { 7618 remote-endpoint = <&ipcc_tpdm_out>; 7619 }; 7620 }; 7621 }; 7622 7623 out-ports { 7624 port { 7625 dlct1_tpda_out: endpoint { 7626 remote-endpoint = <&dlct1_funnel_in0>; 7627 }; 7628 }; 7629 }; 7630 }; 7631 7632 funnel@10c2c000 { 7633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7634 reg = <0x0 0x10c2c000 0x0 0x1000>; 7635 7636 clocks = <&aoss_qmp>; 7637 clock-names = "apb_pclk"; 7638 7639 in-ports { 7640 #address-cells = <1>; 7641 #size-cells = <0>; 7642 7643 port@0 { 7644 reg = <0>; 7645 7646 dlct1_funnel_in0: endpoint { 7647 remote-endpoint = <&dlct1_tpda_out>; 7648 }; 7649 }; 7650 7651 port@4 { 7652 reg = <4>; 7653 7654 dlct1_funnel_in4: endpoint { 7655 remote-endpoint = <&dlct2_funnel_out>; 7656 }; 7657 }; 7658 7659 port@5 { 7660 reg = <5>; 7661 7662 dlct1_funnel_in5: endpoint { 7663 remote-endpoint = <&ddr_funnel0_out>; 7664 }; 7665 }; 7666 }; 7667 7668 out-ports { 7669 port { 7670 dlct1_funnel_out: endpoint { 7671 remote-endpoint = <&funnel1_in6>; 7672 }; 7673 }; 7674 }; 7675 }; 7676 7677 tpdm@10c38000 { 7678 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7679 reg = <0x0 0x10c38000 0x0 0x1000>; 7680 7681 clocks = <&aoss_qmp>; 7682 clock-names = "apb_pclk"; 7683 7684 qcom,cmb-element-bits = <64>; 7685 qcom,cmb-msrs-num = <32>; 7686 7687 out-ports { 7688 port { 7689 dlct2_tpdm0_out: endpoint { 7690 remote-endpoint = <&dlct2_tpda_in16>; 7691 }; 7692 }; 7693 }; 7694 }; 7695 7696 tpdm@10c39000 { 7697 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7698 reg = <0x0 0x10c39000 0x0 0x1000>; 7699 7700 clocks = <&aoss_qmp>; 7701 clock-names = "apb_pclk"; 7702 7703 qcom,cmb-element-bits = <64>; 7704 qcom,cmb-msrs-num = <32>; 7705 7706 out-ports { 7707 port { 7708 dlct2_tpdm1_out: endpoint { 7709 remote-endpoint = <&dlct2_tpda_in17>; 7710 }; 7711 }; 7712 }; 7713 }; 7714 7715 tpda@10c3c000 { 7716 compatible = "qcom,coresight-tpda", "arm,primecell"; 7717 reg = <0x0 0x10c3c000 0x0 0x1000>; 7718 7719 clocks = <&aoss_qmp>; 7720 clock-names = "apb_pclk"; 7721 7722 in-ports { 7723 #address-cells = <1>; 7724 #size-cells = <0>; 7725 7726 port@4 { 7727 reg = <4>; 7728 7729 dlct2_tpda_in4: endpoint { 7730 remote-endpoint = <&mm_funnel_out>; 7731 }; 7732 }; 7733 7734 port@f { 7735 reg = <15>; 7736 7737 dlct2_tpda_in15: endpoint { 7738 remote-endpoint = <&mxa_tpdm_out>; 7739 }; 7740 }; 7741 7742 port@10 { 7743 reg = <16>; 7744 7745 dlct2_tpda_in16: endpoint { 7746 remote-endpoint = <&dlct2_tpdm0_out>; 7747 }; 7748 }; 7749 7750 port@11 { 7751 reg = <17>; 7752 7753 dlct2_tpda_in17: endpoint { 7754 remote-endpoint = <&dlct2_tpdm1_out>; 7755 }; 7756 }; 7757 }; 7758 7759 out-ports { 7760 port { 7761 dlct2_tpda_out: endpoint { 7762 remote-endpoint = <&dlct2_funnel_in0>; 7763 }; 7764 }; 7765 }; 7766 }; 7767 7768 funnel@10c3d000 { 7769 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7770 reg = <0x0 0x10c3d000 0x0 0x1000>; 7771 7772 clocks = <&aoss_qmp>; 7773 clock-names = "apb_pclk"; 7774 7775 in-ports { 7776 port { 7777 dlct2_funnel_in0: endpoint { 7778 remote-endpoint = <&dlct2_tpda_out>; 7779 }; 7780 }; 7781 }; 7782 7783 out-ports { 7784 port { 7785 dlct2_funnel_out: endpoint { 7786 remote-endpoint = <&dlct1_funnel_in4>; 7787 }; 7788 }; 7789 }; 7790 }; 7791 7792 tpdm@10cc1000 { 7793 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7794 reg = <0x0 0x10cc1000 0x0 0x1000>; 7795 7796 clocks = <&aoss_qmp>; 7797 clock-names = "apb_pclk"; 7798 7799 qcom,cmb-element-bits = <64>; 7800 qcom,cmb-msrs-num = <32>; 7801 qcom,dsb-element-bits = <32>; 7802 qcom,dsb-msrs-num = <32>; 7803 status = "disabled"; 7804 7805 out-ports { 7806 port { 7807 tmess_tpdm1_out: endpoint { 7808 remote-endpoint = <&tmess_tpda_in2>; 7809 }; 7810 }; 7811 }; 7812 }; 7813 7814 tpda@10cc4000 { 7815 compatible = "qcom,coresight-tpda", "arm,primecell"; 7816 reg = <0x0 0x10cc4000 0x0 0x1000>; 7817 7818 clocks = <&aoss_qmp>; 7819 clock-names = "apb_pclk"; 7820 7821 in-ports { 7822 #address-cells = <1>; 7823 #size-cells = <0>; 7824 7825 port@2 { 7826 reg = <2>; 7827 7828 tmess_tpda_in2: endpoint { 7829 remote-endpoint = <&tmess_tpdm1_out>; 7830 }; 7831 }; 7832 }; 7833 7834 out-ports { 7835 port { 7836 tmess_tpda_out: endpoint { 7837 remote-endpoint = <&tmess_funnel_in0>; 7838 }; 7839 }; 7840 }; 7841 }; 7842 7843 funnel@10cc5000 { 7844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7845 reg = <0x0 0x10cc5000 0x0 0x1000>; 7846 7847 clocks = <&aoss_qmp>; 7848 clock-names = "apb_pclk"; 7849 7850 in-ports { 7851 port { 7852 tmess_funnel_in0: endpoint { 7853 remote-endpoint = <&tmess_tpda_out>; 7854 }; 7855 }; 7856 }; 7857 7858 out-ports { 7859 port { 7860 tmess_funnel_out: endpoint { 7861 remote-endpoint = <&funnel1_in2>; 7862 }; 7863 }; 7864 }; 7865 }; 7866 7867 funnel@10d04000 { 7868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7869 reg = <0x0 0x10d04000 0x0 0x1000>; 7870 7871 clocks = <&aoss_qmp>; 7872 clock-names = "apb_pclk"; 7873 7874 in-ports { 7875 #address-cells = <1>; 7876 #size-cells = <0>; 7877 7878 port@6 { 7879 reg = <6>; 7880 7881 ddr_funnel0_in6: endpoint { 7882 remote-endpoint = <&ddr_funnel1_out>; 7883 }; 7884 }; 7885 }; 7886 7887 out-ports { 7888 port { 7889 ddr_funnel0_out: endpoint { 7890 remote-endpoint = <&dlct1_funnel_in5>; 7891 }; 7892 }; 7893 }; 7894 }; 7895 7896 tpdm@10d08000 { 7897 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7898 reg = <0x0 0x10d08000 0x0 0x1000>; 7899 7900 clocks = <&aoss_qmp>; 7901 clock-names = "apb_pclk"; 7902 7903 qcom,cmb-element-bits = <32>; 7904 qcom,cmb-msrs-num = <32>; 7905 7906 out-ports { 7907 port { 7908 llcc0_tpdm_out: endpoint { 7909 remote-endpoint = <&llcc_tpda_in0>; 7910 }; 7911 }; 7912 }; 7913 }; 7914 7915 tpdm@10d09000 { 7916 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7917 reg = <0x0 0x10d09000 0x0 0x1000>; 7918 7919 clocks = <&aoss_qmp>; 7920 clock-names = "apb_pclk"; 7921 7922 qcom,cmb-element-bits = <32>; 7923 qcom,cmb-msrs-num = <32>; 7924 7925 out-ports { 7926 port { 7927 llcc1_tpdm_out: endpoint { 7928 remote-endpoint = <&llcc_tpda_in1>; 7929 }; 7930 }; 7931 }; 7932 }; 7933 7934 tpdm@10d0a000 { 7935 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7936 reg = <0x0 0x10d0a000 0x0 0x1000>; 7937 7938 clocks = <&aoss_qmp>; 7939 clock-names = "apb_pclk"; 7940 7941 qcom,cmb-element-bits = <32>; 7942 qcom,cmb-msrs-num = <32>; 7943 7944 out-ports { 7945 port { 7946 llcc2_tpdm_out: endpoint { 7947 remote-endpoint = <&llcc_tpda_in2>; 7948 }; 7949 }; 7950 }; 7951 }; 7952 7953 tpdm@10d0b000 { 7954 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7955 reg = <0x0 0x10d0b000 0x0 0x1000>; 7956 7957 clocks = <&aoss_qmp>; 7958 clock-names = "apb_pclk"; 7959 7960 qcom,cmb-element-bits = <32>; 7961 qcom,cmb-msrs-num = <32>; 7962 7963 out-ports { 7964 port { 7965 llcc3_tpdm_out: endpoint { 7966 remote-endpoint = <&llcc_tpda_in3>; 7967 }; 7968 }; 7969 }; 7970 }; 7971 7972 tpdm@10d0c000 { 7973 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7974 reg = <0x0 0x10d0c000 0x0 0x1000>; 7975 7976 clocks = <&aoss_qmp>; 7977 clock-names = "apb_pclk"; 7978 7979 qcom,cmb-element-bits = <32>; 7980 qcom,cmb-msrs-num = <32>; 7981 7982 out-ports { 7983 port { 7984 llcc4_tpdm_out: endpoint { 7985 remote-endpoint = <&llcc_tpda_in4>; 7986 }; 7987 }; 7988 }; 7989 }; 7990 7991 tpdm@10d0d000 { 7992 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7993 reg = <0x0 0x10d0d000 0x0 0x1000>; 7994 7995 clocks = <&aoss_qmp>; 7996 clock-names = "apb_pclk"; 7997 7998 qcom,cmb-element-bits = <32>; 7999 qcom,cmb-msrs-num = <32>; 8000 8001 out-ports { 8002 port { 8003 llcc5_tpdm_out: endpoint { 8004 remote-endpoint = <&llcc_tpda_in5>; 8005 }; 8006 }; 8007 }; 8008 }; 8009 8010 tpdm@10d0e000 { 8011 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8012 reg = <0x0 0x10d0e000 0x0 0x1000>; 8013 8014 clocks = <&aoss_qmp>; 8015 clock-names = "apb_pclk"; 8016 8017 qcom,cmb-element-bits = <32>; 8018 qcom,cmb-msrs-num = <32>; 8019 8020 out-ports { 8021 port { 8022 llcc6_tpdm_out: endpoint { 8023 remote-endpoint = <&llcc_tpda_in6>; 8024 }; 8025 }; 8026 }; 8027 }; 8028 8029 tpdm@10d0f000 { 8030 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8031 reg = <0x0 0x10d0f000 0x0 0x1000>; 8032 8033 clocks = <&aoss_qmp>; 8034 clock-names = "apb_pclk"; 8035 8036 qcom,cmb-element-bits = <32>; 8037 qcom,cmb-msrs-num = <32>; 8038 8039 out-ports { 8040 port { 8041 llcc7_tpdm_out: endpoint { 8042 remote-endpoint = <&llcc_tpda_in7>; 8043 }; 8044 }; 8045 }; 8046 }; 8047 8048 tpda@10d12000 { 8049 compatible = "qcom,coresight-tpda", "arm,primecell"; 8050 reg = <0x0 0x10d12000 0x0 0x1000>; 8051 8052 clocks = <&aoss_qmp>; 8053 clock-names = "apb_pclk"; 8054 8055 in-ports { 8056 #address-cells = <1>; 8057 #size-cells = <0>; 8058 8059 port@0 { 8060 reg = <0>; 8061 8062 llcc_tpda_in0: endpoint { 8063 remote-endpoint = <&llcc0_tpdm_out>; 8064 }; 8065 }; 8066 8067 port@1 { 8068 reg = <1>; 8069 8070 llcc_tpda_in1: endpoint { 8071 remote-endpoint = <&llcc1_tpdm_out>; 8072 }; 8073 }; 8074 8075 port@2 { 8076 reg = <2>; 8077 8078 llcc_tpda_in2: endpoint { 8079 remote-endpoint = <&llcc2_tpdm_out>; 8080 }; 8081 }; 8082 8083 port@3 { 8084 reg = <3>; 8085 8086 llcc_tpda_in3: endpoint { 8087 remote-endpoint = <&llcc3_tpdm_out>; 8088 }; 8089 }; 8090 8091 port@4 { 8092 reg = <4>; 8093 8094 llcc_tpda_in4: endpoint { 8095 remote-endpoint = <&llcc4_tpdm_out>; 8096 }; 8097 }; 8098 8099 port@5 { 8100 reg = <5>; 8101 8102 llcc_tpda_in5: endpoint { 8103 remote-endpoint = <&llcc5_tpdm_out>; 8104 }; 8105 }; 8106 8107 port@6 { 8108 reg = <6>; 8109 8110 llcc_tpda_in6: endpoint { 8111 remote-endpoint = <&llcc6_tpdm_out>; 8112 }; 8113 }; 8114 8115 port@7 { 8116 reg = <7>; 8117 8118 llcc_tpda_in7: endpoint { 8119 remote-endpoint = <&llcc7_tpdm_out>; 8120 }; 8121 }; 8122 }; 8123 8124 out-ports { 8125 port { 8126 llcc_tpda_out: endpoint { 8127 remote-endpoint = <&ddr_funnel1_in0>; 8128 }; 8129 }; 8130 }; 8131 }; 8132 8133 funnel@10d13000 { 8134 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8135 reg = <0x0 0x10d13000 0x0 0x1000>; 8136 8137 clocks = <&aoss_qmp>; 8138 clock-names = "apb_pclk"; 8139 8140 in-ports { 8141 port { 8142 ddr_funnel1_in0: endpoint { 8143 remote-endpoint = <&llcc_tpda_out>; 8144 }; 8145 }; 8146 }; 8147 8148 out-ports { 8149 port { 8150 ddr_funnel1_out: endpoint { 8151 remote-endpoint = <&ddr_funnel0_in6>; 8152 }; 8153 }; 8154 }; 8155 }; 8156 8157 apps_smmu: iommu@15000000 { 8158 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 8159 reg = <0 0x15000000 0 0x100000>; 8160 8161 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8162 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8163 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8164 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8165 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8166 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8167 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8168 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8169 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8170 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8171 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8172 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8173 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8174 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8175 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8176 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8177 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8178 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8179 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8180 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8181 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8182 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8183 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8184 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8185 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8186 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8187 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8188 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8189 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8190 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8191 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8192 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8193 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8194 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8195 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8196 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8197 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8198 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8199 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8200 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8201 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8202 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8203 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8204 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8205 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8206 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8207 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8208 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8209 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8210 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8211 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8212 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8213 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8214 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8215 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8216 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8217 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8218 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8219 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8220 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8221 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8222 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8223 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8224 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8225 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8226 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8227 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8228 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8229 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8230 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8231 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8232 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8233 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8234 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8235 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8236 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8237 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8238 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8239 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8240 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8241 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8242 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8243 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8244 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8245 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8246 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8247 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8248 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8249 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8250 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8251 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8252 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8253 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8254 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8255 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8256 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8257 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 8258 8259 #iommu-cells = <2>; 8260 #global-interrupts = <1>; 8261 8262 dma-coherent; 8263 }; 8264 8265 pcie_smmu: iommu@15400000 { 8266 compatible = "arm,smmu-v3"; 8267 reg = <0 0x15400000 0 0x80000>; 8268 #iommu-cells = <1>; 8269 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8270 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8271 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8272 interrupt-names = "eventq", 8273 "gerror", 8274 "cmdq-sync"; 8275 dma-coherent; 8276 status = "reserved"; /* Controlled by Gunyah. */ 8277 }; 8278 8279 intc: interrupt-controller@17000000 { 8280 compatible = "arm,gic-v3"; 8281 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8282 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8283 8284 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8285 8286 #interrupt-cells = <3>; 8287 interrupt-controller; 8288 8289 #redistributor-regions = <1>; 8290 redistributor-stride = <0x0 0x40000>; 8291 8292 #address-cells = <2>; 8293 #size-cells = <2>; 8294 ranges; 8295 8296 gic_its: msi-controller@17040000 { 8297 compatible = "arm,gic-v3-its"; 8298 reg = <0 0x17040000 0 0x40000>; 8299 8300 msi-controller; 8301 #msi-cells = <1>; 8302 }; 8303 }; 8304 8305 cpucp_mbox: mailbox@17430000 { 8306 compatible = "qcom,x1e80100-cpucp-mbox"; 8307 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8308 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8309 #mbox-cells = <1>; 8310 }; 8311 8312 apps_rsc: rsc@17500000 { 8313 compatible = "qcom,rpmh-rsc"; 8314 reg = <0 0x17500000 0 0x10000>, 8315 <0 0x17510000 0 0x10000>, 8316 <0 0x17520000 0 0x10000>; 8317 reg-names = "drv-0", "drv-1", "drv-2"; 8318 8319 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8320 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8321 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8322 qcom,tcs-offset = <0xd00>; 8323 qcom,drv-id = <2>; 8324 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8325 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8326 8327 label = "apps_rsc"; 8328 power-domains = <&system_pd>; 8329 8330 apps_bcm_voter: bcm-voter { 8331 compatible = "qcom,bcm-voter"; 8332 }; 8333 8334 rpmhcc: clock-controller { 8335 compatible = "qcom,x1e80100-rpmh-clk"; 8336 8337 clocks = <&xo_board>; 8338 clock-names = "xo"; 8339 8340 #clock-cells = <1>; 8341 }; 8342 8343 rpmhpd: power-controller { 8344 compatible = "qcom,x1e80100-rpmhpd"; 8345 8346 operating-points-v2 = <&rpmhpd_opp_table>; 8347 8348 #power-domain-cells = <1>; 8349 8350 rpmhpd_opp_table: opp-table { 8351 compatible = "operating-points-v2"; 8352 8353 rpmhpd_opp_ret: opp-16 { 8354 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8355 }; 8356 8357 rpmhpd_opp_min_svs: opp-48 { 8358 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8359 }; 8360 8361 rpmhpd_opp_low_svs_d2: opp-52 { 8362 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8363 }; 8364 8365 rpmhpd_opp_low_svs_d1: opp-56 { 8366 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8367 }; 8368 8369 rpmhpd_opp_low_svs_d0: opp-60 { 8370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8371 }; 8372 8373 rpmhpd_opp_low_svs: opp-64 { 8374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8375 }; 8376 8377 rpmhpd_opp_low_svs_l1: opp-80 { 8378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8379 }; 8380 8381 rpmhpd_opp_svs: opp-128 { 8382 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8383 }; 8384 8385 rpmhpd_opp_svs_l0: opp-144 { 8386 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8387 }; 8388 8389 rpmhpd_opp_svs_l1: opp-192 { 8390 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8391 }; 8392 8393 rpmhpd_opp_nom: opp-256 { 8394 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8395 }; 8396 8397 rpmhpd_opp_nom_l1: opp-320 { 8398 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8399 }; 8400 8401 rpmhpd_opp_nom_l2: opp-336 { 8402 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8403 }; 8404 8405 rpmhpd_opp_turbo: opp-384 { 8406 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8407 }; 8408 8409 rpmhpd_opp_turbo_l1: opp-416 { 8410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8411 }; 8412 }; 8413 }; 8414 }; 8415 8416 timer@17800000 { 8417 compatible = "arm,armv7-timer-mem"; 8418 reg = <0 0x17800000 0 0x1000>; 8419 8420 #address-cells = <2>; 8421 #size-cells = <1>; 8422 ranges = <0 0 0 0 0x20000000>; 8423 8424 frame@17801000 { 8425 reg = <0 0x17801000 0x1000>, 8426 <0 0x17802000 0x1000>; 8427 8428 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8429 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8430 8431 frame-number = <0>; 8432 }; 8433 8434 frame@17803000 { 8435 reg = <0 0x17803000 0x1000>; 8436 8437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8438 8439 frame-number = <1>; 8440 8441 status = "disabled"; 8442 }; 8443 8444 frame@17805000 { 8445 reg = <0 0x17805000 0x1000>; 8446 8447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8448 8449 frame-number = <2>; 8450 8451 status = "disabled"; 8452 }; 8453 8454 frame@17807000 { 8455 reg = <0 0x17807000 0x1000>; 8456 8457 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8458 8459 frame-number = <3>; 8460 8461 status = "disabled"; 8462 }; 8463 8464 frame@17809000 { 8465 reg = <0 0x17809000 0x1000>; 8466 8467 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8468 8469 frame-number = <4>; 8470 8471 status = "disabled"; 8472 }; 8473 8474 frame@1780b000 { 8475 reg = <0 0x1780b000 0x1000>; 8476 8477 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8478 8479 frame-number = <5>; 8480 8481 status = "disabled"; 8482 }; 8483 8484 frame@1780d000 { 8485 reg = <0 0x1780d000 0x1000>; 8486 8487 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8488 8489 frame-number = <6>; 8490 8491 status = "disabled"; 8492 }; 8493 }; 8494 8495 sram: sram@18b4e000 { 8496 compatible = "mmio-sram"; 8497 reg = <0x0 0x18b4e000 0x0 0x400>; 8498 8499 #address-cells = <1>; 8500 #size-cells = <1>; 8501 ranges = <0x0 0x0 0x18b4e000 0x400>; 8502 8503 cpu_scp_lpri0: scp-sram-section@0 { 8504 compatible = "arm,scmi-shmem"; 8505 reg = <0x0 0x200>; 8506 }; 8507 8508 cpu_scp_lpri1: scp-sram-section@200 { 8509 compatible = "arm,scmi-shmem"; 8510 reg = <0x200 0x200>; 8511 }; 8512 }; 8513 8514 sbsa_watchdog: watchdog@1c840000 { 8515 compatible = "arm,sbsa-gwdt"; 8516 reg = <0 0x1c840000 0 0x1000>, 8517 <0 0x1c850000 0 0x1000>; 8518 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8519 }; 8520 8521 qfprom: efuse@221c8000 { 8522 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; 8523 reg = <0 0x221c8000 0 0x1000>; 8524 #address-cells = <1>; 8525 #size-cells = <1>; 8526 8527 gpu_speed_bin: gpu-speed-bin@119 { 8528 reg = <0x119 0x2>; 8529 bits = <7 8>; 8530 }; 8531 }; 8532 8533 pmu@24091000 { 8534 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8535 reg = <0 0x24091000 0 0x1000>; 8536 8537 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8538 8539 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8540 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8541 8542 operating-points-v2 = <&llcc_bwmon_opp_table>; 8543 8544 llcc_bwmon_opp_table: opp-table { 8545 compatible = "operating-points-v2"; 8546 8547 opp-0 { 8548 opp-peak-kBps = <800000>; 8549 }; 8550 8551 opp-1 { 8552 opp-peak-kBps = <2188000>; 8553 }; 8554 8555 opp-2 { 8556 opp-peak-kBps = <3072000>; 8557 }; 8558 8559 opp-3 { 8560 opp-peak-kBps = <6220800>; 8561 }; 8562 8563 opp-4 { 8564 opp-peak-kBps = <6835200>; 8565 }; 8566 8567 opp-5 { 8568 opp-peak-kBps = <8371200>; 8569 }; 8570 8571 opp-6 { 8572 opp-peak-kBps = <10944000>; 8573 }; 8574 8575 opp-7 { 8576 opp-peak-kBps = <12748800>; 8577 }; 8578 8579 opp-8 { 8580 opp-peak-kBps = <14745600>; 8581 }; 8582 8583 opp-9 { 8584 opp-peak-kBps = <16896000>; 8585 }; 8586 }; 8587 }; 8588 8589 /* cluster0 */ 8590 bwmon_cluster0: pmu@240b3400 { 8591 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8592 reg = <0 0x240b3400 0 0x600>; 8593 8594 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8595 8596 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8597 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8598 8599 operating-points-v2 = <&cpu_bwmon_opp_table>; 8600 }; 8601 8602 /* cluster2 */ 8603 bwmon_cluster2: pmu@240b5400 { 8604 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8605 reg = <0 0x240b5400 0 0x600>; 8606 8607 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8608 8609 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8610 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8611 8612 operating-points-v2 = <&cpu_bwmon_opp_table>; 8613 8614 cpu_bwmon_opp_table: opp-table { 8615 compatible = "operating-points-v2"; 8616 8617 opp-0 { 8618 opp-peak-kBps = <4800000>; 8619 }; 8620 8621 opp-1 { 8622 opp-peak-kBps = <7464000>; 8623 }; 8624 8625 opp-2 { 8626 opp-peak-kBps = <9600000>; 8627 }; 8628 8629 opp-3 { 8630 opp-peak-kBps = <12896000>; 8631 }; 8632 8633 opp-4 { 8634 opp-peak-kBps = <14928000>; 8635 }; 8636 8637 opp-5 { 8638 opp-peak-kBps = <17064000>; 8639 }; 8640 }; 8641 }; 8642 8643 /* cluster1 */ 8644 pmu@240b6400 { 8645 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8646 reg = <0 0x240b6400 0 0x600>; 8647 8648 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8649 8650 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8651 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8652 8653 operating-points-v2 = <&cpu_bwmon_opp_table>; 8654 }; 8655 8656 system-cache-controller@25000000 { 8657 compatible = "qcom,x1e80100-llcc"; 8658 reg = <0 0x25000000 0 0x200000>, 8659 <0 0x25200000 0 0x200000>, 8660 <0 0x25400000 0 0x200000>, 8661 <0 0x25600000 0 0x200000>, 8662 <0 0x25800000 0 0x200000>, 8663 <0 0x25a00000 0 0x200000>, 8664 <0 0x25c00000 0 0x200000>, 8665 <0 0x25e00000 0 0x200000>, 8666 <0 0x26000000 0 0x200000>, 8667 <0 0x26200000 0 0x200000>; 8668 reg-names = "llcc0_base", 8669 "llcc1_base", 8670 "llcc2_base", 8671 "llcc3_base", 8672 "llcc4_base", 8673 "llcc5_base", 8674 "llcc6_base", 8675 "llcc7_base", 8676 "llcc_broadcast_base", 8677 "llcc_broadcast_and_base"; 8678 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8679 }; 8680 8681 remoteproc_cdsp: remoteproc@32300000 { 8682 compatible = "qcom,x1e80100-cdsp-pas"; 8683 reg = <0x0 0x32300000 0x0 0x10000>; 8684 8685 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8686 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8687 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8688 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8689 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8690 interrupt-names = "wdog", 8691 "fatal", 8692 "ready", 8693 "handover", 8694 "stop-ack"; 8695 8696 clocks = <&rpmhcc RPMH_CXO_CLK>; 8697 clock-names = "xo"; 8698 8699 power-domains = <&rpmhpd RPMHPD_CX>, 8700 <&rpmhpd RPMHPD_MXC>, 8701 <&rpmhpd RPMHPD_NSP>; 8702 power-domain-names = "cx", 8703 "mxc", 8704 "nsp"; 8705 8706 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8707 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8708 8709 memory-region = <&cdsp_mem>, 8710 <&q6_cdsp_dtb_mem>; 8711 8712 qcom,qmp = <&aoss_qmp>; 8713 8714 qcom,smem-states = <&smp2p_cdsp_out 0>; 8715 qcom,smem-state-names = "stop"; 8716 8717 status = "disabled"; 8718 8719 glink-edge { 8720 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8721 IPCC_MPROC_SIGNAL_GLINK_QMP 8722 IRQ_TYPE_EDGE_RISING>; 8723 mboxes = <&ipcc IPCC_CLIENT_CDSP 8724 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8725 8726 label = "cdsp"; 8727 qcom,remote-pid = <5>; 8728 8729 fastrpc { 8730 compatible = "qcom,fastrpc"; 8731 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8732 label = "cdsp"; 8733 qcom,non-secure-domain; 8734 #address-cells = <1>; 8735 #size-cells = <0>; 8736 8737 compute-cb@1 { 8738 compatible = "qcom,fastrpc-compute-cb"; 8739 reg = <1>; 8740 iommus = <&apps_smmu 0x0c01 0x20>; 8741 dma-coherent; 8742 }; 8743 8744 compute-cb@2 { 8745 compatible = "qcom,fastrpc-compute-cb"; 8746 reg = <2>; 8747 iommus = <&apps_smmu 0x0c02 0x20>; 8748 dma-coherent; 8749 }; 8750 8751 compute-cb@3 { 8752 compatible = "qcom,fastrpc-compute-cb"; 8753 reg = <3>; 8754 iommus = <&apps_smmu 0x0c03 0x20>; 8755 dma-coherent; 8756 }; 8757 8758 compute-cb@4 { 8759 compatible = "qcom,fastrpc-compute-cb"; 8760 reg = <4>; 8761 iommus = <&apps_smmu 0x0c04 0x20>; 8762 dma-coherent; 8763 }; 8764 8765 compute-cb@5 { 8766 compatible = "qcom,fastrpc-compute-cb"; 8767 reg = <5>; 8768 iommus = <&apps_smmu 0x0c05 0x20>; 8769 dma-coherent; 8770 }; 8771 8772 compute-cb@6 { 8773 compatible = "qcom,fastrpc-compute-cb"; 8774 reg = <6>; 8775 iommus = <&apps_smmu 0x0c06 0x20>; 8776 dma-coherent; 8777 }; 8778 8779 compute-cb@7 { 8780 compatible = "qcom,fastrpc-compute-cb"; 8781 reg = <7>; 8782 iommus = <&apps_smmu 0x0c07 0x20>; 8783 dma-coherent; 8784 }; 8785 8786 compute-cb@8 { 8787 compatible = "qcom,fastrpc-compute-cb"; 8788 reg = <8>; 8789 iommus = <&apps_smmu 0x0c08 0x20>; 8790 dma-coherent; 8791 }; 8792 8793 /* note: compute-cb@9 is secure */ 8794 8795 compute-cb@10 { 8796 compatible = "qcom,fastrpc-compute-cb"; 8797 reg = <10>; 8798 iommus = <&apps_smmu 0x0c0c 0x20>; 8799 dma-coherent; 8800 }; 8801 8802 compute-cb@11 { 8803 compatible = "qcom,fastrpc-compute-cb"; 8804 reg = <11>; 8805 iommus = <&apps_smmu 0x0c0d 0x20>; 8806 dma-coherent; 8807 }; 8808 8809 compute-cb@12 { 8810 compatible = "qcom,fastrpc-compute-cb"; 8811 reg = <12>; 8812 iommus = <&apps_smmu 0x0c0e 0x20>; 8813 dma-coherent; 8814 }; 8815 8816 compute-cb@13 { 8817 compatible = "qcom,fastrpc-compute-cb"; 8818 reg = <13>; 8819 iommus = <&apps_smmu 0x0c0f 0x20>; 8820 dma-coherent; 8821 }; 8822 }; 8823 }; 8824 }; 8825 }; 8826 8827 timer { 8828 compatible = "arm,armv8-timer"; 8829 8830 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8831 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8832 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8833 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8834 }; 8835 8836 thermal_zones: thermal-zones { 8837 aoss0-thermal { 8838 thermal-sensors = <&tsens0 0>; 8839 8840 trips { 8841 trip-point0 { 8842 temperature = <90000>; 8843 hysteresis = <2000>; 8844 type = "hot"; 8845 }; 8846 8847 aoss0-critical { 8848 temperature = <115000>; 8849 hysteresis = <1000>; 8850 type = "critical"; 8851 }; 8852 }; 8853 }; 8854 8855 cpu0-0-top-thermal { 8856 thermal-sensors = <&tsens0 1>; 8857 8858 trips { 8859 cpu-critical { 8860 temperature = <115000>; 8861 hysteresis = <1000>; 8862 type = "critical"; 8863 }; 8864 }; 8865 }; 8866 8867 cpu0-0-btm-thermal { 8868 thermal-sensors = <&tsens0 2>; 8869 8870 trips { 8871 cpu-critical { 8872 temperature = <115000>; 8873 hysteresis = <1000>; 8874 type = "critical"; 8875 }; 8876 }; 8877 }; 8878 8879 cpu0-1-top-thermal { 8880 thermal-sensors = <&tsens0 3>; 8881 8882 trips { 8883 cpu-critical { 8884 temperature = <115000>; 8885 hysteresis = <1000>; 8886 type = "critical"; 8887 }; 8888 }; 8889 }; 8890 8891 cpu0-1-btm-thermal { 8892 thermal-sensors = <&tsens0 4>; 8893 8894 trips { 8895 cpu-critical { 8896 temperature = <115000>; 8897 hysteresis = <1000>; 8898 type = "critical"; 8899 }; 8900 }; 8901 }; 8902 8903 cpu0-2-top-thermal { 8904 thermal-sensors = <&tsens0 5>; 8905 8906 trips { 8907 cpu-critical { 8908 temperature = <115000>; 8909 hysteresis = <1000>; 8910 type = "critical"; 8911 }; 8912 }; 8913 }; 8914 8915 cpu0-2-btm-thermal { 8916 thermal-sensors = <&tsens0 6>; 8917 8918 trips { 8919 cpu-critical { 8920 temperature = <115000>; 8921 hysteresis = <1000>; 8922 type = "critical"; 8923 }; 8924 }; 8925 }; 8926 8927 cpu0-3-top-thermal { 8928 thermal-sensors = <&tsens0 7>; 8929 8930 trips { 8931 cpu-critical { 8932 temperature = <115000>; 8933 hysteresis = <1000>; 8934 type = "critical"; 8935 }; 8936 }; 8937 }; 8938 8939 cpu0-3-btm-thermal { 8940 thermal-sensors = <&tsens0 8>; 8941 8942 trips { 8943 cpu-critical { 8944 temperature = <115000>; 8945 hysteresis = <1000>; 8946 type = "critical"; 8947 }; 8948 }; 8949 }; 8950 8951 cpuss0-top-thermal { 8952 thermal-sensors = <&tsens0 9>; 8953 8954 trips { 8955 cpuss2-critical { 8956 temperature = <115000>; 8957 hysteresis = <1000>; 8958 type = "critical"; 8959 }; 8960 }; 8961 }; 8962 8963 cpuss0-btm-thermal { 8964 thermal-sensors = <&tsens0 10>; 8965 8966 trips { 8967 cpuss2-critical { 8968 temperature = <115000>; 8969 hysteresis = <1000>; 8970 type = "critical"; 8971 }; 8972 }; 8973 }; 8974 8975 mem-thermal { 8976 thermal-sensors = <&tsens0 11>; 8977 8978 trips { 8979 trip-point0 { 8980 temperature = <90000>; 8981 hysteresis = <2000>; 8982 type = "hot"; 8983 }; 8984 8985 mem-critical { 8986 temperature = <115000>; 8987 hysteresis = <0>; 8988 type = "critical"; 8989 }; 8990 }; 8991 }; 8992 8993 video-thermal { 8994 thermal-sensors = <&tsens0 12>; 8995 8996 trips { 8997 trip-point0 { 8998 temperature = <90000>; 8999 hysteresis = <2000>; 9000 type = "hot"; 9001 }; 9002 9003 video-critical { 9004 temperature = <115000>; 9005 hysteresis = <1000>; 9006 type = "critical"; 9007 }; 9008 }; 9009 }; 9010 9011 aoss1-thermal { 9012 thermal-sensors = <&tsens1 0>; 9013 9014 trips { 9015 trip-point0 { 9016 temperature = <90000>; 9017 hysteresis = <2000>; 9018 type = "hot"; 9019 }; 9020 9021 aoss0-critical { 9022 temperature = <115000>; 9023 hysteresis = <1000>; 9024 type = "critical"; 9025 }; 9026 }; 9027 }; 9028 9029 cpu1-0-top-thermal { 9030 thermal-sensors = <&tsens1 1>; 9031 9032 trips { 9033 cpu-critical { 9034 temperature = <115000>; 9035 hysteresis = <1000>; 9036 type = "critical"; 9037 }; 9038 }; 9039 }; 9040 9041 cpu1-0-btm-thermal { 9042 thermal-sensors = <&tsens1 2>; 9043 9044 trips { 9045 cpu-critical { 9046 temperature = <115000>; 9047 hysteresis = <1000>; 9048 type = "critical"; 9049 }; 9050 }; 9051 }; 9052 9053 cpu1-1-top-thermal { 9054 thermal-sensors = <&tsens1 3>; 9055 9056 trips { 9057 cpu-critical { 9058 temperature = <115000>; 9059 hysteresis = <1000>; 9060 type = "critical"; 9061 }; 9062 }; 9063 }; 9064 9065 cpu1-1-btm-thermal { 9066 thermal-sensors = <&tsens1 4>; 9067 9068 trips { 9069 cpu-critical { 9070 temperature = <115000>; 9071 hysteresis = <1000>; 9072 type = "critical"; 9073 }; 9074 }; 9075 }; 9076 9077 cpu1-2-top-thermal { 9078 thermal-sensors = <&tsens1 5>; 9079 9080 trips { 9081 cpu-critical { 9082 temperature = <115000>; 9083 hysteresis = <1000>; 9084 type = "critical"; 9085 }; 9086 }; 9087 }; 9088 9089 cpu1-2-btm-thermal { 9090 thermal-sensors = <&tsens1 6>; 9091 9092 trips { 9093 cpu-critical { 9094 temperature = <115000>; 9095 hysteresis = <1000>; 9096 type = "critical"; 9097 }; 9098 }; 9099 }; 9100 9101 cpu1-3-top-thermal { 9102 thermal-sensors = <&tsens1 7>; 9103 9104 trips { 9105 cpu-critical { 9106 temperature = <115000>; 9107 hysteresis = <1000>; 9108 type = "critical"; 9109 }; 9110 }; 9111 }; 9112 9113 cpu1-3-btm-thermal { 9114 thermal-sensors = <&tsens1 8>; 9115 9116 trips { 9117 cpu-critical { 9118 temperature = <115000>; 9119 hysteresis = <1000>; 9120 type = "critical"; 9121 }; 9122 }; 9123 }; 9124 9125 cpuss1-top-thermal { 9126 thermal-sensors = <&tsens1 9>; 9127 9128 trips { 9129 cpuss2-critical { 9130 temperature = <115000>; 9131 hysteresis = <1000>; 9132 type = "critical"; 9133 }; 9134 }; 9135 }; 9136 9137 cpuss1-btm-thermal { 9138 thermal-sensors = <&tsens1 10>; 9139 9140 trips { 9141 cpuss2-critical { 9142 temperature = <115000>; 9143 hysteresis = <1000>; 9144 type = "critical"; 9145 }; 9146 }; 9147 }; 9148 9149 aoss2-thermal { 9150 thermal-sensors = <&tsens2 0>; 9151 9152 trips { 9153 trip-point0 { 9154 temperature = <90000>; 9155 hysteresis = <2000>; 9156 type = "hot"; 9157 }; 9158 9159 aoss0-critical { 9160 temperature = <115000>; 9161 hysteresis = <1000>; 9162 type = "critical"; 9163 }; 9164 }; 9165 }; 9166 9167 cpu2-0-top-thermal { 9168 thermal-sensors = <&tsens2 1>; 9169 9170 trips { 9171 cpu-critical { 9172 temperature = <115000>; 9173 hysteresis = <1000>; 9174 type = "critical"; 9175 }; 9176 }; 9177 }; 9178 9179 cpu2-0-btm-thermal { 9180 thermal-sensors = <&tsens2 2>; 9181 9182 trips { 9183 cpu-critical { 9184 temperature = <115000>; 9185 hysteresis = <1000>; 9186 type = "critical"; 9187 }; 9188 }; 9189 }; 9190 9191 cpu2-1-top-thermal { 9192 thermal-sensors = <&tsens2 3>; 9193 9194 trips { 9195 cpu-critical { 9196 temperature = <115000>; 9197 hysteresis = <1000>; 9198 type = "critical"; 9199 }; 9200 }; 9201 }; 9202 9203 cpu2-1-btm-thermal { 9204 thermal-sensors = <&tsens2 4>; 9205 9206 trips { 9207 cpu-critical { 9208 temperature = <115000>; 9209 hysteresis = <1000>; 9210 type = "critical"; 9211 }; 9212 }; 9213 }; 9214 9215 cpu2-2-top-thermal { 9216 thermal-sensors = <&tsens2 5>; 9217 9218 trips { 9219 cpu-critical { 9220 temperature = <115000>; 9221 hysteresis = <1000>; 9222 type = "critical"; 9223 }; 9224 }; 9225 }; 9226 9227 cpu2-2-btm-thermal { 9228 thermal-sensors = <&tsens2 6>; 9229 9230 trips { 9231 cpu-critical { 9232 temperature = <115000>; 9233 hysteresis = <1000>; 9234 type = "critical"; 9235 }; 9236 }; 9237 }; 9238 9239 cpu2-3-top-thermal { 9240 thermal-sensors = <&tsens2 7>; 9241 9242 trips { 9243 cpu-critical { 9244 temperature = <115000>; 9245 hysteresis = <1000>; 9246 type = "critical"; 9247 }; 9248 }; 9249 }; 9250 9251 cpu2-3-btm-thermal { 9252 thermal-sensors = <&tsens2 8>; 9253 9254 trips { 9255 cpu-critical { 9256 temperature = <115000>; 9257 hysteresis = <1000>; 9258 type = "critical"; 9259 }; 9260 }; 9261 }; 9262 9263 cpuss2-top-thermal { 9264 thermal-sensors = <&tsens2 9>; 9265 9266 trips { 9267 cpuss2-critical { 9268 temperature = <115000>; 9269 hysteresis = <1000>; 9270 type = "critical"; 9271 }; 9272 }; 9273 }; 9274 9275 cpuss2-btm-thermal { 9276 thermal-sensors = <&tsens2 10>; 9277 9278 trips { 9279 cpuss2-critical { 9280 temperature = <115000>; 9281 hysteresis = <1000>; 9282 type = "critical"; 9283 }; 9284 }; 9285 }; 9286 9287 aoss3-thermal { 9288 thermal-sensors = <&tsens3 0>; 9289 9290 trips { 9291 trip-point0 { 9292 temperature = <90000>; 9293 hysteresis = <2000>; 9294 type = "hot"; 9295 }; 9296 9297 aoss0-critical { 9298 temperature = <115000>; 9299 hysteresis = <1000>; 9300 type = "critical"; 9301 }; 9302 }; 9303 }; 9304 9305 nsp0-thermal { 9306 thermal-sensors = <&tsens3 1>; 9307 9308 trips { 9309 trip-point0 { 9310 temperature = <90000>; 9311 hysteresis = <2000>; 9312 type = "hot"; 9313 }; 9314 9315 nsp0-critical { 9316 temperature = <115000>; 9317 hysteresis = <1000>; 9318 type = "critical"; 9319 }; 9320 }; 9321 }; 9322 9323 nsp1-thermal { 9324 thermal-sensors = <&tsens3 2>; 9325 9326 trips { 9327 trip-point0 { 9328 temperature = <90000>; 9329 hysteresis = <2000>; 9330 type = "hot"; 9331 }; 9332 9333 nsp1-critical { 9334 temperature = <115000>; 9335 hysteresis = <1000>; 9336 type = "critical"; 9337 }; 9338 }; 9339 }; 9340 9341 nsp2-thermal { 9342 thermal-sensors = <&tsens3 3>; 9343 9344 trips { 9345 trip-point0 { 9346 temperature = <90000>; 9347 hysteresis = <2000>; 9348 type = "hot"; 9349 }; 9350 9351 nsp2-critical { 9352 temperature = <115000>; 9353 hysteresis = <1000>; 9354 type = "critical"; 9355 }; 9356 }; 9357 }; 9358 9359 nsp3-thermal { 9360 thermal-sensors = <&tsens3 4>; 9361 9362 trips { 9363 trip-point0 { 9364 temperature = <90000>; 9365 hysteresis = <2000>; 9366 type = "hot"; 9367 }; 9368 9369 nsp3-critical { 9370 temperature = <115000>; 9371 hysteresis = <1000>; 9372 type = "critical"; 9373 }; 9374 }; 9375 }; 9376 9377 gpuss-0-thermal { 9378 polling-delay-passive = <200>; 9379 9380 thermal-sensors = <&tsens3 5>; 9381 9382 cooling-maps { 9383 map0 { 9384 trip = <&gpuss0_alert0>; 9385 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9386 }; 9387 }; 9388 9389 trips { 9390 gpuss0_alert0: trip-point0 { 9391 temperature = <95000>; 9392 hysteresis = <1000>; 9393 type = "passive"; 9394 }; 9395 9396 gpu-critical { 9397 temperature = <115000>; 9398 hysteresis = <1000>; 9399 type = "critical"; 9400 }; 9401 }; 9402 }; 9403 9404 gpuss-1-thermal { 9405 polling-delay-passive = <200>; 9406 9407 thermal-sensors = <&tsens3 6>; 9408 9409 cooling-maps { 9410 map0 { 9411 trip = <&gpuss1_alert0>; 9412 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9413 }; 9414 }; 9415 9416 trips { 9417 gpuss1_alert0: trip-point0 { 9418 temperature = <95000>; 9419 hysteresis = <1000>; 9420 type = "passive"; 9421 }; 9422 9423 gpu-critical { 9424 temperature = <115000>; 9425 hysteresis = <1000>; 9426 type = "critical"; 9427 }; 9428 }; 9429 }; 9430 9431 gpuss-2-thermal { 9432 polling-delay-passive = <200>; 9433 9434 thermal-sensors = <&tsens3 7>; 9435 9436 cooling-maps { 9437 map0 { 9438 trip = <&gpuss2_alert0>; 9439 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9440 }; 9441 }; 9442 9443 trips { 9444 gpuss2_alert0: trip-point0 { 9445 temperature = <95000>; 9446 hysteresis = <1000>; 9447 type = "passive"; 9448 }; 9449 9450 gpu-critical { 9451 temperature = <115000>; 9452 hysteresis = <1000>; 9453 type = "critical"; 9454 }; 9455 }; 9456 }; 9457 9458 gpuss-3-thermal { 9459 polling-delay-passive = <200>; 9460 9461 thermal-sensors = <&tsens3 8>; 9462 9463 cooling-maps { 9464 map0 { 9465 trip = <&gpuss3_alert0>; 9466 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9467 }; 9468 }; 9469 9470 trips { 9471 gpuss3_alert0: trip-point0 { 9472 temperature = <95000>; 9473 hysteresis = <1000>; 9474 type = "passive"; 9475 }; 9476 9477 gpu-critical { 9478 temperature = <115000>; 9479 hysteresis = <1000>; 9480 type = "critical"; 9481 }; 9482 }; 9483 }; 9484 9485 gpuss-4-thermal { 9486 polling-delay-passive = <200>; 9487 9488 thermal-sensors = <&tsens3 9>; 9489 9490 cooling-maps { 9491 map0 { 9492 trip = <&gpuss4_alert0>; 9493 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9494 }; 9495 }; 9496 9497 trips { 9498 gpuss4_alert0: trip-point0 { 9499 temperature = <95000>; 9500 hysteresis = <1000>; 9501 type = "passive"; 9502 }; 9503 9504 gpu-critical { 9505 temperature = <115000>; 9506 hysteresis = <1000>; 9507 type = "critical"; 9508 }; 9509 }; 9510 }; 9511 9512 gpuss-5-thermal { 9513 polling-delay-passive = <200>; 9514 9515 thermal-sensors = <&tsens3 10>; 9516 9517 cooling-maps { 9518 map0 { 9519 trip = <&gpuss5_alert0>; 9520 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9521 }; 9522 }; 9523 9524 trips { 9525 gpuss5_alert0: trip-point0 { 9526 temperature = <95000>; 9527 hysteresis = <1000>; 9528 type = "passive"; 9529 }; 9530 9531 gpu-critical { 9532 temperature = <115000>; 9533 hysteresis = <1000>; 9534 type = "critical"; 9535 }; 9536 }; 9537 }; 9538 9539 gpuss-6-thermal { 9540 polling-delay-passive = <200>; 9541 9542 thermal-sensors = <&tsens3 11>; 9543 9544 cooling-maps { 9545 map0 { 9546 trip = <&gpuss6_alert0>; 9547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9548 }; 9549 }; 9550 9551 trips { 9552 gpuss6_alert0: trip-point0 { 9553 temperature = <95000>; 9554 hysteresis = <1000>; 9555 type = "passive"; 9556 }; 9557 9558 gpu-critical { 9559 temperature = <115000>; 9560 hysteresis = <1000>; 9561 type = "critical"; 9562 }; 9563 }; 9564 }; 9565 9566 gpuss-7-thermal { 9567 polling-delay-passive = <200>; 9568 9569 thermal-sensors = <&tsens3 12>; 9570 9571 cooling-maps { 9572 map0 { 9573 trip = <&gpuss7_alert0>; 9574 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9575 }; 9576 }; 9577 9578 trips { 9579 gpuss7_alert0: trip-point0 { 9580 temperature = <95000>; 9581 hysteresis = <1000>; 9582 type = "passive"; 9583 }; 9584 9585 gpu-critical { 9586 temperature = <115000>; 9587 hysteresis = <1000>; 9588 type = "critical"; 9589 }; 9590 }; 9591 }; 9592 9593 camera0-thermal { 9594 thermal-sensors = <&tsens3 13>; 9595 9596 trips { 9597 trip-point0 { 9598 temperature = <90000>; 9599 hysteresis = <2000>; 9600 type = "hot"; 9601 }; 9602 9603 camera0-critical { 9604 temperature = <115000>; 9605 hysteresis = <1000>; 9606 type = "critical"; 9607 }; 9608 }; 9609 }; 9610 9611 camera1-thermal { 9612 thermal-sensors = <&tsens3 14>; 9613 9614 trips { 9615 trip-point0 { 9616 temperature = <90000>; 9617 hysteresis = <2000>; 9618 type = "hot"; 9619 }; 9620 9621 camera0-critical { 9622 temperature = <115000>; 9623 hysteresis = <1000>; 9624 type = "critical"; 9625 }; 9626 }; 9627 }; 9628 }; 9629}; 9630